KR20110051016A - Printed circuit board having vdd pads connected to each other - Google Patents

Printed circuit board having vdd pads connected to each other Download PDF

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Publication number
KR20110051016A
KR20110051016A KR1020090107658A KR20090107658A KR20110051016A KR 20110051016 A KR20110051016 A KR 20110051016A KR 1020090107658 A KR1020090107658 A KR 1020090107658A KR 20090107658 A KR20090107658 A KR 20090107658A KR 20110051016 A KR20110051016 A KR 20110051016A
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South Korea
Prior art keywords
vdd
printed circuit
circuit board
pads
package substrate
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KR1020090107658A
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Korean (ko)
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박주영
배효근
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삼성전기주식회사
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Priority to KR1020090107658A priority Critical patent/KR20110051016A/en
Publication of KR20110051016A publication Critical patent/KR20110051016A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PURPOSE: A printed circuit board including VDD pads is provided to stably operating a semiconductor chip by forming a connection type VDD pad on a package substrate mounting area. CONSTITUTION: A plurality of VDD pads(134) are mounted on a package substrate mounting area of a printed circuit board(130). Voltage is applied to a VDD terminal of the package substrate through the VDD pads. A circuit pattern(136) is connected to two or more VDD pads in which different voltage are applied. The VDD pads and a connection circuit pattern are integrally formed by the same manufacturing processes.

Description

연결형 ＶＤＤ 패드가 형성된 인쇄회로기판{Printed circuit board having VDD pads connected to each other}Printed circuit board having VDD pads connected to each other}

본 발명은 인쇄회로기판에 관련된다.The present invention relates to a printed circuit board.

휴대용 전자기기의 수요가 증가함에 따라 전자기기가 소형화되고 있고, 그에 따라 메인 인쇄회로기판 역시 소형화되며, 인쇄회로기판에 실장되는 칩의 집적도가 이슈화되고 있다.As demand for portable electronic devices increases, electronic devices become smaller, and thus, main printed circuit boards are also miniaturized, and integration of chips mounted on printed circuit boards is an issue.

메인 인쇄회로기판에 칩을 실장하기 위해 패키지기판(또는 리드프레임 기판)을 사용하게 되는데, 패키지기판은 반도체칩과 메인 인쇄회로기판을 연결해주며 집적도를 극대화하기 위한 인쇄회로기판이다.A package substrate (or lead frame substrate) is used to mount a chip on the main printed circuit board. The package substrate connects the semiconductor chip and the main printed circuit board and maximizes the integration degree.

반도체칩이 메인 인쇄회로기판에 실장됨에 있어서, 그 기능을 발휘하기 위해 안정적인 전압의 공급이 요구된다. 반도체칩에 대한 전압의 공급은 메인 인쇄회로기판의 패키지기판 실장영역에 형성된 VDD 패드로부터 패키지기판의 VDD 단자를 통해 반도체칩에 전달된다. 반도체칩은 패키지기판과 와이어 본딩으로 연결되어 있으며 패키지기판의 VDD 단자로부터 전압을 공급받는다.When the semiconductor chip is mounted on the main printed circuit board, it is required to supply a stable voltage in order to exhibit its function. The supply of voltage to the semiconductor chip is transferred from the VDD pad formed in the package board mounting area of the main printed circuit board to the semiconductor chip through the VDD terminal of the package board. The semiconductor chip is connected to the package substrate by wire bonding and receives a voltage from the VDD terminal of the package substrate.

도 1은 반도체칩(10)이 패키지기판(20)을 통해 메인 인쇄회로기판(30)에 실장된 모습을 도시하고 있다. 반도체칩(10)은 패키지기판(20)과 와이어 본딩을 통해 연결되어 있으며, 패키지기판(20)은 메인 인쇄회로기판(30)과 솔더볼 방식에 의해 연결될 수 있다.1 illustrates a state in which a semiconductor chip 10 is mounted on a main printed circuit board 30 through a package substrate 20. The semiconductor chip 10 is connected to the package substrate 20 through wire bonding, and the package substrate 20 may be connected to the main printed circuit board 30 by a solder ball method.

도 2는 메인 인쇄회로기판(30)에 형성된 종래의 패키지기판 실장영역(32)을 도시하고 있다. 패키지기판 실장영역(32)에는 패키지기판을 실장하기 위한 다수의 패드가 형성된다. 도 2에는 패키지기판에 전압을 공급하기 위한 VDD 패드(34)가 별도로 분리되어 형성되어 있다.2 shows a conventional package board mounting area 32 formed on the main printed circuit board 30. In the package substrate mounting area 32, a plurality of pads for mounting the package substrate are formed. In FIG. 2, the VDD pad 34 for supplying a voltage to the package substrate is separately formed.

별도로 분리되어 있는 VDD 패드(34)는 안정적인 전압을 공급하는데 한계를 가지며, 예컨대 메인 인쇄회로기판에 실장되는 반도체칩이 무선주파수 CMOS 전력증폭기인 경우 밴드별 하모닉 특성 및 포워드 아이솔레이션(forword isolation) 특성의 변동이 심한 문제점이 있다.The separate VDD pad 34 has a limitation in supplying a stable voltage. For example, when the semiconductor chip mounted on the main printed circuit board is a radio frequency CMOS power amplifier, the harmonic characteristics and the word isolation characteristics of each band are used. There is a problem with fluctuations.

본 발명은 상기와 같은 문제점을 해결하기 위해 창안된 것으로서, 패키지기판에 안정한 전압을 공급하기 위해 패키지기판 실장영역에 연결형 VDD 패드가 형성된 인쇄회로기판을 제안한다. The present invention has been made to solve the above problems, and proposes a printed circuit board having a VDD pad connected to the package board mounting area in order to supply a stable voltage to the package board.

본 발명은 연결형 VDD 패드가 형성된 인쇄회로기판에 관련되며, 인쇄회로기판에 있어서, 상기 인쇄회로기판의 패키지기판 실장영역에 형성된 다수의 VDD 패드, 및 상기 다수의 VDD 패드에서 2 이상의 VDD 패드를 연결하는 연결 회로패턴을 포함한다.The present invention relates to a printed circuit board on which a connected VDD pad is formed, wherein the printed circuit board includes a plurality of VDD pads formed in a package board mounting area of the printed circuit board, and two or more VDD pads connected to the plurality of VDD pads. It includes a connection circuit pattern.

또한, 본 발명은 상기 연결 회로패턴은 상기 다수의 VDD 패드에서 인접하는 2 이상의 VDD 패드를 연결하는 것을 특징으로 한다.In addition, the present invention is characterized in that the connection circuit pattern connects two or more adjacent VDD pads in the plurality of VDD pads.

또한, 본 발명은 상기 연결 회로패턴은 인접하는 상기 2 이상의 VDD 패드의 동일선 상에 위치한 일측을 연결하는 라인 형상을 갖는 것을 특징으로 한다.In addition, the present invention is characterized in that the connection circuit pattern has a line shape for connecting one side located on the same line of the two or more adjacent VDD pads.

또한, 본 발명은 상기 연결 회로패턴은 상기 다수의 VDD 패드를 모두 연결하는 것을 특징으로 한다.In addition, the connection circuit pattern is characterized in that for connecting all of the plurality of VDD pads.

또한, 본 발명은 상기 패키지기판 실장영역에 반도체칩이 실장된 패키지기판이 실장되고, 상기 반도체칩은 무선주파수 CMOS 전력증폭기인 것을 특징으로 한다.In addition, the present invention is characterized in that a package substrate on which a semiconductor chip is mounted is mounted in the package substrate mounting region, and the semiconductor chip is a radio frequency CMOS power amplifier.

본 발명의 특징 및 이점들은 첨부도면에 의거한 다음의 상세한 설명으로 더 욱 명백해질 것이다.The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

이에 앞서 본 명세서 및 청구범위에 사용된 용어나 단어는 통상적이고 사전적인 의미로 해석되어서는 아니되며, 발명자가 그 자신의 발명을 가장 최선의 방법으로 설명하기 위해 용어의 개념을 적절하게 정의할 수 있다는 원칙에 입각하여 본 발명의 기술적 사상에 부합되는 의미와 개념으로 해석되어야만 한다.Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

본 발명에 따른 인쇄회로기판은 패키지기판 실장영역에 연결형 VDD 패드를 형성함으로써 패키지기판에 안정된 전압을 공급할 수 있고, 그에 따라 패키지기판에 실장된 반도체칩의 구동을 안정적으로 구현할 수 있다.The printed circuit board according to the present invention can supply a stable voltage to the package board by forming a connection type VDD pad in the package board mounting area, thereby stably driving the driving of the semiconductor chip mounted on the package board.

특히, 패키지기판에 실장된 반도체칩이 무선주파수 CMOS 전력증폭기인 경우 밴드별 하모닉이 강화되며, 높은 밴드영역에서 포워드 아이솔레이션 특성이 강화된다.In particular, when the semiconductor chip mounted on the package substrate is a radio frequency CMOS power amplifier, the harmonics of each band are enhanced, and the forward isolation characteristics are enhanced in the high band region.

본 발명의 목적, 특정한 장점들 및 신규한 특징들은 첨부된 도면들과 연관되어지는 이하의 상세한 설명과 바람직한 실시예들로부터 더욱 명백해질 것이다. 본 명세서에서 각 도면의 구성요소들에 참조번호를 부가함에 있어서, 동일한 구성 요소들에 한해서는 비록 다른 도면상에 표시되더라도 가능한 한 동일한 번호를 가지도록 하고 있음에 유의하여야 한다. 또한, 본 발명을 설명함에 있어서, 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명은 생략한다. The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and the preferred embodiments associated with the accompanying drawings. In the present specification, in adding reference numerals to the components of each drawing, it should be noted that the same components as possible, even if displayed on different drawings have the same number as possible. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 반도체칩이 실장된 패키지기판의 평면도이며, 도 4는 본 발명의 바람직한 실시예에 따른 연결형 VDD 패드가 형성된 인쇄회로기판(이하 인쇄회로기판)에 구성된 패키지기판 실장영역을 도시한 평면도이다. 이하, 이를 참고하여 본 발명에 따른 인쇄회로기판을 설명하기로 한다.3 is a plan view of a package board on which semiconductor chips are mounted, and FIG. 4 is a plan view showing a package board mounting area formed on a printed circuit board (hereinafter, referred to as a printed circuit board) on which a connected VDD pad is formed according to a preferred embodiment of the present invention. . Hereinafter, a printed circuit board according to the present invention will be described with reference to this.

도 3에 도시된 것과 같이, 반도체칩(10)이 패키지기판(20)에 실장되어 있으며, 반도체칩(10)의 단자들은 패키지기판의 VDD 단자(25)들과 와이어본딩 되어있다. 인쇄회로기판에 반도체칩(10)을 실장함에 있어서, 반도체칩 실장의 집적화를 위해 패키지기판(20)을 이용한다. 반도체칩(10)은 패키지기판(20)의 VDD 단자(25)를 통해 인가되는 전압으로 작동된다. 따라서, 패키지기판(20)의 VDD 단자(25)를 통해 인가되는 전압이 안정화되느냐의 여부에 따라 반도체칩(10)의 안정성이 결정된다.As shown in FIG. 3, the semiconductor chip 10 is mounted on the package substrate 20, and the terminals of the semiconductor chip 10 are wire bonded to the VDD terminals 25 of the package substrate. In mounting the semiconductor chip 10 on a printed circuit board, the package substrate 20 is used for integration of the semiconductor chip mounting. The semiconductor chip 10 is operated at a voltage applied through the VDD terminal 25 of the package substrate 20. Therefore, the stability of the semiconductor chip 10 is determined depending on whether or not the voltage applied through the VDD terminal 25 of the package substrate 20 is stabilized.

이때, 패키지기판(20)의 VDD 단자(25)를 통해 인가되는 전압의 안정성 여부는 패키지기판 실장영역에 형성된 VDD 패드의 전압과 관계되고, 이는 도 4를 참고하여 후술한다.In this case, the stability of the voltage applied through the VDD terminal 25 of the package substrate 20 is related to the voltage of the VDD pad formed in the package substrate mounting region, which will be described later with reference to FIG. 4.

도 4에 도시된 것과 같이, 본 발명에 따른 인쇄회로기판(130)은 패키지기판 실장영역(132)에 다수의 VDD 패드(134)가 형성되고, 다수의 VDD 패드(134)에서 2 이상의 VDD 패드(134)를 연결하는 연결 회로패턴(136)을 포함하는 것을 특징으로 한다.As shown in FIG. 4, in the printed circuit board 130 according to the present invention, a plurality of VDD pads 134 are formed in the package board mounting region 132, and two or more VDD pads in the plurality of VDD pads 134. It characterized in that it comprises a connection circuit pattern 136 for connecting (134).

도 4에는 6개의 VDD 패드(134)가 도시되어 있으나 이는 하나의 예시에 불과하고 이는 변형되어 실시될 수 있다.Although six VDD pads 134 are shown in FIG. 4, this is merely an example and may be modified.

이때, 상술한 것과 같이 패키지기판은 인쇄회로기판(130)의 패키지기판 실장영역(132)에 실장되고, 도 3에 도시된 것과 같이 패키지 기판(20)의 VDD 단자(25)는 패키지기판 실장영역(132)에 형성된 VDD 패드(134)에 접속한다. 그 접속방법은 솔더볼 방식과 같이 공지된 사항이므로 상세한 설명은 생략한다.At this time, as described above, the package substrate is mounted on the package substrate mounting region 132 of the printed circuit board 130, and as shown in FIG. 3, the VDD terminal 25 of the package substrate 20 is a package substrate mounting region. And a VDD pad 134 formed at 132. The connection method is a known matter, such as a solder ball method, so a detailed description thereof will be omitted.

여기서, 다수의 VDD 패드(134)를 통해 패키지기판(20)의 VDD 단자(25)에 전압이 전달된다. VDD 패드(134)에 전달되는 전압은 외부전압이 인쇄회로기판(130)의 전원층(예컨대, 다층 인쇄회로기판)을 통해 인가되면, 인쇄회로기판(130)에 형성된 다수의 회로패턴을 통해 VDD 패드(134)로 전달된다. Here, a voltage is transmitted to the VDD terminal 25 of the package substrate 20 through the plurality of VDD pads 134. When the external voltage is applied through the power supply layer (eg, the multilayered printed circuit board) of the printed circuit board 130, the VDD pad 134 transmits VDD through a plurality of circuit patterns formed on the printed circuit board 130. Delivered to pad 134.

한편, 전원층과 다수의 VDD 패드(134) 사이에 형성된 회로패턴의 차이에 따라 각각의 VDD 패드(134)에서 갖는 전압의 세기는 달라질 수 있다.On the other hand, according to the difference in the circuit pattern formed between the power supply layer and the plurality of VDD pads 134, the strength of the voltage of each VDD pad 134 may vary.

이때, 연결 회로패턴(136)은 2 이상의 VDD 패드(134)를 연결한다. 연결 회로패턴(136)은 전압의 세기가 상이한 2 이상의 VDD 패드(134)를 연결하여 2 이상의 VDD 패드(134)가 갖는 전압의 세기를 동일하게 해준다. In this case, the connection circuit pattern 136 connects two or more VDD pads 134. The connection circuit pattern 136 connects two or more VDD pads 134 having different voltage intensities to equalize the voltage of two or more VDD pads 134.

예를 들면, 도 4에 도시된 것과 달리 연결 회로패턴은 첫 번째 VDD 패 드(134-1)과 세 번째 VDD 패드(134-3)를 선택적으로 연결할 수 있다. 따라서, 그에 연결되는 VDD 단자(25-1, 25-3)에는 동일한 전압이 인가되고, 전압의 변동이 감소한다.For example, unlike in FIG. 4, the connection circuit pattern may selectively connect the first VDD pad 134-1 and the third VDD pad 134-3. Therefore, the same voltage is applied to the VDD terminals 25-1 and 25-3 connected thereto, and the variation in voltage is reduced.

또한, 연결 회로패턴(136)은 인접하는 2 이상의 VDD 패드(134)를 연결하는 것을 특징으로 한다. 도 4에는 인접하는 3개의 VDD 패드(134-1, 134-2, 134-3)가 연결 회로패턴(136-1, 136-2)을 통해 연결되어 있으나 이는 하나의 예시에 불과하며, 연결되는 VDD 패드의 개수는 변형되어 실시될 수 있다.In addition, the connection circuit pattern 136 connects two or more adjacent VDD pads 134. In FIG. 4, three adjacent VDD pads 134-1, 134-2, and 134-3 are connected through the connection circuit patterns 136-1 and 136-2, but this is only one example. The number of VDD pads may be modified.

이때 3개의 VDD 패드(134-1, 134-2, 134-3) 역시 동일한 전압을 갖게 된다. 따라서 이에 연결된 VDD 단자(25-1, 25-2, 25-3)에 인가되는 전압의 세기는 동일하고, VDD 단자(25-1, 25-2, 25-3)에 인가되는 전압은 개별적으로 분리된 VDD 패드를 통해 인가되는 것보다 변동이 약하고 안정된다. At this time, the three VDD pads 134-1, 134-2, and 134-3 also have the same voltage. Therefore, the voltages applied to the VDD terminals 25-1, 25-2, and 25-3 connected thereto are the same, and the voltages applied to the VDD terminals 25-1, 25-2, and 25-3 are individually The variation is weaker and more stable than that applied through a separate VDD pad.

그리고, VDD 패드(134)와 연결 회로패턴(136)은 패키지기판 실장영역(132)을 형성함에 있어 동일한 제조공정에 따라 일체로 형성될 수 있는데, 인접하는 VDD 패드(134)를 연결하는 연결 회로패턴(136)은 그 구조가 간단하여 제조 공정이 단순해지는 장점이 있다.In addition, the VDD pad 134 and the connection circuit pattern 136 may be integrally formed according to the same manufacturing process in forming the package substrate mounting region 132, and the connection circuit connecting the adjacent VDD pads 134 to each other. The pattern 136 has the advantage that the structure is simple and the manufacturing process is simplified.

또한, 연결 회로패턴(136)은 인접하는 상기 2 이상의 VDD 패드(134)의 동일선 상에 위치한 일측을 연결하는 라인 형상을 갖는 것을 특징으로 한다. In addition, the connection circuit pattern 136 has a line shape for connecting one side located on the same line of the two or more adjacent VDD pads 134.

연결 회로패턴(136)은 다수의 VDD 패드(134)에 대해 인접하는 VDD 패드 사이 에 위치하여 인접하는 VDD 패드를 연결하면 그 효과를 발휘할 수 있다. 그러나, 도 4에 도시된 것과 같이, 연결 회로패턴(136)이 3개의 VDD 패드(134-1, 134-2, 134-3)의 동일선 상에 위치한 일측을 연결하는 라인 형상의 연결 회로패턴(136-1, 136-2)을 가짐으로써 자체 저항값이 낮아지므로 안정된 전압을 전달할 수 있으며, 연결 회로패턴(136)의 제조공정이 단순해진다.The connection circuit pattern 136 may be positioned between adjacent VDD pads with respect to the plurality of VDD pads 134 to connect the adjacent VDD pads. However, as shown in FIG. 4, the connecting circuit pattern 136 connects one side of the three VDD pads 134-1, 134-2, and 134-3 connected to one side on the same line. By having 136-1 and 136-2, the self-resistance value is lowered, so that a stable voltage can be transmitted, and the manufacturing process of the connection circuit pattern 136 is simplified.

한편, 도 4에는 연결 회로패턴(136)이 패키지기판 실장영역(132)의 내측 방향으로 동일선 상에서 인접하는 VDD 패드(134)를 연결하는 라인 형상을 갖고 있으나 이는 하나의 예시에 불과하며, 연결 회로패턴(136)은 패키지기판 실장영역(132)의 외측 방향으로 동일선 상에서 인접하는 VDD 패드(134)를 연결하는 라인 형상을 가질 수도 있다.Meanwhile, in FIG. 4, the connection circuit pattern 136 has a line shape for connecting adjacent VDD pads 134 on the same line in the inner direction of the package substrate mounting region 132, but this is only one example. The pattern 136 may have a line shape that connects adjacent VDD pads 134 on the same line in the outer direction of the package substrate mounting region 132.

그리고, 패키지기판 실장영역(132)에 반도체칩(10)이 실장된 패키지기판(20)이 실장될 때, 반도체칩(10)이 무선주파수 CMOS 전력증폭기(이하 CMOS 전력증폭기)인 경우, CMOS 전력증폭기에 연결 회로패턴(136)을 통해 연결된 2 이상의 VDD 패드(134)를 통해 전압이 인가되므로 CMOS 전력증폭기의 밴드별 하모닉이 강화되며, 높은 밴드영역에서 포워드 아이솔레이션 특성이 강화된다.When the package substrate 20 in which the semiconductor chip 10 is mounted in the package substrate mounting region 132 is mounted, the CMOS power is a CMOS power amplifier (hereinafter referred to as a CMOS power amplifier). Since voltage is applied through two or more VDD pads 134 connected to the amplifier through the circuit pattern 136, the harmonics of each band of the CMOS power amplifier are enhanced, and the forward isolation characteristic is enhanced in the high band region.

도 5는 본 발명의 바람직한 또 다른 실시예에 따른 인쇄회로기판(230)에 구성된 패키지기판 실장영역(232)을 도시한 평면도이다.FIG. 5 is a plan view illustrating a package board mounting area 232 configured in a printed circuit board 230 according to another exemplary embodiment of the present invention.

도 5에 도시된 것과 같이, 연결 회로패턴(236)은 다수의 VDD 패드(234)를 모 두 연결하는 것을 특징으로 한다. 연결 회로패턴(236)에 의해 다수의 VDD 패드(234)는 모두 동일한 전압을 갖게 되고, 그에 따라 패키지기판(20)의 VDD 단자(25)에는 동일한 전압이 인가되므로 VDD 단자(25)에 인가되는 전압의 변화가 줄어들고 안정화된다.As shown in FIG. 5, the connection circuit pattern 236 connects all of the plurality of VDD pads 234. The plurality of VDD pads 234 have the same voltage by the connection circuit pattern 236, and thus the same voltage is applied to the VDD terminal 25 of the package substrate 20, thereby being applied to the VDD terminal 25. The change in voltage is reduced and stabilized.

한편 본 발명은 기재된 실시예에 한정되는 것이 아니고, 본 발명의 사상 및 범위를 벗어나지 않고 다양하게 수정 및 변형을 할 수 있음은 이 기술 분야에서 통상의 지식을 가진 자에게는 자명하다. 따라서, 그러한 변형예 또는 수정예들은 본 발명의 특허청구범위에 속한다 해야 할 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Therefore, such modifications or variations will have to belong to the claims of the present invention.

도 1은 반도체칩을 실장한 패키지기판이 실장된 인쇄회로기판에 대한 단면도이다.1 is a cross-sectional view of a printed circuit board on which a package board on which a semiconductor chip is mounted is mounted.

도 2는 종래의 인쇄회로기판에 구성된 패키지기판 실장영역을 도시한 평면도이다.2 is a plan view illustrating a package board mounting area configured in a conventional printed circuit board.

도 3은 반도체칩이 실장된 패키지기판의 평면도이다.3 is a plan view of a package substrate on which semiconductor chips are mounted.

도 4는 본 발명의 바람직한 실시예에 따른 인쇄회로기판에 대한 패키지기판 실장영역을 도시한 평면도이다.4 is a plan view illustrating a package board mounting area for a printed circuit board according to an exemplary embodiment of the present invention.

도 5는 본 발명의 바람직한 또 다른 실시예에 따른 인쇄회로기판에 구성된 패키지기판 실장영역을 도시한 평면도이다.FIG. 5 is a plan view illustrating a package board mounting area configured in a printed circuit board according to another exemplary embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10 : 반도체칩 20 : 패키지기판(리드프레임 기판)10: semiconductor chip 20: package substrate (lead frame substrate)

25 : VDD 단자 30, 130, 230 : 인쇄회로기판 25: VDD terminal 30, 130, 230: printed circuit board

32, 132, 232 : 패키지기판 실장영역 34, 134, 234 : VDD 패드32, 132, 232: Package board mounting area 34, 134, 234: VDD pad

136, 236 : 연결 회로패턴136, 236: connecting circuit pattern

Claims (5)

인쇄회로기판에 있어서,In a printed circuit board, 상기 인쇄회로기판의 패키지기판 실장영역에 형성된 다수의 VDD 패드; 및A plurality of VDD pads formed in the package board mounting area of the printed circuit board; And 상기 다수의 VDD 패드에서 2 이상의 VDD 패드를 연결하는 연결 회로패턴을 포함하는 것을 특징으로 하는 연결형 VDD 패드가 형성된 인쇄회로기판.And a connection circuit pattern for connecting two or more VDD pads in the plurality of VDD pads. 청구항 1에 있어서,The method according to claim 1, 상기 연결 회로패턴은 상기 다수의 VDD 패드에서 인접하는 2 이상의 VDD 패드를 연결하는 것을 특징으로 하는 연결형 VDD 패드가 형성된 인쇄회로기판.The connection circuit pattern is a printed circuit board having a connection type VDD pad, characterized in that for connecting two or more adjacent VDD pads in the plurality of VDD pads. 청구항 2에 있어서,The method according to claim 2, 상기 연결 회로패턴은 인접하는 상기 2 이상의 VDD 패드의 동일선 상에 위치한 일측을 연결하는 라인 형상을 갖는 것을 특징으로 하는 연결형 VDD 패드가 형성된 인쇄회로기판.The connection circuit pattern is a printed circuit board having a connection type VDD pad having a line shape for connecting one side located on the same line of the two or more adjacent VDD pads. 청구항 1에 있어서,The method according to claim 1, 상기 연결 회로패턴은 상기 다수의 VDD 패드를 모두 연결하는 것을 특징으로 하는 연결형 VDD 패드가 형성된 인쇄회로기판.The connection circuit pattern is a printed circuit board having a connection type VDD pad, characterized in that for connecting all the plurality of VDD pads. 청구항 1에 있어서,The method according to claim 1, 상기 패키지기판 실장영역에 반도체칩이 실장된 패키지기판이 실장되고, 상기 반도체칩은 무선주파수 CMOS 전력증폭기인 것을 특징으로 하는 연결형 VDD 패드가 형성된 인쇄회로기판.And a package board having a semiconductor chip mounted on the package board mounting area, wherein the semiconductor chip is a radio frequency CMOS power amplifier.
KR1020090107658A 2009-11-09 2009-11-09 Printed circuit board having vdd pads connected to each other KR20110051016A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105490671A (en) * 2014-10-01 2016-04-13 亚德诺半导体集团 High isolation wideband switch
CN105490671B (en) * 2014-10-01 2019-07-16 亚德诺半导体集团 High-isolation wideband switch

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105490671A (en) * 2014-10-01 2016-04-13 亚德诺半导体集团 High isolation wideband switch
CN105490671B (en) * 2014-10-01 2019-07-16 亚德诺半导体集团 High-isolation wideband switch

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