JP2006041061A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006041061A
JP2006041061A JP2004216533A JP2004216533A JP2006041061A JP 2006041061 A JP2006041061 A JP 2006041061A JP 2004216533 A JP2004216533 A JP 2004216533A JP 2004216533 A JP2004216533 A JP 2004216533A JP 2006041061 A JP2006041061 A JP 2006041061A
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semiconductor device
semiconductor chip
chip
capacitor
electrodes
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JP4370993B2 (en
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Shigeru Yokosuka
茂 横須加
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing the reduction in the noise eliminating capability of a capacitive element without being affected by the wire inductance while taking advantage of downsizing of the package. <P>SOLUTION: In the configuration of the semiconductor device 10, a semiconductor chip 4 with a plurality of electrode pads 3 formed thereto is mounted on the upper side of a semiconductor chip mount substrate 2, and a plurality of external connection ball electrodes 6 are formed to a lower side of the semiconductor chip mount substrate 2 to electrically connect a plurality of electrode pass corresponding to the ball electrodes. A capacitor chip 11 is laminated on the semiconductor chip 4 with its plural external connection pads 12 corresponding to a plurality of the electrode pads 3 of the semiconductor chip 4. The pads 3, 12 of the semiconductor chip 4 and the capacitor chip 11 corresponding to each other are connected electrically via a plurality of interconnection terminals 1 formed to the semiconductor chip mount substrate 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、半導体装置に係り、詳しくは、ノイズ除去用の複数の容量素子を形成した容量チップを、半導体チップに積層した半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a capacitor chip formed with a plurality of capacitor elements for noise removal is stacked on a semiconductor chip.

ＬＳＩ（Large Scale Integrated circuit:大規模集積回路）で代表される半導体装置が、携帯電話等の各種電子機器に広く使用されている。このような電子機器に用いられる半導体装置は、電子機器の小型化に対応するために高密度実装に適した構造のものが、例えばＢＧＡ（Ball Grid Array）方式の樹脂封止型半導体装置が好んで用いられている。図９は従来の同半導体装置を示す平面図、図１０は図９のＤ−Ｄ矢視断面図である。   A semiconductor device typified by an LSI (Large Scale Integrated circuit) is widely used in various electronic devices such as mobile phones. A semiconductor device used in such an electronic device has a structure suitable for high-density mounting in order to cope with the downsizing of the electronic device. For example, a BGA (Ball Grid Array) type resin-encapsulated semiconductor device is preferable. It is used in. 9 is a plan view showing the conventional semiconductor device, and FIG. 10 is a cross-sectional view taken along the line DD in FIG.

同半導体装置１００は、図９及び図１０に示すように、複数の内部接続用端子１０１が形成された半導体チップ搭載用基板１０２の上面に、各内部接続用端子１０１に対応する複数の電極パッド１０３が形成された半導体チップ１０４が搭載され、各内部接続用端子１０１と対応する各電極パッド１０３との間はそれぞれ複数のボンディングワイヤ１０５により接続されている。各内部接続用端子１０１は、搭載用基板１０２に形成された内部配線（図示せず）により、搭載用基板１０２の下面に形成された対応する複数の外部接続用ボール電極（外部接続用電極）１０６にそれぞれ接続されている。また、半導体チップ１０４を含む搭載用基板１０２の上面はパッケージとなる封止樹脂１０７により覆われている。このＢＧＡ方式の樹脂封止型半導体装置１００は、これ以前から一般的に用いられている、外部接続用リード（外部接続用電極）がパッケージの四辺に引き出された構造のＱＦＰ（Quad Flat Package）方式のそれに比べて、パッケージである封止樹脂１０７により覆われている搭載用基板１０２の下面に複数の外部接続用ボール電極１０６を形成できるので、パッケージの面積当たりの外部接続用電極の配置密度を高くとれるので、小型化に適した構造を有している。   As shown in FIGS. 9 and 10, the semiconductor device 100 includes a plurality of electrode pads corresponding to each internal connection terminal 101 on an upper surface of a semiconductor chip mounting substrate 102 on which a plurality of internal connection terminals 101 are formed. A semiconductor chip 104 on which 103 is formed is mounted, and each internal connection terminal 101 and each corresponding electrode pad 103 are connected by a plurality of bonding wires 105. Each internal connection terminal 101 has a plurality of corresponding external connection ball electrodes (external connection electrodes) formed on the lower surface of the mounting substrate 102 by internal wiring (not shown) formed on the mounting substrate 102. 106, respectively. Further, the upper surface of the mounting substrate 102 including the semiconductor chip 104 is covered with a sealing resin 107 serving as a package. This BGA type resin-encapsulated semiconductor device 100 is a QFP (Quad Flat Package) that has been generally used before and has a structure in which external connection leads (external connection electrodes) are drawn out on four sides of the package. Compared to that of the method, since a plurality of external connection ball electrodes 106 can be formed on the lower surface of the mounting substrate 102 covered with the sealing resin 107 which is a package, the arrangement density of the external connection electrodes per area of the package Therefore, it has a structure suitable for downsizing.

一方、電子機器に用いられる半導体装置は半導体チップから発生する高調波ノイズや、外部から配線を介して入ってくる高周波ノイズ等の様々のノイズにより影響を受けるので、上述の半導体装置１００の外部接続用ボール電極１０６のような外部接続用電極に、ノイズを除去するための容量素子（バイパスコンデンサ）を接続する必要がある。このように、ノイズを低減するために容量素子を用いる半導体装置は、例えば特許文献１に開示されているように、従来から一般的に知られている。同半導体装置１１０は、図１１に示すように、複数のコンデンサ・セル１１１がグリッドをなすようにタイリング（tiling）されたコンデンサ・アレイ１１２が形成されている。ここでコンデンサ・アレイ１１２は、半導体基板上に形成した導電層を化学機械的研磨法等により研磨する際に、導電層の密度の均一性を高めるために利用されている。   On the other hand, a semiconductor device used in an electronic device is affected by various noises such as harmonic noise generated from a semiconductor chip and high-frequency noise entering from outside through wiring. It is necessary to connect a capacitor element (bypass capacitor) for removing noise to an external connection electrode such as the ball electrode 106 for use. As described above, a semiconductor device that uses a capacitive element to reduce noise has been generally known as disclosed in, for example, Patent Document 1. In the semiconductor device 110, as shown in FIG. 11, a capacitor array 112 is formed in which a plurality of capacitor cells 111 are tiled so as to form a grid. Here, the capacitor array 112 is used to increase the density uniformity of the conductive layer when the conductive layer formed on the semiconductor substrate is polished by a chemical mechanical polishing method or the like.

ところで、前述したようなＢＧＡ方式の樹脂封止型半導体装置１００は、半導体チップ１０４が搭載される搭載用基板１０２の下面に外部接続用電極として働く複数の外部接続用ボール電極１０６が形成されているので、この搭載用基板１０２の下面の領域にはノイズ除去用の容量素子等の電子部品を配置できないことになる。したがって、必然的にそのような電子部品は半導体装置１００の外周領域に配置せざるを得ない。   By the way, in the BGA type resin-encapsulated semiconductor device 100 as described above, a plurality of external connection ball electrodes 106 serving as external connection electrodes are formed on the lower surface of the mounting substrate 102 on which the semiconductor chip 104 is mounted. Therefore, an electronic component such as a noise removing capacitive element cannot be disposed in the region of the lower surface of the mounting substrate 102. Therefore, such electronic components are inevitably disposed in the outer peripheral region of the semiconductor device 100.

上述のような電子部品を外周領域に配置したＢＧＡ型の半導体装置が、例えば特許文献２に開示されている。同半導体装置１２０は、図１２に示すように、電源電圧ＶDDを供給する電源プレーンＰＶDD、電源電圧ＶDDQを供給する電源プレーンＰＶDDQ及びグランドプレーンＰＧが形成され、３層の配線基板１２１ａ、１２１ｂ、１２１ｃが積層された多層背面基板から成るキャリア基板１２１の上面に、アレイ状にチップ電極が主面に形成された半導体チップ１２２がバンプを介して接続（搭載）されている。なお、バンプを介さずに、例えば特許文献３に示されるようなワイヤボンディングにより接続してもよい。   For example, Patent Document 2 discloses a BGA type semiconductor device in which the electronic components as described above are arranged in the outer peripheral region. In the semiconductor device 120, as shown in FIG. 12, a power plane PVDD that supplies a power supply voltage VDD, a power plane PVDDQ that supplies a power supply voltage VDDQ, and a ground plane PG are formed, and three-layer wiring boards 121a, 121b, and 121c are formed. A semiconductor chip 122 in which chip electrodes are formed on the main surface in an array is connected (mounted) via bumps to the upper surface of a carrier substrate 121 composed of a multilayer rear substrate on which are stacked. In addition, you may connect by wire bonding as shown, for example in patent document 3, not via a bump.

電源プレーンＰＶDD、電源プレーンＰＶDDQ及びグランドプレーンＰＧは、キャリア基板１２１に形成された内部配線（図示せず）により、キャリア基板１２１の下面に形成された対応する複数のバンプ（外部接続用電極）１２３にそれぞれ接続されている。さらに、半導体チップ１２２の外周領域の配線基板１２１ａ上にはノイズ除去用の容量素子１２４が実装され、この容量素子１２４の一方接続部にはスルーホールＨ１を介して電源プレーンＰＶDDが接続されるとともに、他方接続部にはスルーホールＨ２を介して電源プレーンＰＶDDQが接続されている。また、半導体チップ１２２及び容量素子１２４を含むキャリア基板１２１の上面はパッケージとなる封止樹脂１２５により覆われている。   The power plane PVDD, the power plane PVDDQ, and the ground plane PG have a plurality of corresponding bumps (external connection electrodes) 123 formed on the lower surface of the carrier substrate 121 by internal wiring (not shown) formed on the carrier substrate 121. Are connected to each. Further, a noise removing capacitor element 124 is mounted on the wiring substrate 121a in the outer peripheral area of the semiconductor chip 122, and a power plane PVDD is connected to one connecting portion of the capacitor element 124 through a through hole H1. The other connection portion is connected to a power plane PVDDQ via a through hole H2. Further, the upper surface of the carrier substrate 121 including the semiconductor chip 122 and the capacitor element 124 is covered with a sealing resin 125 serving as a package.

また、ノイズ除去用の容量素子を形成したＢＧＡ方式の半導体装置が、例えば特許文献４に開示されている。同半導体装置１３０は、図１３に示すように、樹脂テープ１３１に設けられたリード１３２と金属板１３３との間に誘電体から成る絶縁性接着剤１３４が介在されて、コンデンサＣ及び相互インダクタンスＭが形成されている。
特開２０００−１７４２０７号公報 特開２００１−１６８２６６号公報 特開平７−３７９２９号公報 特開平１０−１１２４７２号公報 Also, for example, Patent Document 4 discloses a BGA type semiconductor device in which a noise removing capacitive element is formed. In the semiconductor device 130, as shown in FIG. 13, an insulating adhesive 134 made of a dielectric is interposed between a lead 132 provided on a resin tape 131 and a metal plate 133, so that a capacitor C and a mutual inductance M are provided. Is formed.
JP 2000-174207 A JP 2001-168266 A JP-A-7-37929 JP-A-10-112472

ところで、ノイズ除去用の容量素子を形成した特許文献２、４記載の従来の半導体装置では、それぞれ以下に説明するような問題がある。
まず、特許文献２記載の従来の半導体装置１２０では、図１２に示すように、ノイズ除去用の容量素子１２４が半導体チップ１２２の外周領域の配線基板１２１ａ上に実装されているので、パッケージとなる封止樹脂１２５のサイズが容量素子１２４を封止する分だけ大きくなって、結果的に半導体装置１２０のサイズが大きくなるため、前述したようなＢＧＡ方式の樹脂封止型半導体装置の特徴である小型化に適した利点が生かせなくなる。 By the way, the conventional semiconductor devices described in Patent Documents 2 and 4 in which the noise removing capacitance element is formed have the following problems.
First, in the conventional semiconductor device 120 described in Patent Document 2, as shown in FIG. 12, the noise removing capacitor element 124 is mounted on the wiring substrate 121a in the outer peripheral region of the semiconductor chip 122, so that it becomes a package. Since the size of the sealing resin 125 is increased by the amount for sealing the capacitor element 124, the size of the semiconductor device 120 is increased as a result, which is a feature of the BGA type resin-encapsulated semiconductor device as described above. Advantages suitable for downsizing cannot be used.

また、従来の半導体装置１２０では、半導体チップ１２２の各端子からみると、キャリア基板１２１の内部配線に加えて、外部接続用電極としてのバンプ１２３が接続される電子機器基板の内部配線（図示せず）を経由して容量素子１２４が接続されるので、大きな配線インダクタンスが容量素子１２４に直列に接続されたことになって、容量素子１２４のノイズ除去能力が大幅に低下してしまう欠点が生ずる。ここで、容量素子１２４をパッケージである封止樹脂１２５内に実装したことにより、そのような欠点を緩和することが可能となるが、サイズ的に実装できる容量素子１２４の数が限られるので、必要な端子全てに容量素子を接続することはできない。   Further, in the conventional semiconductor device 120, as viewed from each terminal of the semiconductor chip 122, in addition to the internal wiring of the carrier substrate 121, the internal wiring (not shown) of the electronic device substrate to which the bump 123 as the external connection electrode is connected. Since the capacitive element 124 is connected via a large amount of wiring inductance, a large wiring inductance is connected in series to the capacitive element 124, resulting in a drawback that the noise removal capability of the capacitive element 124 is greatly reduced. . Here, by mounting the capacitive element 124 in the sealing resin 125 which is a package, it is possible to alleviate such a drawback, but since the number of capacitive elements 124 that can be mounted in size is limited, Capacitance elements cannot be connected to all necessary terminals.

次に、特許文献４記載の従来の半導体装置１３０では、図１３に示すように、リード１３２と金属板１３３と絶縁性接着剤１３４とによりコンデンサＣを形成することができるが、これらのコンデンサＣは実質的に半導体チップの外周領域に形成されるので、上述した半導体装置１２０と同じような欠点が生ずるようになる。   Next, in the conventional semiconductor device 130 described in Patent Document 4, as shown in FIG. 13, the capacitor C can be formed by the lead 132, the metal plate 133, and the insulating adhesive 134. Is substantially formed in the outer peripheral region of the semiconductor chip, and therefore, the same disadvantage as the semiconductor device 120 described above occurs.

この発明は、上述の事情に鑑みてなされたもので、パッケージの小型化を生かしたままで、配線インダクタンスの影響を受けることなく容量素子のノイズ除去能力の低下を防止することができるようにした半導体装置を提供することを目的としている。   The present invention has been made in view of the above-described circumstances, and is a semiconductor capable of preventing a reduction in noise removal capability of a capacitive element without being affected by wiring inductance while making use of the downsizing of the package. The object is to provide a device.

上記課題を解決するために、請求項１記載の発明は、絶縁基板の上面に複数の電極が形成された半導体チップが搭載されるとともに、上記絶縁基板の下面に上記複数の電極と対応するもの同士が電気的に接続された複数の外部接続用電極が形成されて成る半導体装置に係り、上記半導体チップに、該半導体チップの上記複数の電極と対応する複数の電極が形成された容量チップが積層され、上記半導体チップと上記容量チップとの対応する電極同士が、上記絶縁基板に形成された複数の内部接続用端子を介して電気的に接続されることを特徴としている。   In order to solve the above problems, the invention according to claim 1 is provided with a semiconductor chip having a plurality of electrodes formed on the upper surface of the insulating substrate and corresponding to the plurality of electrodes on the lower surface of the insulating substrate. The present invention relates to a semiconductor device in which a plurality of external connection electrodes that are electrically connected to each other are formed, and a capacitor chip in which a plurality of electrodes corresponding to the plurality of electrodes of the semiconductor chip are formed on the semiconductor chip. The stacked electrodes and corresponding electrodes of the semiconductor chip and the capacitor chip are electrically connected through a plurality of internal connection terminals formed on the insulating substrate.

また、請求項２記載の発明は、請求項１記載の半導体装置に係り、上記半導体チップと上記容量チップとの対応する電極同士が、それぞれボンディングワイヤを介して上記内部接続用端子に電気的に接続されることを特徴としている。   According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the corresponding electrodes of the semiconductor chip and the capacitor chip are electrically connected to the internal connection terminals via bonding wires, respectively. It is characterized by being connected.

また、請求項３記載の発明は、請求項１又は２記載の半導体装置に係り、上記容量チップに複数の容量素子が形成され、該容量素子の一方の電極が複数に分割される一方、他方の電極が共通に形成されることを特徴としている。   According to a third aspect of the invention, there is provided the semiconductor device according to the first or second aspect, wherein a plurality of capacitive elements are formed on the capacitive chip, and one electrode of the capacitive element is divided into a plurality of parts, while the other These electrodes are formed in common.

また、請求項４記載の発明は、請求項３記載の半導体装置に係り、上記容量素子の上記一方の複数の電極が対応する上記容量チップの上記複数の電極にそれぞれ電気的に接続されることを特徴としている。   The invention according to claim 4 relates to the semiconductor device according to claim 3, wherein the one plurality of electrodes of the capacitor element are electrically connected to the plurality of electrodes of the corresponding capacitor chip, respectively. It is characterized by.

また、請求項５記載の発明は、請求項１乃至４のいずれか一に記載の半導体装置に係り、上記絶縁基板の上記複数の内部接続用端子の少なくとも一つ、上記半導体チップの上記複数の電極の少なくとも一つ、上記容量チップの上記複数の電極の少なくとも一つがグランド用端子として形成されて、該グランド用端子が上記容量素子の上記他方の共通電極に電気的に接続されることを特徴としている。   A fifth aspect of the present invention relates to the semiconductor device according to any one of the first to fourth aspects, wherein at least one of the plurality of internal connection terminals of the insulating substrate and the plurality of the plurality of semiconductor chips. At least one of the electrodes and at least one of the plurality of electrodes of the capacitor chip are formed as a ground terminal, and the ground terminal is electrically connected to the other common electrode of the capacitor element. It is said.

また、請求項６記載の発明は、請求項５記載の半導体装置に係り、上記絶縁基板の上記内部接続用端子の周囲にグランド用配線層が形成され、該グランド用配線層が上記共通電極に電気的に接続されることを特徴としている。   According to a sixth aspect of the invention, there is provided the semiconductor device according to the fifth aspect, wherein a ground wiring layer is formed around the internal connection terminal of the insulating substrate, and the ground wiring layer is formed on the common electrode. It is characterized by being electrically connected.

また、請求項７記載の発明は、請求項１乃至６のいずれか一に記載の半導体装置に係り、複数の上記容量チップが上記半導体チップに積層されることを特徴としている。   A seventh aspect of the invention relates to the semiconductor device according to any one of the first to sixth aspects, wherein a plurality of the capacitor chips are stacked on the semiconductor chip.

この発明の半導体装置によれば、半導体チップに、この半導体チップの複数の電極パッドと対応する複数の外部接続用パッドが形成された容量チップが積層され、半導体チップと容量チップとの対応するパッド同士が、半導体チップ搭載用基板に形成された複数の内部接続用端子を介して電気的に接続されるので、パッケージの小型化を生かしたままで、配線インダクタンスの影響を受けることなく容量素子のノイズ除去能力の低下を防止することができる。   According to the semiconductor device of the present invention, a capacitor chip in which a plurality of external connection pads corresponding to a plurality of electrode pads of the semiconductor chip is stacked on the semiconductor chip, and the pads corresponding to the semiconductor chip and the capacitor chip are stacked. Since the two are electrically connected via a plurality of internal connection terminals formed on the semiconductor chip mounting substrate, the noise of the capacitive element is not affected by the wiring inductance while taking advantage of the miniaturization of the package. A reduction in removal capability can be prevented.

半導体チップ搭載用基板の上面に複数の電極パッドが形成された半導体チップが搭載されるとともに、半導体チップ搭載用基板の下面に複数の電極パッドと対応するもの同士が電気的に接続された複数の外部接続用ボール電極が形成されて成る構成において、半導体チップに、この半導体チップの複数の電極パッドと対応する複数の外部接続用パッドが形成された容量チップが積層され、半導体チップと容量チップとの対応するパッド同士が、半導体チップ搭載用基板に形成された複数の内部接続用端子を介して電気的に接続されている。   A semiconductor chip having a plurality of electrode pads formed on the upper surface of the semiconductor chip mounting substrate is mounted, and a plurality of electrodes corresponding to the plurality of electrode pads are electrically connected to the lower surface of the semiconductor chip mounting substrate. In the configuration in which the ball electrodes for external connection are formed, a capacitor chip in which a plurality of external connection pads corresponding to the plurality of electrode pads of the semiconductor chip is stacked on the semiconductor chip, and the semiconductor chip, the capacitor chip, The corresponding pads are electrically connected through a plurality of internal connection terminals formed on the semiconductor chip mounting substrate.

図１はこの発明の実施例１である半導体装置の構成を示す平面図、図２は図１のＡ−Ａ矢視断面図、図３は同半導体装置の半導体チップを示す平面図、図４は同半導体装置の容量チップを示す平面図、図５は図４のＢ−Ｂ矢視断面図、また、図６は同半導体装置の製造方法を工程順に示す工程図である。
この例の半導体装置１０は、図１及び図２に示すように、複数の内部接続用端子１が形成された半導体チップ搭載用基板２の上面に、各内部接続用端子１に対応する複数の電極パッド３が形成された半導体チップ４が搭載され、各内部接続用端子１と対応する各電極パッド３との間はそれぞれ複数のボンディングワイヤ５により接続されている。各内部接続用端子１は、搭載用基板２に形成された内部配線（図示せず）により、搭載用基板２の下面に形成された対応する複数の外部接続用ボール電極（外部接続用電極）６にそれぞれ接続されている。 1 is a plan view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention, FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1, and FIG. 3 is a plan view showing a semiconductor chip of the semiconductor device. Is a plan view showing the capacitor chip of the semiconductor device, FIG. 5 is a cross-sectional view taken along the line BB of FIG. 4, and FIG. 6 is a process diagram showing the method of manufacturing the semiconductor device in order of steps.
As shown in FIGS. 1 and 2, the semiconductor device 10 of this example includes a plurality of corresponding internal connection terminals 1 on an upper surface of a semiconductor chip mounting substrate 2 on which a plurality of internal connection terminals 1 are formed. A semiconductor chip 4 on which electrode pads 3 are formed is mounted, and each internal connection terminal 1 and each corresponding electrode pad 3 are connected by a plurality of bonding wires 5. Each internal connection terminal 1 has a plurality of corresponding external connection ball electrodes (external connection electrodes) formed on the lower surface of the mounting substrate 2 by internal wiring (not shown) formed on the mounting substrate 2. 6 are connected to each other.

半導体チップ搭載用基板２上の内部接続用端子１は、後述するように、半導体チップ４の電極パッド３及び容量チップ１１の外部接続用パッド１２と同数だけ形成され、方形状の四辺に沿ってそれぞれ複数の例えば５個が設けられている。また、各辺の内部接続用端子１の１つはグランド用端子１Ｇとして用いられるようになっている。さらに、複数の内部接続用端子１の周囲には、グランドを強化する目的で枠状のグランド用配線層７が形成されて、このグランド用配線層７には各グランド用端子１Ｇが内部配線８により接続されている。   As will be described later, the same number of internal connection terminals 1 on the semiconductor chip mounting substrate 2 as the electrode pads 3 of the semiconductor chip 4 and the external connection pads 12 of the capacitor chip 11 are formed along the four sides of the square. For example, a plurality of, for example, five pieces are provided. One of the internal connection terminals 1 on each side is used as a ground terminal 1G. Further, a frame-like ground wiring layer 7 is formed around the plurality of internal connection terminals 1 for the purpose of strengthening the ground, and each ground terminal 1G is connected to the internal wiring 8 in the ground wiring layer 7. Connected by.

半導体チップ４は、図３に示すように、方形状の四辺に沿ってそれぞれ複数の例えば５個の電極パッド３が設けられて、Ａｇペースト等の導電性接着剤や両面テープ等の接着剤により、搭載用基板２の中央部に固着される。また、各辺の電極パッド３の１つはグランド用端子３Ｇとして用いられて、グランド用ワイヤ５Ｇによりグランド用端子１Ｇに接続されている。残りの電極パッド３は、電源用端子、信号入力用端子及び信号出力用端子として用いられる。   As shown in FIG. 3, the semiconductor chip 4 is provided with a plurality of, for example, five electrode pads 3 along four sides of a square, and is made of a conductive adhesive such as Ag paste or an adhesive such as double-sided tape. , Fixed to the center of the mounting substrate 2. In addition, one of the electrode pads 3 on each side is used as a ground terminal 3G and is connected to the ground terminal 1G by a ground wire 5G. The remaining electrode pads 3 are used as power supply terminals, signal input terminals, and signal output terminals.

また、半導体装置１０は、図１及び図２に示すように、半導体チップ４と略同様なサイズを有し半導体チップ４上にシリコン基板等から成るスペーサ９を介して、後述のように複数の容量素子Ｃが形成された容量チップ１１が積層されるように搭載されている。容量チップ１１は、図４に示すように、方形状の四辺に沿ってそれぞれ複数の例えば５個の外部接続用パッド１２が設けられて、各外部接続用パッド１２と対応する各内部接続用端子１との間はそれぞれ複数のボンディングワイヤ１３により接続されている。各辺の外部接続用パッド１２の１つはグランド用パッド１２Ｇとして用いられて、グランド用ワイヤ１３Ｇによりグランド用端子１Ｇに接続されている。   Further, as shown in FIGS. 1 and 2, the semiconductor device 10 has a size substantially the same as that of the semiconductor chip 4, and a plurality of semiconductor devices 10 as described later via spacers 9 made of a silicon substrate or the like on the semiconductor chip 4. The capacitor chip 11 on which the capacitor element C is formed is mounted so as to be stacked. As shown in FIG. 4, the capacitor chip 11 is provided with a plurality of, for example, five external connection pads 12 along each of the four sides of the square, and each internal connection terminal corresponding to each external connection pad 12. 1 are connected to each other by a plurality of bonding wires 13. One of the external connection pads 12 on each side is used as a ground pad 12G and is connected to the ground terminal 1G by a ground wire 13G.

さらに容量チップ１１は、図５にも示すように、シリコン基板等の支持板１４に形成された共通の下部電極１５と、この下部電極１５上に形成された誘電体層１６と、この誘電体層１６上に形成された複数の例えば１６個の上部電極１７とを有している。各上部電極１７と対応する各外部接続用パッド１２との間はそれぞれ内部配線１８により接続されている。各グランド用パッド１２Ｇはスルーホール配線１９により下部電極１５に接続されている。また、複数の上部電極１７は絶縁性保護膜２０により覆われる。以上の構成により、容量チップ１１には１６個の容量素子Ｃが形成されて、容量チップ１１はＡｇペースト等の導電性接着剤や両面テープ等の接着剤によりスペーサ９を介して、半導体チップ４上に重畳されるように搭載される。また、半導体チップ４、容量チップ１１及び各ボンディングワイヤ５、１３等を含む搭載用基板２の上面はパッケージとなる封止樹脂２１により覆われている。   Further, as shown in FIG. 5, the capacitor chip 11 includes a common lower electrode 15 formed on a support plate 14 such as a silicon substrate, a dielectric layer 16 formed on the lower electrode 15, and the dielectric A plurality of, for example, 16 upper electrodes 17 formed on the layer 16 are included. Each upper electrode 17 and each corresponding external connection pad 12 are connected by an internal wiring 18. Each ground pad 12G is connected to the lower electrode 15 by a through-hole wiring 19. The plurality of upper electrodes 17 are covered with an insulating protective film 20. With the above configuration, 16 capacitive elements C are formed in the capacitive chip 11, and the capacitive chip 11 is connected to the semiconductor chip 4 via the spacer 9 with a conductive adhesive such as Ag paste or an adhesive such as double-sided tape. It is mounted so as to be superimposed on the top. Further, the upper surface of the mounting substrate 2 including the semiconductor chip 4, the capacitor chip 11, the bonding wires 5 and 13, etc. is covered with a sealing resin 21 that becomes a package.

上述したような半導体装置１０によれば、容量チップ１１に形成された複数の容量素子Ｃは半導体チップ搭載用基板２上において、各ボンディングワイヤ５、１３を通じて、半導体チップ４の複数の電極パッド３により構成される電源端子とグランド用端子との間に、信号入力端子及び信号出力端子とグランド用端子との間にそれぞれ接続されることになる。したがって、外部接続用電極としての外部接続用ボール電極６が接続される電子機器基板の内部配線を経由して各容量素子Ｃが接続されることはないので、大きな配線インダクタンスが各容量素子Ｃに直列に接続されず、しかも必要な端子全てに容量素子Ｃを接続できるため、容量素子Ｃのノイズ除去能力が低下することはなくなる。   According to the semiconductor device 10 as described above, the plurality of capacitor elements C formed on the capacitor chip 11 are connected to the plurality of electrode pads 3 of the semiconductor chip 4 through the bonding wires 5 and 13 on the semiconductor chip mounting substrate 2. The signal input terminal, the signal output terminal, and the ground terminal are respectively connected between the power supply terminal constituted by the above and the ground terminal. Therefore, since each capacitive element C is not connected via the internal wiring of the electronic equipment substrate to which the external connection ball electrode 6 as the external connection electrode is connected, a large wiring inductance is applied to each capacitive element C. Since the capacitive element C can be connected to all necessary terminals without being connected in series, the noise removal capability of the capacitive element C is not reduced.

また、複数の容量素子Ｃを形成した容量チップ１１は半導体チップ４と略同様なサイズを有して、半導体チップ４に積層されるように搭載されるので、半導体チップ４の外周領域に容量チップ４を搭載するための余分のスペースを占有することがない。したがって、パッケージとなる封止樹脂２１のサイズが容量チップ４を封止する分だけ大きくなることがないので、結果的に半導体装置１０のサイズも大きくなることはなく、ＢＧＡ方式の樹脂封止型半導体装置の特徴である小型化の利点を生かすことができる。   Further, the capacitor chip 11 in which the plurality of capacitor elements C are formed has substantially the same size as the semiconductor chip 4 and is mounted so as to be stacked on the semiconductor chip 4. No extra space for mounting 4 is occupied. Therefore, since the size of the sealing resin 21 that becomes the package does not increase by the amount for sealing the capacitor chip 4, the size of the semiconductor device 10 does not increase as a result. The advantage of downsizing, which is a feature of the semiconductor device, can be utilized.

次に、図６を参照して、この例の半導体装置１０の製造方法を工程順に説明する。
まず、図６（ａ）に示すように、複数の内部接続用端子１及びこの周囲に枠状のグランド用配線層７が形成された半導体チップ搭載用基板２を用意する。搭載用基板２には、後述するように、搭載用基板２の下面に複数の外部接続用ボール電極（外部接続用電極）６が形成されたときに、各内部接続用端子１が対応する複数の外部接続用ボール電極６にそれぞれ接続されるように内部配線（図示せず）が形成されている。 Next, with reference to FIG. 6, the manufacturing method of the semiconductor device 10 of this example will be described in the order of steps.
First, as shown in FIG. 6A, a plurality of internal connection terminals 1 and a semiconductor chip mounting substrate 2 on which a frame-like ground wiring layer 7 is formed are prepared. As will be described later, when a plurality of external connection ball electrodes (external connection electrodes) 6 are formed on the lower surface of the mounting substrate 2, the mounting substrate 2 has a plurality of corresponding internal connection terminals 1. Internal wiring (not shown) is formed so as to be connected to the external connection ball electrodes 6.

次に、図６（ｂ）に示すように、方形状の四辺に沿ってそれぞれ複数の例えば５個の電極パッド３が設けられた半導体チップ４を、Ａｇペースト等の導電性接着剤や両面テープ等の接着剤により、搭載用基板２の中央部に固着する。次に、搭載用基板２の各内部接続用端子１と対応する各電極パッド３との間をそれぞれ複数のボンディングワイヤ５により接続する。   Next, as shown in FIG. 6 (b), the semiconductor chip 4 provided with a plurality of, for example, five electrode pads 3 along each of the four sides of the square is made of conductive adhesive such as Ag paste or double-sided tape. It adheres to the center part of the mounting substrate 2 with an adhesive such as. Next, each internal connection terminal 1 of the mounting substrate 2 and each corresponding electrode pad 3 are connected by a plurality of bonding wires 5.

次に、図６（ｃ）に示すように、方形状の四辺に沿ってそれぞれ複数の例えば５個の外部接続用電極１２及び複数の例えば１６個の容量素子Ｃが形成された容量チップ１１を、Ａｇペースト等の導電性接着剤や両面テープ等の接着剤によりスペーサ９を介して、半導体チップ４に積層するように搭載する。次に、半導体チップ搭載用基板２の各内部接続用端子１と対応する各外部接続用電極１２との間をそれぞれ複数のボンディングワイヤ１３により接続する。
次に、搭載用基板２の下面に外部接続用ボール電極６を設けた後、半導体チップ４、容量チップ１１及び各ボンディングワイヤ５、１３等を含む搭載用基板２の上面にパッケージとなる封止樹脂２１を形成することにより、図１及び図２に示したような半導体装置１０を完成させる。 Next, as shown in FIG. 6C, a capacitor chip 11 in which a plurality of, for example, five external connection electrodes 12 and a plurality of, for example, 16 capacitor elements C are formed along the four sides of the square. The semiconductor chip 4 is mounted so as to be laminated via the spacer 9 with a conductive adhesive such as Ag paste or an adhesive such as double-sided tape. Next, each internal connection terminal 1 of the semiconductor chip mounting substrate 2 and each corresponding external connection electrode 12 are connected by a plurality of bonding wires 13.
Next, after the external connection ball electrode 6 is provided on the lower surface of the mounting substrate 2, a package that becomes a package is formed on the upper surface of the mounting substrate 2 including the semiconductor chip 4, the capacitor chip 11, the bonding wires 5 and 13, and the like. By forming the resin 21, the semiconductor device 10 as shown in FIGS. 1 and 2 is completed.

このように、この例の半導体装置１０によれば、半導体チップ搭載用基板２の上面に複数の電極パッド３が形成された半導体チップ４が搭載されるとともに、半導体チップ搭載用基板２の下面に複数の電極パッド３と対応するもの同士が電気的に接続された複数の外部接続用ボール電極６が形成されて成る構成において、半導体チップ４に、この半導体チップ４の複数の電極パッド３と対応する複数の外部接続用パッド１２が形成された容量チップ１１が積層され、半導体チップ４と容量チップ１１との対応するパッド３、１２同士が、半導体チップ搭載用基板２に形成された複数の内部接続用端子１を介して電気的に接続されているので、外部接続用電極としての外部接続用ボール電極６が接続される電子機器基板の内部配線を経由して各容量素子Ｃが接続されることはないので、大きな配線インダクタンスが各容量素子Ｃに直列に接続されない。
したがって、パッケージの小型化を生かしたままで、配線インダクタンスの影響を受けることなく容量素子のノイズ除去能力の低下を防止することができる。 Thus, according to the semiconductor device 10 of this example, the semiconductor chip 4 on which the plurality of electrode pads 3 are formed is mounted on the upper surface of the semiconductor chip mounting substrate 2, and the lower surface of the semiconductor chip mounting substrate 2 is mounted. In a configuration in which a plurality of external connection ball electrodes 6 are formed in which the corresponding ones of the plurality of electrode pads 3 are electrically connected to each other, the semiconductor chip 4 corresponds to the plurality of electrode pads 3 of the semiconductor chip 4. Capacitor chips 11 having a plurality of external connection pads 12 formed thereon are stacked, and pads 3 and 12 corresponding to the semiconductor chip 4 and the capacitor chip 11 are formed on the semiconductor chip mounting substrate 2. Since it is electrically connected via the connection terminal 1, each external connection ball electrode 6 as an external connection electrode is connected via the internal wiring of the electronic device substrate. Since there is no possibility that the amount element C is connected, a large wiring inductance is not connected in series with the capacitance elements C.
Therefore, it is possible to prevent a reduction in the noise removal capability of the capacitive element without being affected by the wiring inductance while keeping the downsizing of the package.

図７は、この発明の実施例２である半導体装置の構成を示す平面図、図８は図７のＣ−Ｃ矢視断面図である。この例の半導体装置の構成が、上述の実施例１のそれと大きく異なるところは、複数の容量チップを半導体チップに積層するようにした点である。
この例の半導体装置２２は、図７及び図８に示すように、実施例１における容量チップ１１を第１の容量チップとして用いて半導体チップ４の下部に積層するとともに、第２の容量チップとして新たな容量チップ２３を用いて、半導体チップ４の上部に積層している。 7 is a plan view showing a configuration of a semiconductor device according to Embodiment 2 of the present invention, and FIG. 8 is a cross-sectional view taken along the line CC of FIG. The configuration of the semiconductor device of this example is greatly different from that of the first embodiment described above in that a plurality of capacitor chips are stacked on the semiconductor chip.
As shown in FIGS. 7 and 8, the semiconductor device 22 of this example uses the capacitor chip 11 according to the first embodiment as a first capacitor chip and is stacked below the semiconductor chip 4, and as the second capacitor chip. A new capacitor chip 23 is used and stacked on top of the semiconductor chip 4.

容量チップ２３は、容量チップ１１と略同様なサイズを有し半導体チップ４上にシリコン基板等から成るスペーサ２４を介して、容量チップ１１と同様に複数の容量素子Ｃが形成されるように構成されている。容量チップ２３は、図７及び図８に示すように、方形状の四辺に沿ってそれぞれ複数の例えば５個の外部接続用パッド２５が設けられて、各外部接続用パッド２５と対応する各内部接続用端子１との間はそれぞれ複数のボンディングワイヤ２６により接続されている。各辺の外部接続用パッド２６の１つはグランド用パッド２６Ｇとして用いられて、グランド用ワイヤ２６Ｇによりグランド用端子１Ｇに接続されている。
これ以外は、上述した実施例１の構成と略同様であるので、図７において、図１の構成部分と対応する各部には同一の番号を付してその説明を省略する。 The capacitor chip 23 has substantially the same size as the capacitor chip 11 and is configured such that a plurality of capacitor elements C are formed on the semiconductor chip 4 through spacers 24 made of a silicon substrate or the like, like the capacitor chip 11. Has been. As shown in FIGS. 7 and 8, the capacitor chip 23 is provided with a plurality of, for example, five external connection pads 25 along the four sides of the square, and each internal chip corresponding to each external connection pad 25 is provided. The connection terminals 1 are connected to each other by a plurality of bonding wires 26. One of the external connection pads 26 on each side is used as a ground pad 26G, and is connected to the ground terminal 1G by a ground wire 26G.
Other than this, the configuration is substantially the same as the configuration of the first embodiment described above. Therefore, in FIG. 7, the same numbers are assigned to the components corresponding to the components in FIG.

このように、この例の構成によっても実施例１と略同様な効果を得ることができる。   As described above, the configuration of this example can provide substantially the same effect as that of the first embodiment.

以上、この発明の実施例を図面により詳述してきたが、具体的な構成はこの実施例に限られるものではなく、この発明の要旨を逸脱しない範囲の設計の変更等があってもこの発明に含まれる。例えば、実施例ではＢＧＡ方式の樹脂封止型半導体装置に例をあげて説明したが、これに限ることなくＰＧＡ（Pin Grid Array）方式のような、あるいはボール、ピン以外にも外部接続用電極として平坦な導電層を形成したような他の方式の樹脂封止型半導体装置にも適用することができる。また、パッケージの構造は樹脂封止型に限ることなく、セラミックパッケージのような他の封止型にも適用することができる。また、容量チップに形成する複数の容量素子は、誘電体層として高誘電率材料を用いる等の工夫により、高い容量を得ることができるようになる。また、実施例では容量チップに１６個の容量素子を形成する例で説明したが、容量素子の数は目的、用途等に応じて任意に選ぶことができる。   The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and the present invention can be changed even if there is a design change or the like without departing from the gist of the present invention. include. For example, in the embodiments, a BGA type resin-encapsulated semiconductor device has been described as an example. However, the present invention is not limited to this, but the PGA (Pin Grid Array) type, or external connection electrodes other than balls and pins. The present invention can also be applied to other types of resin-encapsulated semiconductor devices in which a flat conductive layer is formed. Further, the structure of the package is not limited to the resin sealing type, but can be applied to other sealing types such as a ceramic package. In addition, a plurality of capacitive elements formed in the capacitive chip can obtain a high capacitance by a device such as using a high dielectric constant material as a dielectric layer. In the embodiment, an example in which 16 capacitive elements are formed on the capacitive chip has been described. However, the number of capacitive elements can be arbitrarily selected according to the purpose and application.

この発明の実施例１である半導体装置の構成を示す平面図である。It is a top view which shows the structure of the semiconductor device which is Example 1 of this invention. 図１のＡ−Ａ矢視断面図である。It is AA arrow sectional drawing of FIG. 同半導体装置の半導体チップを示す平面図である。It is a top view which shows the semiconductor chip of the semiconductor device. 同半導体装置の容量チップを示す平面図である。It is a top view which shows the capacity | capacitance chip | tip of the semiconductor device. 図４のＢ−Ｂ矢視断面図である。It is a BB arrow sectional view of Drawing 4. 同半導体装置の製造方法を工程順に示す工程図である。It is process drawing which shows the manufacturing method of the same semiconductor device in process order. この発明の実施例２である半導体装置の構成を示す平面図である。It is a top view which shows the structure of the semiconductor device which is Example 2 of this invention. 図７のＣ−Ｃ矢視断面図である。It is CC sectional view taken on the line of FIG. 従来の半導体装置の構成を示す平面図である。It is a top view which shows the structure of the conventional semiconductor device. 図９のＤ−Ｄ矢視断面図である。It is DD sectional view taken on the line of FIG. 従来の半導体装置の概略構成を示す平面図である。It is a top view which shows schematic structure of the conventional semiconductor device. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device. 従来の半導体装置の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the conventional semiconductor device.

符号の説明Explanation of symbols

１ 内部接続用端子
１Ｇ グランド用端子
２ 半導体チップ搭載用基板
３ 電極パッド
３Ｇ グランド用パッド
４ 半導体チップ
５、１３、２６ ボンディングワイヤ
５Ｇ、１３Ｇ、２６Ｇ グランド用ワイヤ
６ 外部接続用ボール電極（外部接続用電極）
７ グランド用配線層
８ 内部配線
９、２４ スペーサ
１０、２２ 半導体装置
１１、２３ 容量チップ
１２、２５ 外部接続用パッド
１２Ｇ グランド用パッド
１４ 支持板
１５ 下部電極
１６ 誘電体層
１７ 上部電極
１８ 内部配線
１９ スルーホール配線
２０ 絶縁性保護膜
２１ 封止樹脂
DESCRIPTION OF SYMBOLS 1 Internal connection terminal 1G Ground terminal 2 Semiconductor chip mounting board 3 Electrode pad 3G Ground pad 4 Semiconductor chip 5, 13, 26 Bonding wire 5G, 13G, 26G Ground wire 6 Ball electrode for external connection (For external connection electrode)
7 Ground wiring layer 8 Internal wiring 9, 24 Spacer 10, 22 Semiconductor device 11, 23 Capacitance chip 12, 25 External connection pad 12G Ground pad 14 Support plate 15 Lower electrode 16 Dielectric layer 17 Upper electrode 18 Internal wiring 19 Through-hole wiring 20 Insulating protective film 21 Sealing resin

Claims (7)

絶縁基板の上面に複数の電極が形成された半導体チップが搭載されるとともに、前記絶縁基板の下面に前記複数の電極と対応するもの同士が電気的に接続された複数の外部接続用電極が形成されて成る半導体装置であって、
前記半導体チップに、該半導体チップの前記複数の電極と対応する複数の電極が形成された容量チップが積層され、前記半導体チップと前記容量チップとの対応する電極同士が、前記絶縁基板に形成された複数の内部接続用端子を介して電気的に接続されることを特徴とする半導体装置。 A semiconductor chip having a plurality of electrodes formed on the upper surface of the insulating substrate is mounted, and a plurality of external connection electrodes are formed on the lower surface of the insulating substrate and corresponding to the plurality of electrodes are electrically connected to each other. A semiconductor device comprising:
A capacitor chip in which a plurality of electrodes corresponding to the plurality of electrodes of the semiconductor chip are formed is stacked on the semiconductor chip, and corresponding electrodes of the semiconductor chip and the capacitor chip are formed on the insulating substrate. A semiconductor device, wherein the semiconductor device is electrically connected through a plurality of internal connection terminals. 前記半導体チップと前記容量チップとの対応する電極同士が、それぞれボンディングワイヤを介して前記内部接続用端子に電気的に接続されることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the corresponding electrodes of the semiconductor chip and the capacitor chip are electrically connected to the internal connection terminals through bonding wires, respectively. 前記容量チップに複数の容量素子が形成され、該容量素子の一方の電極が複数に分割される一方、他方の電極が共通に形成されることを特徴とする請求項１又は２記載の半導体装置。   3. The semiconductor device according to claim 1, wherein a plurality of capacitor elements are formed on the capacitor chip, and one electrode of the capacitor element is divided into a plurality of electrodes, while the other electrode is formed in common. . 前記容量素子の前記一方の複数の電極が対応する前記容量チップの前記複数の電極にそれぞれ電気的に接続されることを特徴とする請求項３記載の半導体装置。   4. The semiconductor device according to claim 3, wherein the plurality of electrodes of the capacitive element are electrically connected to the plurality of electrodes of the corresponding capacitive chip. 前記絶縁基板の前記複数の内部接続用端子の少なくとも一つ、前記半導体チップの前記複数の電極の少なくとも一つ、前記容量チップの前記複数の電極の少なくとも一つがグランド用端子として形成されて、該グランド用端子が前記容量素子の前記他方の共通電極に電気的に接続されることを特徴とする請求項１乃至４のいずれか一に記載の半導体装置。   At least one of the plurality of internal connection terminals of the insulating substrate, at least one of the plurality of electrodes of the semiconductor chip, and at least one of the plurality of electrodes of the capacitor chip are formed as ground terminals, The semiconductor device according to claim 1, wherein a ground terminal is electrically connected to the other common electrode of the capacitor element. 前記絶縁基板の前記内部接続用端子の周囲にグランド用配線層が形成され、該グランド用配線層が前記共通電極に電気的に接続されることを特徴とする請求項５記載の半導体装置。   6. The semiconductor device according to claim 5, wherein a ground wiring layer is formed around the internal connection terminal of the insulating substrate, and the ground wiring layer is electrically connected to the common electrode. 複数の前記容量チップが前記半導体チップに積層されることを特徴とする請求項１乃至６のいずれか一に記載の半導体装置。
The semiconductor device according to claim 1, wherein a plurality of the capacitor chips are stacked on the semiconductor chip.
JP2004216533A 2004-07-23 2004-07-23 Semiconductor device Expired - Fee Related JP4370993B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250708A (en) * 2006-03-15 2007-09-27 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing process
KR100828499B1 (en) 2006-11-15 2008-05-13 한국과학기술원 Semiconductor chip package for reducing wire bonding inductance
JP2012221973A (en) * 2011-04-04 2012-11-12 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and method of manufacturing the same
CN114664771A (en) * 2022-02-14 2022-06-24 致瞻科技(上海)有限公司 Novel semiconductor capacitor packaging structure and packaging method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250708A (en) * 2006-03-15 2007-09-27 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing process
JP4714049B2 (en) * 2006-03-15 2011-06-29 Ｏｋｉセミコンダクタ株式会社 Semiconductor device and manufacturing method of semiconductor device
KR100828499B1 (en) 2006-11-15 2008-05-13 한국과학기술원 Semiconductor chip package for reducing wire bonding inductance
JP2012221973A (en) * 2011-04-04 2012-11-12 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and method of manufacturing the same
CN114664771A (en) * 2022-02-14 2022-06-24 致瞻科技(上海)有限公司 Novel semiconductor capacitor packaging structure and packaging method thereof

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