KR20110050963A - Method for fabricating semiconductoer package - Google Patents

Method for fabricating semiconductoer package Download PDF

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Publication number
KR20110050963A
KR20110050963A KR1020090107587A KR20090107587A KR20110050963A KR 20110050963 A KR20110050963 A KR 20110050963A KR 1020090107587 A KR1020090107587 A KR 1020090107587A KR 20090107587 A KR20090107587 A KR 20090107587A KR 20110050963 A KR20110050963 A KR 20110050963A
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KR
South Korea
Prior art keywords
wafer
via hole
electrode
mask pattern
forming
Prior art date
Application number
KR1020090107587A
Other languages
Korean (ko)
Inventor
김종훈
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090107587A priority Critical patent/KR20110050963A/en
Publication of KR20110050963A publication Critical patent/KR20110050963A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a semiconductor package is disclosed. The disclosed method of manufacturing a semiconductor package includes forming a first via hole exposing the contact pad of the circuit part by etching the wafer from a rear surface facing the front surface of the wafer on which the circuit portion is formed, and filling the first via hole to form a through electrode. Forming a mask pattern exposing the through electrode and the wafer around the wafer on the back surface of the wafer; and etching the wafer exposed by the mask pattern to expose a side surface of the through electrode. Forming a second via hole, removing the mask pattern, and filling an insulating film in the second via hole. According to the present invention, since the alignment margin of the through electrode forming process is improved, defects due to lack of the alignment margin are suppressed and the yield is improved.

Description

Semiconductor package manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOER PACKAGE}

The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a semiconductor package using a through silicon via (TSV) technology.

Through silicon via (TSV) technology, a through electrode is formed on a semiconductor chip, and a plurality of semiconductor chips are electrically stacked through the through electrode. By using TSV technology, a plurality of semiconductor chips can be implemented in one package, thereby enabling development of a high capacity package, and improving signal transmission speed between semiconductor chips.

One method of implementing a TSV is the 'via last TSV scheme', which forms a TSV from the back side of the wafer.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor package using a via last TSV scheme according to the prior art, and FIGS. 2 to 4 are plan views of FIGS. 1B, 1D, and 1F, respectively.

Referring to FIG. 1A, the carrier substrate 13 is attached to the front surface of the wafer 10 on which the bonding pads 11B are formed via the adhesive member 12.

The wafer 10 includes a plurality of semiconductor chips and a scribe lane positioned between the semiconductor chips.

Although not shown, the semiconductor chip includes a circuit portion. The circuit portion includes, for example, a data storage portion for storing data and a data processing portion for processing the data. The bonding pad 11B corresponds to an electrical contact of a circuit portion for connection with the outside.

The semiconductor chip includes a contact pad 11A electrically connected to a circuit portion therein, and the contact pad 11A and the bonding pad 11B are formed by a conductive connection member 11C penetrating through the insulating film 11D formed therebetween. Electrically connected.

Referring to FIG. 1B, the wafer 10 is thinly processed by back-grinding the rear surface facing the front surface of the wafer 10.

1C and 2, the wafer 10 is turned upside down so that the backside of the wafer 10 faces upward, and then a donut in a position corresponding to the contact pad 11A on the backside of the wafer 10. The first via hole 15 exposing the contact pad 11A is formed by forming the first mask pattern 14 having an opening having a shape, and etching the wafer 10 from the rear surface using the first mask pattern 14. Form.

Next, the first mask pattern 14 is removed.

Referring to FIG. 1D, an insulating film 16 is formed on the back surface of the wafer 10 to fill the first via hole 15.

1E and 3, a second mask pattern 17 is formed on the insulating film 16 to open the upper portion of the wafer 10 inside the insulating film 16 embedded in the first via hole 15. The insulating layer 16 opened by the second mask pattern 17 and the lower wafer 10 are etched to form a second via hole 18 exposing the contact pad 11A.

1F and 4, the second mask pattern 17 is removed, and a conductive film is formed on the insulating film 16 including the second via hole 18 through a barrier film (not shown) to form the second via hole. Landfill 18.

Next, the conductive film and the barrier film formed outside the second via hole 18 are removed to form the through electrode 19 electrically connected to the contact pad 11A.

Referring to FIG. 1G, the adhesive member 12 and the carrier substrate 13 are removed.

However, the above-described conventional technology has a problem that alignment margins are not secured when forming the second via hole 18 due to the small size of the wafer 10 inside the insulating film 16 embedded in the first via hole 15. have.

As a result, the second via hole 18 penetrates the wafer 10 outside the insulating film 16 embedded in the first via hole 15 so that the through electrode 19 is shorted with the wafer 10. Is generated.

An object of the present invention is to provide a method of manufacturing a semiconductor package suitable for improving the alignment margin of the through electrode forming step.

A method of manufacturing a semiconductor package according to an embodiment of the present invention includes forming a first via hole that exposes a contact pad of a circuit part by etching the wafer from a rear surface facing a front surface of a wafer on which a circuit part is formed, and the first via hole. Forming a through electrode by filling a gap; forming a mask pattern exposing the through electrode and the wafer around the wafer on the rear surface of the wafer; and etching the wafer exposed by the mask pattern. And forming a second via hole exposing side surfaces of the through electrode, removing the mask pattern, and filling an insulating film in the second via hole.

The first via hole is formed one per one contact pad.

At least two first via holes may be formed per one contact pad.

The forming of the first via hole may be performed by a photolithography process.

The forming of the first via hole may be performed by a laser drilling process.

And prior to forming the first via hole, backgrinding the back surface of the wafer.

And prior to backgrinding the back side of the wafer, attaching a carrier substrate to the front side of the wafer.

According to the present invention, since the alignment margin of the through-electrode forming process is improved, defects due to insufficient alignment margin are suppressed and the yield is improved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5A to 5H are cross-sectional views illustrating a method of manufacturing a semiconductor package using a through electrode according to a first embodiment of the present invention, and FIGS. 6 to 8 are plan views of FIGS. 5D, 5F, and 5G, respectively. to be.

Referring to FIG. 5A, the carrier substrate 53 is attached to the entire surface of the wafer 50 on which the bonding pad 51B is formed through the adhesive member 52.

The wafer 50 has a plurality of semiconductor chips and a scribe lane located between the semiconductor chips.

Although not shown, the semiconductor chip includes a circuit portion.

The circuit portion includes, for example, a data storage portion for storing data and a data processing portion for processing the data. The bonding pad 51B corresponds to an electrical contact of a circuit unit for connection with the outside.

The semiconductor chip includes a contact pad 51A electrically connected to a circuit portion therein, and the contact pad 51A and the bonding pad 51B are formed by a conductive connection member 51C penetrating through the insulating film 51D formed therebetween. Electrically connected.

Referring to FIG. 5B, the wafer 50 is thinly processed by back-grinding the back surface opposite to the front surface of the wafer 50.

Referring to FIG. 5C, the wafer 50 is turned upside down so that the back side of the wafer 50 faces upward, and then the opening having the opening in a position corresponding to the contact pad 51A on the back side of the wafer 50. 1 mask pattern 54 is formed.

5D and 6, the first via hole 55 exposing the contact pad 51B is formed by etching the wafer 50 from the rear surface using the first mask pattern 54.

The wafer 50 may be etched by a dry etching process.

In the embodiment shown in the drawings, a photolithography process is used to form the first via hole 55, but a laser drilling process may be used in addition to the photolithography process.

Referring to FIG. 5E, the first via hole 55 is filled to form the through electrode 56.

The through electrode 56 may be formed on the first mask pattern 54 including the first via hole 55 to form a conductive film through a barrier film (not shown), and to form a barrier film formed outside the first via hole 55. It can be formed by removing the conductive film.

Copper may be used as the conductive film. An electroplating process may be used as the conductive film.

Thereafter, the first mask pattern 54 is removed to protrude the through electrode 56 over the back surface of the wafer 50.

5F and 7, a second mask pattern 57 exposing the through electrode 56 and the wafer 50 around the through electrode 56 is formed, and an etching selectivity between the through electrode 56 and the wafer 50 is formed. Using the difference, the wafer 50 exposed by the second mask pattern 57 is selectively etched to form a second via hole 58 exposing the side surface of the through electrode 56.

5G and 8, the insulating layer 59 is formed on the back surface of the wafer 50 so that the second mask pattern 57 is removed and the second via hole 58 is buried.

The insulating layer 63 may be formed of any one of a silicon oxide layer SiO 2 and a polymer.

Next, the insulating layer 59 is etched entirely so that the through electrode 56 is exposed.

As a result of the front surface etching, the insulating layer 59 remains on the back surface of the wafer 50 except for the inside of the second via hole 58 and the through electrode 56.

Referring to FIG. 5H, the adhesive member 52 and the carrier substrate 53 attached to the entire surface of the wafer 50 are removed.

Subsequently, although not shown, the wafer 50 may be cut along the scribe lane to individualize the semiconductor chips, and the individualized semiconductor chips may be electrically connected to each other through a through electrode to form a stack package.

9A to 9H are cross-sectional views illustrating a method of manufacturing a semiconductor package using a through electrode according to a second embodiment of the present invention, and FIGS. 10 to 12 are plan views of FIGS. 9D, 9F, and 9G, respectively. to be.

In the second embodiment of the present invention, unlike in the first embodiment in which one through electrode 56 is formed in one contact pad 51B, at least two through electrodes 56 in one contact pad 51B are provided. ).

Referring to FIG. 9A, the carrier substrate 53 is attached to the entire surface of the wafer 50 on which the bonding pad 51B is formed via the adhesive member 52.

The wafer 50 has a plurality of semiconductor chips and a scribe lane located between the semiconductor chips.

Although not shown, the semiconductor chip includes a circuit portion.

The circuit portion includes, for example, a data storage portion for storing data and a data processing portion for processing the data. The bonding pad 51B corresponds to an electrical contact of a circuit unit for connection with the outside.

The semiconductor chip includes a contact pad 51A electrically connected to a circuit portion therein, and the contact pad 51A and the bonding pad 51B are formed by a conductive connection member 51C penetrating through the insulating film 51D formed therebetween. Electrically connected.

Referring to FIG. 9B, the wafer 50 is thinly processed by back-grinding the back surface opposite to the front surface of the wafer 50.

Referring to FIG. 9C, the wafer 50 is turned upside down so that the backside of the wafer 50 faces upward, and then at least two openings are positioned on the backside of the wafer 50 corresponding to the contact pads 51A. The first mask pattern 54 is formed.

9D and 10, at least two first via holes 55 are formed to expose the contact pad 51B by etching the wafer 50 from the rear surface using the first mask pattern 54.

The etching of the wafer 50 may be performed by a dry etching process.

In the embodiment shown in the drawings, a photolithography process is used to form the first via holes 55, but a laser drilling process may be used in addition to the photolithography process.

Referring to FIG. 9E, through vias 56 may be formed by filling the first via holes 55.

The through electrodes 56 form a conductive film on the first mask pattern 54 including the first via holes 55 through a barrier film (not shown), and the barrier film formed outside the first via holes 55. It can be formed by removing the conductive film.

Copper may be used as the conductive film. An electroplating process may be used as the conductive film.

Thereafter, the first mask pattern 54 is removed to protrude through electrodes 56 onto the back surface of the wafer 50.

9F and 11, the second mask pattern 57 exposing the through electrodes 56 and the wafer 50 around the through electrode 56 is formed, and the etching between the through electrode 56 and the wafer 50 is performed. Using the selectivity difference, the wafer 50 exposed by the second mask pattern 57 is selectively etched to form a second via hole 58 exposing side surfaces of the through electrodes 56.

9G and 12, the insulating layer 59 is formed on the back surface of the wafer 50 so that the second mask pattern 57 is removed and the second via hole 58 is buried.

The insulating layer 63 may be formed of any one of a silicon oxide layer SiO 2 and a polymer.

Next, the insulating layer 59 is etched entirely so that the through electrode 56 is exposed.

As a result of the front surface etching, the insulating layer 59 remains on the back surface of the wafer 50 except for the inside of the second via hole 58 and the through electrode 56.

9H, the adhesive member 52 and the carrier substrate 53 attached to the entire surface of the wafer 50 are removed.

Subsequently, although not shown, the wafer 50 may be cut along the scribe lane to individualize the semiconductor chips, and the individualized semiconductor chips may be electrically connected to each other through a through electrode to form a stack package.

Using the second embodiment, the size of the first via hole 55 is reduced compared to the first embodiment, so that the first via hole 55 embedding time is shortened. In addition, since the area of the insulating layer 59 may be increased compared to the through electrode 56, the capacitance of the through electrode 56 may be reduced, thereby improving electrical characteristics.

As described in detail above, since the through electrode having a small size is first formed, a mask pattern exposing the through electrode and the semiconductor chip around the semiconductor device is formed and the semiconductor chip around the through electrode is etched using the mask pattern as a mask. The alignment margin of the through electrode forming process is improved. Therefore, device defects caused by insufficient alignment margin are suppressed and the yield is improved.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

For example, in the above-described embodiments, the process is performed while the carrier substrate 53 is attached to the front surface of the wafer 30. However, the process is performed without attaching the carrier substrate 53 to the front surface of the wafer 30. You may proceed.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor package according to the prior art.

2-4 are plan views in the processes of FIGS. 1B, 1D and 1F, respectively.

5A to 5H are cross-sectional views illustrating a method of manufacturing a semiconductor package using a through electrode according to a first embodiment of the present invention.

6 to 8 illustrate planar structures in the processes of FIGS. 5D, 5F, and 5G, respectively.

9A to 9H are cross-sectional views illustrating a method of manufacturing a semiconductor package using a through electrode according to a second embodiment of the present invention.

10-12 are plan views in the processes of FIGS. 9D, 9F and 9G, respectively.

<Description of main parts of drawing>

50: wafer

51A: Contact Pad

52: adhesive member

53: carrier substrate

54, 57: first and second mask patterns

55, 58: 1st, 2nd via hole

56: through electrode

59: insulating film

Claims (7)

Etching the wafer from a rear surface opposite the front surface of the wafer on which the circuit portion is formed to form a first via hole exposing a contact pad of the circuit portion; Filling the first via hole to form a through electrode; Forming a mask pattern on the back surface of the wafer to expose the through electrode and the wafer around the wafer; Etching the wafer exposed by the mask pattern to form a second via hole exposing side surfaces of the through electrode; Removing the mask pattern; and Filling an insulating film in the second via hole; Semiconductor package manufacturing method comprising a. The method of claim 1, Wherein the first via holes are formed one per one contact pad. The method of claim 1, And at least two first via holes are formed per one contact pad. The method of claim 1, The method of claim 1, wherein the forming of the first via hole is performed by a photolithography process. The method of claim 1, The method of claim 1, wherein the forming of the first via hole is performed by a laser drilling process. The method of claim 1, Prior to forming the first via hole, further comprising backgrinding the back surface of the wafer. The method of claim 6, And attaching a carrier substrate to the front surface of the wafer prior to backgrinding the back surface of the wafer.
KR1020090107587A 2009-11-09 2009-11-09 Method for fabricating semiconductoer package KR20110050963A (en)

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Application Number Priority Date Filing Date Title
KR1020090107587A KR20110050963A (en) 2009-11-09 2009-11-09 Method for fabricating semiconductoer package

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KR20110050963A true KR20110050963A (en) 2011-05-17

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