KR20110049200A - Laminated chip device - Google Patents

Abstract

PURPOSE: A laminated chip device is provided to prevent a mistake while chip devices are mounted on a surface. CONSTITUTION: A first conductive pattern unit(C) is formed in an element and includes a through hole. A first conductive pattern unit(L1) is separated from the first conductive pattern unit in the element and is formed on the first conductive pattern unit. A third conductive pattern unit(L2) is separated from the first conductive pattern unit in the element, is formed in the lower part of the first conductive pattern unit, and is connected to the second conductive pattern unit through the through hole of the first conductive pattern unit. A resistance pattern unit is formed between the second and third conductive pattern units.

Description

Laminated chip device

The present invention relates to a stacked chip device, and more particularly, to a stacked chip device having no orientation.

In general, the resistor R serves to control the current flow or lower the voltage in the circuit. In particular, the resistor plays a role of impedance matching or the like in the AC circuit. The resistor is combined with other passive elements such as capacitor (C) or inductor (L) to implement various filters and performs the function of frequency selection as well as the removal of high frequency noise.

In addition, the capacitor (C) basically serves to cut off the DC and to pass the AC signal, and also constitutes a time constant circuit, a time delay circuit, an RC, and an LC filter circuit. The capacitor itself also serves to remove noise.

In addition, varistors are widely used as protection devices for protecting important electronic components and circuits from overvoltage (surge voltage) and static electricity because the resistance changes according to the applied voltage. In other words, no current flows through the varistors arranged in the circuit. However, if an overvoltage is applied to both ends of the varistor due to an overvoltage or the like exceeding a certain voltage, the resistance of the varistor decreases rapidly and almost all current flows to the varistor, and no current flows to other elements, so that the circuit in which the varistor is disposed is protected from overvoltage. .

The varistor acts as a capacitor in a steady state without overvoltage. Capacitors have parasitic inductance values, not just capacitance values. An inductor is a device that has a property of preventing a change in current when a current flows through the wire. Inductors have parasitic capacitance values in addition to inductance values. This changes the function of the device at a specific high frequency, which is called the self-resonant frequency.

The resistive-varistor composite chip formed by combining a resistive component and a varistor component together in a single chip removes noise that may occur in a high frequency line simultaneously with protection from overvoltage and static electricity. By combining the varistor element and the resistance element as described above, it is possible not only to effectively protect important electronic components, small motors and circuits from overvoltage, but also to ensure stable operation of electronic components or circuits by securing a stable power supply voltage and removing noise components. I can guarantee it.

Therefore, the combination of the inductor-varistor realizes a pi (π) type filter made of an inductor-capacitor having good high frequency noise rejection.

Such a resistance-varistor coupling element or an inductor-varistor coupling element immediately exhibits the function of the varistor when an abnormal overvoltage in the circuit is introduced, thereby protecting the electronic component or circuit from the overvoltage and removing noise components.

In particular, in recent years, in response to the miniaturization of electronic devices, demands for highly integrated circuit chip elements have increased. Accordingly, RC filters, LV filters, LC filters and the like are used.

Compared with the conventional RC filter and LV filter, the LV filter tends to have better radiation characteristics than the RC filter. As a result, the LV filter is mainly employed where a better attenuation characteristic is required.

By the way, both the conventional RC filter and the LV filter have directivity. The RC filter has the vertical direction, and the LV filter or the LC filter has the vertical direction.

Looking at the problem of the device having the directionality as described above, an additional process for inserting the direction recognition mark at the time of manufacturing is required, and the work efficiency is low. In addition, since a device such as a camera must be mounted in order to recognize the direction when screening or taping, an additional cost occurs. In addition, mistakes in surface mount (SMT) operation can be mistaken.

In particular, when the device having the directional element is installed in the design circuit, if it is incorrectly installed without considering the directionality, it may not be able to perform its function and the circuit wiring may be twisted.

The present invention has been proposed to solve the above-described problems, and an object thereof is to provide a stacked chip device with no directionality.

In order to achieve the above object, a stacked chip device according to a preferred embodiment of the present invention includes: a first conductive pattern portion formed inside the body and having a through hole; A second conductive pattern portion formed on the first conductive pattern portion and spaced apart from the first conductive pattern portion in the body; And a third conductive pattern portion formed below the first conductive pattern portion spaced apart from the first conductive pattern portion in the body, and connected to the second conductive pattern portion through the through hole of the first conductive pattern portion.

According to another aspect of the present invention, there is provided a stacked chip device including: a first conductive pattern part formed inside a body and having a through hole; A second conductive pattern portion formed on the first conductive pattern portion and spaced apart from the first conductive pattern portion in the body; A third conductive pattern portion formed below the first conductive pattern portion spaced apart from the first conductive pattern portion in the body, and connected to the second conductive pattern portion through a through hole of the first conductive pattern portion; And a resistance pattern portion formed in the through hole and formed between the second conductive pattern portion and the third conductive pattern portion.

According to still another aspect of the present invention, there is provided a stacked chip device, including: a first conductive pattern part formed inside the body and having a first through hole; A second conductive pattern portion formed on the first conductive pattern portion and spaced apart from the first conductive pattern portion in the body; A third conductive pattern part spaced apart from the first conductive pattern part in the body and formed under the first conductive pattern part, and connected to the second conductive pattern part through a first through hole of the first conductive pattern part; And a resistance pattern portion formed on an outer surface of the body, and one end of which is connected to at least one conductive pattern portion of the second conductive pattern portion and the third conductive pattern portion through a second through hole formed in the body.

Preferably, the first conductive pattern portion includes a pattern structure of a capacitor or a varistor, the second conductive pattern portion includes a pattern structure of an inductor, and the third conductive pattern portion includes a pattern structure of an inductor.

Preferably, the first conductive pattern portion includes: a first inner electrode pattern formed to be connected to an external terminal of the first side of the body; A second internal electrode pattern formed to be connected to an external terminal of a second side of the body; A common ground pattern formed to be connected to an external terminal of the third side of the body and spaced apart from the first and second internal electrode patterns to have an area overlapping the first and second internal electrode patterns: and an external terminal of the body The third internal electrode pattern may include a third internal electrode pattern that is connected to the through hole in the body without contact with and is formed to be spaced apart from the common ground pattern and overlaps the common ground pattern.

The first inner electrode pattern and the second inner electrode pattern are formed on the same sheet, and the third inner electrode pattern is formed on a sheet different from the sheet on which the first inner electrode pattern and the second inner electrode pattern are formed. Alternatively, the first inner electrode pattern, the second inner electrode pattern and the third inner electrode pattern are formed in different sheets, respectively. Alternatively, the first inner electrode pattern, the second inner electrode pattern, and the third inner electrode pattern are formed to be spaced apart from each other on the same sheet.

The first conductive pattern portion may include: a first inner electrode pattern formed to be connected to an external terminal on a first side of the body; A second internal electrode pattern formed to be connected to an external terminal of a second side of the body; A common ground pattern formed to be connected to an external terminal of the third side of the body and spaced apart from the first and second internal electrode patterns to have an area overlapping the first and second internal electrode patterns: and an external terminal of the body The third internal electrode pattern may include a third internal electrode pattern connected to the first through hole in the body without contact with and having a region overlapping with the common ground pattern to overlap the common ground pattern.

The resistive pattern portion is filled with a resist paste in the through hole.

The second conductive pattern portion is formed inside the body without contact with an external terminal of the body, one end of which is in contact with the second through hole and the other end of which is in contact with the resistance pattern.

The third conductive pattern portion is formed inside the body without contacting the outer terminal of the body, one end of the contact portion is in contact with the second through hole and the other end is in contact with the resistance pattern portion.

The other end of the resistance pattern portion is connected to either an external terminal on the first side of the body and an external terminal on the second side.

According to the present invention having such a configuration, since the capacitor or varistor is placed in the center and the inductor is arranged up and down, there is no directivity in the up, down, left and right directions, and the interference between the elements is reduced compared to the existing configuration.

On the other hand, since the structure of the LC filter or LV filter has a superior radiation characteristics than the conventional RC filter.

Since there is no directionality, there is no need to insert a direction recognition mark, thereby improving work efficiency.

Since there is no directionality, there is no need for a device such as a camera for direction recognition when screening or taping, so no additional cost is incurred.

Since there is no directionality, misalignment does not occur in surface mount work.

Hereinafter, a multilayer chip device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings. Prior to the detailed description of the present invention, the terms or words used in the specification and claims described below should not be construed as being limited to the ordinary or dictionary meanings. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only one of the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

1 is a view for explaining the internal configuration of a stacked chip device according to an embodiment of the present invention, Figure 2 is an external perspective view of a stacked chip device according to an embodiment of the present invention.

The stacked chip device according to an embodiment of the present invention, the first conductive pattern portion (C) is formed in the center portion of the inside of the body (1) having a through hole vertically penetrating the inner center; A second conductive pattern portion L1 spaced apart from the first conductive pattern portion C in the body 1 and formed on the first conductive pattern portion C; And a first conductive pattern portion C spaced apart from the first conductive pattern portion C, and formed below the first conductive pattern portion C. The second conductive pattern is formed through the through hole of the first conductive pattern portion C. The third conductive pattern part L2 connected to the part L1 is included.

The first conductive pattern portion C includes a pattern structure of a capacitor or a varistor, and the second conductive pattern portion L1 and the third conductive pattern portion L2 each include a pattern structure of an inductor. Accordingly, the stacked chip device according to the embodiment of the present invention is composed of an LV filter or an LC filter.

The first conductive pattern portion C may include the first internal electrode patterns 81, 82, 83, 84; 121, which are formed to be connected to the external terminals 401, 402, 403, 404 on the first side of the body 1. 122, 123, 124; Second internal electrode patterns 85, 86, 87, 88; 125, 126, 127, 128 formed to be connected to the external terminals 405, 406, 407, 408 on the second side of the body 1; The first and second internal electrode patterns (81, 82, 83, 84; 121, 122, 123, 124) formed to be connected to an external terminal (at least one of 409 and 410) on the third side of the body 1; ), (85, 86, 87, 88; 125, 126, 127, 128)) to be spaced apart from the first and second internal electrode patterns ((81, 82, 83, 84; 121, 122, 123, 124). ), (85, 86, 87, 88; 125, 126, 127, 128)) and a common ground pattern 72, 92, 112, 132 having an overlapping area: and external terminals 401-of the body 1. The third internal electrode pattern having a region connected to the through hole in the body 1 without contact with the 410 and spaced apart from the common ground patterns 92 and 112 and overlapping the common ground patterns 92 and 112. (102, 104, 106, 108).

The common ground pattern 72 is formed in the longitudinal direction at the center of the upper surface of the sheet 70, and both ends (or any one end) are exposed. Through-holes 72a, 72b, 72c, 72d spaced apart from each other are formed in the central portion in the longitudinal direction on the upper surface of the sheet 70. Since the pattern form of the sheets 90, 110, 130 is the same as the pattern form of the sheet 70 described above, it will be understood that the description of the pattern form of the sheet 70 described above will be fully understood without the description.

The first inner electrode patterns 81, 82, 83, and 84 are formed to be spaced apart from one another in the longitudinal direction on the upper surface of the sheet 80, and the second inner electrode patterns 85, 86, 87, and 88 are formed of the sheet. On the upper surface of the 80 is formed to be spaced apart from each other in the longitudinal direction. Through-holes 80a, 80b, 80c, and 80d spaced apart from each other are formed in the central portion in the longitudinal direction on the upper surface of the sheet 80. That is, the pattern form in the sheet 80 is a shape in which one first internal electrode pattern and one second internal electrode pattern are formed to face one-to-one with respect to one through hole, and each first internal electrode pattern is formed. And one end of the second inner electrode pattern is exposed for contact with the corresponding outer terminal.

Since the pattern form of the sheet 120 is the same as the pattern form of the sheet 80 described above, it will be understood that the description of the pattern form of the sheet 80 described above will be fully understood without the description.

The third internal electrode patterns 102, 104, 106, and 108 are formed to be spaced apart from each other at the center of the upper surface of the sheet 100. Corresponding through holes 102a, 104a, 106a and 108a are formed in each of the third internal electrode patterns 102, 104, 106 and 108.

Of the electrode patterns formed on the plurality of sheets used for the first conductive pattern portion C described above, only the third internal electrode patterns 102, 104, 106, and 108 contact the through holes 102a, 104a, 106a, and 108a. do.

The second conductive pattern portion L1 is formed to be spaced apart from each other on the sheet 10, but is connected to the external terminals 401, 402, 403, and 404 on the first side of the body 1, and has a via hole at one side thereof. Connection patterns 12, 14, 16, and 18 formed with 12a, 14a, 16a, and 18a; Internal electrode patterns 22, 24, 26, and 28 formed on the sheet 20 to be spaced apart from each other, and having via holes 22a, 24a, 26a, and 28a formed at one side thereof; Internal electrode patterns 32, 34, 36, and 38 formed on the sheet 30 to be spaced apart from each other, and having via holes 32a, 34a, 36a, and 38a formed on one side thereof; Internal electrode patterns 42, 44, 46, and 48 formed on the sheet 40 to be spaced apart from each other, and having via holes 42a, 44a, 46a, and 48a formed at one side thereof; Internal electrode patterns 52, 54, 56, and 58 formed on the sheet 50 to be spaced apart from each other, and having via holes 52a, 54a, 56a, and 58a formed at one side thereof; And internal electrode patterns 62, 64, 66, and 68 formed on the sheet 60 to be spaced apart from each other, and having via holes 62a, 64a, 66a, and 68a formed at one side thereof.

The internal electrode pattern of the second conductive pattern portion L1 is wound in the vertical direction through the via hole for each unit element.

The third conductive pattern part L2 is formed to be spaced apart from each other on the sheet 190, but is connected to the external terminals 405, 406, 407, and 408 on the second side of the body 1. , 196, 198); Internal electrode patterns 182, 184, 186, and 188 formed on the sheet 180 to be spaced apart from each other, and having via holes 182a, 184a, 186a, and 188a formed on one side thereof; Internal electrode patterns 172, 174, 176, and 178 formed on the sheet 170 and having via holes 172a, 174a, 176a, and 178a formed at one side thereof; Internal electrode patterns 162, 164, 166, and 168 that are formed to be spaced apart from each other in the sheet 160, and have via holes 162a, 164a, 166a, and 168a formed on one side thereof; Internal electrode patterns 152, 154, 156, and 158 formed on the sheet 150 to be spaced apart from each other, and having via holes 152a, 154a, 156a, and 158a formed on one side thereof; And internal electrode patterns 142, 144, 146, and 148 that are formed to be spaced apart from each other, and have via holes 142a, 144a, 146a, and 148a formed on one side thereof.

The internal electrode pattern of the third conductive pattern portion L2 is wound in the vertical direction through the via hole for each unit element.

The stacking number of the first conductive pattern portion C described above is adjustable according to the capacitance required for each unit element, and the stacking number of the second conductive pattern portion L1 and the third conductive pattern portion L2 is a unit element. It can be adjusted according to the inductance required.

1 and 2 are divided into four unit elements.

In Fig. 1, reference numerals DM1 and DM2 are dummy layers. The dummy layer DM1 is formed by stacking a plurality of sheets 210, and the dummy layer DM2 is formed by stacking a plurality of sheets 310. Through holes spaced apart from each other are formed in the sheets of the dummy layers DM1 and DM2. Although the number of sheets constituting each of the dummy layers DM1 and DM2 is expressed in plural, the sheet may be composed of one sheet having a thickness sufficient to perform a dummy role.

In FIG. 1, reference numeral 200 denotes a cover sheet.

When the stacked chip device according to the exemplary embodiment of the present invention is cut vertically, each unit device has a cross section as shown in FIG. 3. FIG. 3 is a schematic diagram and is simply shown centering on a characteristic part instead of the complicated reference numeral as in FIG. 1.

In FIG. 3, reference numeral C corresponds to the first conductive pattern portion of FIG. 1, reference numeral L1 corresponds to the second conductive pattern portion of FIG. 1, and reference numeral L2 corresponds to the third conductive pattern portion of FIG. 1. do.

 In FIG. 3, reference numeral C1 corresponds to the first internal electrode pattern in the first conductive pattern portion, reference C2 corresponds to the second internal electrode pattern in the first conductive pattern portion, and reference numeral C3 denotes the first conductive pattern. It corresponds to the 3rd internal electrode pattern in a part.

In Fig. 3, reference numeral 500 denotes a through hole. The through hole 500 of FIG. 3 is a collection of through holes for each unit element of the chip device of FIG. 1. In other words, when the sheets of the dummy layers DM1 and DM2 and the sheets 70, 80, 90, 100, 110, 120, and 130 are sequentially stacked as in FIG. 1, for example, through holes are formed to penetrate vertically. Through holes 500 in FIG. 3 become through holes 72a, 80a, 92a, 102a, 112a, 120a, and 132a, and dummy layers perpendicularly contacting the upper and lower portions of the through holes.

FIG. 4 is an equivalent circuit diagram of FIG. 3. In the stacked chip device according to the exemplary embodiment of the present invention, three capacitors (or varistors) are formed at the center to form a pi (π) type LC filter or an LV filter of five stages.

As described above, the implementation of the 5-stage configuration is as follows. A company's existing chip device may have a structure in which an inductor is disposed at an upper portion, a three-layer capacitor is disposed at a lower portion, and an inductor and a capacitor are individually connected to input / output terminals. In this case, however, capacitors cannot be disposed between the inductors due to the structure, so that a practical five-stage filter cannot be realized.

The company's existing chip device may have a structure (five layers in total) in which inductors and capacitors are stacked alternately and inductors and capacitors are individually connected to input and output terminals. In this case, interference between the capacitor layer and the inductor layer stacked up and down is generated, thereby causing a cross talk problem. Therefore, since the dummy layer must be interposed between the capacitor layer and the inductor layer, a problem arises in that the thickness of the chip element is increased.

However, in the stacked chip device according to the exemplary embodiment of the present invention, a five-stage pi (π) LC filter or LV having no directivity in the up, down, left, and right directions by arranging inductors up and down with three capacitors (or varistors) in the center thereof. Not only was it a filter, but it also minimized the interference between devices. That is, in the existing chip device of Company B, the interference between the devices is generated at four places as the inductor and the capacitor are alternately stacked, whereas the stacked chip device according to the embodiment of the present invention may generate the interference between the devices at two places. . According to the comparison, the stacked chip device according to the exemplary embodiment of the present invention has a low profile and a low number of processes in the manufacturing process as well as an improved design freedom.

On the other hand, the stacked chip device according to the embodiment of the present invention shows an attenuation characteristic that is about three times better as the number of stages increases compared to the existing LV filter. Of course, the stacked chip device according to the embodiment of the present invention has the structure of the LC filter or the LV filter, so that the radiation characteristics are superior to the conventional RC filter. There is no need for a process of inserting the direction recognition mark due to the lack of directivity in the up, down, left and right directions, thereby improving work efficiency. Since there is no up and down direction, there is no need for a device such as a camera to recognize the direction when screening or taping, so that no additional cost is generated and no misunderstanding occurs during surface mounting.

5 is a first modified example of the stacked chip device according to the embodiment of the present invention.

In comparison with the embodiment of the present invention, the first modification differs in the arrangement of the internal electrode patterns in the first conductive pattern portion C. That is, in the embodiment of the present invention, the first inner electrode pattern and the second inner electrode pattern are formed on the same sheet, but in the first modification, they are formed on different sheets. On the other hand, there is also a slight difference in the arrangement of the common ground pattern. Accordingly, the total number of sheets in the first modification may be larger than the total number of sheets in the embodiment of the present invention.

This first modification differs only from the embodiment of the present invention in the arrangement of the internal electrode patterns, and is the same in terms of function and effect.

6 is a second modified example of the stacked chip device according to the embodiment of the present invention.

Compared with the embodiment of the present invention, the second modification differs in the arrangement of the internal electrode patterns in the first conductive pattern portion C. FIG. That is, in the embodiment of the present invention, the first inner electrode pattern and the second inner electrode pattern are formed on the same sheet, and the third inner electrode pattern is formed on a sheet different from the sheet on which the first inner electrode pattern and the second inner electrode pattern are formed. However, in the second modification, the first to third internal electrode patterns are formed to be spaced apart from each other on the same sheet.

In the second modification, the first conductive pattern portion C is made of a sheet having a dielectric constant K of approximately 800.

Therefore, the total number of sheets in the second modification is smaller than the total number of sheets in the embodiment of the present invention.

This second variant differs only from the embodiment of the present invention in the arrangement of the internal electrode patterns, and is almost identical in function and effect. The second variant easily forms an attenuation band notch due to the coupling between the capacitors due to the high capacitance.

7 is a third modified example of the stacked chip device according to the embodiment of the present invention.

The third modified example is different from the embodiment of the present invention in that the resistance pattern part 600 is further provided. The resistance pattern part 600 means that the through hole 500 is filled with a resistor paste. In the third modification, the rest of the configuration except for the resistance pattern unit 600 is the same as the embodiment of the present invention.

According to the third modification, it is possible to implement an RLV filter or an RLC filter having no directionality of up, down, left and right.

8 is a fourth modified example of the stacked chip device according to the embodiment of the present invention.

The fourth modified example shows an RLV filter or RLC filter having a structure different from that of the third modified example.

In the above-described embodiments of the present invention and the first to third modified examples, one through hole is provided, but the fourth modified example includes the first through hole 500 and the second through holes 510 and 520. That is, the first through hole 500 of the fourth modified example corresponds to the through hole of the first exemplary embodiment and the first to third modified examples. The second through holes 510 and 520 are positioned on a vertical extension line of the first through hole 500. One side of the second through hole 510 is exposed to the central portion of the upper surface of the body 1, and the other side of the second through hole 510 is in contact with the second conductive pattern part L1. One side of the second through hole 520 is exposed to the center of the bottom surface of the body 1, and the other side of the second through hole 520 is in contact with the third conductive pattern part L2.

In the fourth modified example, the resistance pattern 600 is formed on the upper surface of the body 1, one end of the resistance pattern 600 is in contact with an external terminal of the first side surface, and the other end of the resistance pattern 600 is second. Covers the through hole 510. On the other hand, the second through hole 520 of the fourth modification is covered by the pattern 530 patterned with Ag paste. Of course, depending on the situation, the pattern 530 may be a resist pattern patterned using a resist paste. That is, the mounting position of the resistance pattern 600 may be the upper surface or the bottom surface of the body 1. On the other hand, the resistance pattern 600 may be provided in both the upper surface and the lower surface of the body 1.

In the fourth modification, since the resistance pattern 600 and the pattern 530 are formed on the outer surface of the body 1, the cover layer 700 for protecting the resistance pattern 600 and the pattern 530 is provided separately. Lose.

The fourth modification described above is different from the other modifications and examples in which the resistance pattern 600 is formed on the outer surface of the body 1, in which the resistance pattern is formed inside the body 1, but the third modification is As shown in FIG. 1, it is possible to implement an RLV filter or an RLC filter having no direction in up, down, left, and right directions.

FIG. 9 is a diagram illustrating an example in which the internal electrode patterns of the stacked chip device illustrated in FIG. 1 are implemented differently.

Those skilled in the art can easily understand the configuration of the stacked chip device according to the exemplary embodiment of the present invention by the description of the above-described description of FIGS. Even without the description of FIG. 1, the configuration of FIG. 9 may be easily understood by the description of the above-described FIGS. 1 to 4 and the description of the modifications.

In FIG. 9, only the first conductive pattern portion C, the second conductive pattern portion L1, and the third conductive pattern portion L2 are illustrated, and the dummy layer is not illustrated.

On the other hand, the present invention is not limited only to the above-described embodiments and can be carried out by modifications and variations within the scope not departing from the gist of the present invention, the technical idea that such modifications and variations are also within the scope of the claims Must see

1 is a view for explaining the internal configuration of a stacked chip device according to an embodiment of the present invention.

2 is an external perspective view of a stacked chip device according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of any one of a plurality of unit devices of a stacked chip device according to an exemplary embodiment of the present invention.

4 is an equivalent circuit diagram of FIG. 3.

5 is a first modified example of the stacked chip device according to the embodiment of the present invention.

6 is a second modified example of the stacked chip device according to the embodiment of the present invention.

7 is a third modified example of the stacked chip device according to the embodiment of the present invention.

8 is a fourth modified example of the stacked chip device according to the embodiment of the present invention.

FIG. 9 is a diagram illustrating an example in which the internal electrode patterns of the stacked chip device illustrated in FIG. 1 are implemented differently.

Description of the Related Art

C: first conductive pattern portion L1: second conductive pattern portion

L2: 3rd conductive pattern part

Claims (16)

A first conductive pattern portion formed inside the body and having a through hole; A second conductive pattern portion formed on the first conductive pattern portion and spaced apart from the first conductive pattern portion in the body; And The third conductive pattern part is spaced apart from the first conductive pattern part in the body and is formed under the first conductive pattern part, and is connected to the second conductive pattern part through a through hole of the first conductive pattern part. Multilayer chip device, characterized in that. A first conductive pattern portion formed inside the body and having a through hole; A second conductive pattern portion formed on the first conductive pattern portion and spaced apart from the first conductive pattern portion in the body; A third conductive pattern part spaced apart from the first conductive pattern part in the body, and formed under the first conductive pattern part, and connected to the second conductive pattern part through a through hole of the first conductive pattern part; And And a resistance pattern portion formed in the through hole and formed between the second conductive pattern portion and the third conductive pattern portion. A first conductive pattern portion formed inside the body and having a first through hole; A second conductive pattern portion formed on the first conductive pattern portion and spaced apart from the first conductive pattern portion in the body; A third conductive pattern spaced apart from the first conductive pattern portion in the body, and formed under the first conductive pattern portion, and connected to the second conductive pattern portion through a first through hole of the first conductive pattern portion; part; And Is formed on the outer surface of the body, one end comprises a resistance pattern portion connected to at least one conductive pattern portion of the second conductive pattern portion and the third conductive pattern portion through a second through hole formed in the interior of the body. Multilayer chip device. The method according to any one of claims 1 to 3, The first conductive pattern unit is a stacked chip device, characterized in that it comprises a pattern structure of a capacitor or varistor. The method according to any one of claims 1 to 3, The second conductive pattern unit is a stacked chip device, characterized in that it comprises a pattern structure of the inductor. The method according to any one of claims 1 to 3, The third conductive pattern unit is a stacked chip device, characterized in that it comprises a pattern structure of the inductor. The method according to claim 1 or 2, The first conductive pattern portion, A first internal electrode pattern formed to be connected to an external terminal of the first side of the body; A second internal electrode pattern formed to be connected to an external terminal of the second side of the body; A common ground pattern formed to be connected to an external terminal of the third side surface of the body and spaced apart from the first and second internal electrode patterns, and having a region overlapping with the first and second internal electrode patterns; and And a third internal electrode pattern connected to the through hole inside the body without contact with an external terminal of the body, and spaced apart from the common ground pattern, the third inner electrode pattern having a region overlapping with the common ground pattern. Multilayer chip device. The method of claim 7, The first inner electrode pattern and the second inner electrode pattern are formed on the same sheet, and the third inner electrode pattern is formed on a sheet different from the sheet on which the first inner electrode pattern and the second inner electrode pattern are formed. Stacked chip device characterized in that. The method of claim 7, The first and second internal electrode patterns, the second internal electrode pattern and the third internal electrode pattern, the stacked chip device, characterized in that formed in different sheets. The method of claim 7, The first and second internal electrode patterns, the second internal electrode pattern and the third internal electrode pattern is a stacked chip device, characterized in that formed on the same sheet spaced apart from each other. The method of claim 3, The first conductive pattern portion, A first internal electrode pattern formed to be connected to an external terminal of the first side of the body; A second internal electrode pattern formed to be connected to an external terminal of the second side of the body; A common ground pattern formed to be connected to an external terminal of the third side surface of the body and spaced apart from the first and second internal electrode patterns, and having a region overlapping with the first and second internal electrode patterns; and A third internal electrode pattern connected to the first through hole in the body without contact with an external terminal of the body, and spaced apart from the common ground pattern, and having a region overlapping with the common ground pattern; Stacked chip device, characterized in that. The method according to claim 2, And the resistor pattern portion is filled with a resistor paste in the through hole. The method of claim 3, The second conductive pattern portion is formed in the interior of the body without contact with the external terminal of the body, one end portion is in contact with the second through hole, the other end is laminated, characterized in that the contact with the resistance pattern portion Chip elements. The method of claim 3, The third conductive pattern portion may be formed inside the body without contact with an external terminal of the body, wherein one end portion contacts the second through hole and the other end portion contacts the resistance pattern portion. Chip elements. The method of claim 3, And the other end of the resistor pattern portion is connected to any one of an external terminal of an external terminal of a first side and an external terminal of a second side of the body. The method according to any one of claims 1 to 3, The stacked chip device may include a plurality of unit devices arranged in parallel and implemented as an array chip.

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