KR20110033330A - Program method of a non volatile memory device - Google Patents

Abstract

The present invention relates to a method of programming a nonvolatile memory device, the method of programming a nonvolatile memory device having a string structure in which a source select transistor, a plurality of memory cells, and a drain transistor are connected in series, the Nth of the plurality of memory cells. And sequentially programming a memory cell adjacent to the source select transistor from a memory cell, and sequentially programming a memory cell adjacent to the drain transistor from an N + 1th memory cell. It starts.

Description

Program method of a nonvolatile memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of programming a nonvolatile memory device, and more particularly, to a method of programming a nonvolatile memory device capable of performing a stable program operation by suppressing program disturb.

The memory cell array of the NAND flash memory device among the nonvolatile memory devices includes a plurality of memory cell strings connected to respective bit lines. Each of the memory cell strings includes a drain select transistor, a plurality of memory cells, and a source select transistor. The gate terminal of each of these devices is connected to a word line and operates in response to a signal applied from the bit line and the word line.

In general, a programming method of a flash memory device is performed by electrons moving from a channel of a cell selected by a Fowler Nordheim tunneling method to a floating gate.

1 is a diagram illustrating a memory block and a program operation of a NAND flash memory device.

Referring to FIG. 1, a NAND flash memory device includes a memory cell array, and the memory cell array is divided into a plurality of memory blocks. Each memory cell block includes a plurality of strings (only two are shown for convenience; ST1 and ST2).

Each cell string has a structure in which a drain select transistor DST, a plurality of memory cells C0 to Cn, and a source select transistor SST are connected in series. Here, the drain select transistors DST included in each of the cell strings ST1 and ST2 are connected to the corresponding bit lines BL1 and BL2, respectively, and the source select transistors SST are connected in parallel to the common source line CSL. Connected. Meanwhile, gates of the drain select transistors DST included in each of the cell strings ST1 and ST2 are connected to each other to form a drain select line DSL, and gates of the source select transistors SST are connected to each other to form a source select line. (SSL). In addition, the gates of the memory cells C0 to Cn are connected to each other to form respective word lines WL0 to WLn, and each word line is a page unit. At this time, two, four, eight, sixteen, or thirty-two pages become one page group.

When a program operation is performed in the memory cell array having the above structure, a program voltage Vpgm is applied to a word line (for example, WLi) to which a selected memory cell (a memory cell to be programmed) is connected, and to the remaining word lines, Pass voltage Vpass is applied. In addition, a ground voltage (eg, 0 V) is applied to the bit line BL2 connected to the string (eg, ST2) including the selected memory cell, and a program inhibit voltage (eg, is applied to the bit line connected to the other string. For example, Vcc) is applied. When the program operation is performed according to the voltage condition, the program operation is performed by the voltage difference between the word line and the channel region in the selected memory cell Ci. On the other hand, in the memory cell included in the string ST1 to which the program inhibit voltage is applied, when the program voltage Vpgm is applied to the word line, channel boosting occurs due to capacitor coupling to increase the voltage in the channel region and lower the voltage difference. Program operation does not work. This is called program disturb.

In addition, during the program operation, a disturb phenomenon due to hot carrier injection occurs in the memory cell C0 adjacent to the source select transistor SST, thereby reducing the reliability of the program operation of the device.

SUMMARY OF THE INVENTION The present invention provides a method of programming a nonvolatile memory device having a string structure in which a plurality of memory cells are connected in series, wherein memory cells connected from word lines 0 to N are precharged through a source line and N Memory cells connected sequentially from word line 1 to word line 0, and connected to the word line after word line N + 1, precharge the string through the bit line and sequentially from word line N + 1 to the last word line. The present invention provides a method of programming a nonvolatile memory device capable of preventing hot carrier generation by programming to prevent program disturb.

A method of programming a nonvolatile memory device according to an embodiment of the present invention is a method of programming a nonvolatile memory device having a string structure in which a source select transistor, a plurality of memory cells, and a drain transistor are connected in series. Sequentially programming a memory cell adjacent to the source select transistor from an Nth memory cell, and sequentially programming a memory cell adjacent to the drain transistor from an N + 1th memory cell.

The programming of the N-th memory cell may include applying a source voltage applied to a source line as a positive voltage, turning on the source select transistor, and selecting a selected memory cell among the plurality of memory cells. Applying a program voltage to the memory cell and applying a pass voltage to the unselected memory cells, wherein the N + 1 th memory cell and the N + 2 th memory cell are turned off to reduce the channel capacitor.

In the step of turning on the source select transistor, the drain select transistor is turned off.

In the step of sequentially programming the memory cells adjacent to the source select transistor from the Nth memory cell, a positive voltage is applied to a source line to supply a channel voltage of a string.

The sequentially programming of the memory cell adjacent to the drain transistor from the N + 1 th memory cell may include precharging a bit line connected to the drain select transistor, turning on the drain select transistor, and the plurality of memories. Applying a program voltage to a selected memory cell among the cells, and applying a pass voltage to an unselected memory cell.

According to an embodiment of the present invention, in a method of programming a nonvolatile memory device having a string structure in which a plurality of memory cells are connected in series, memory cells connected to word lines from word lines 0 to N are precharged through a source line. Memory cells connected sequentially from word line N to word line 0, and connected to word lines after word line N + 1, precharge the string through the bit line, and sequentially from word line N + 1 to the last word line. The program disturb can be prevented by suppressing hot carrier generation.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

2 is a string structure illustrating a program method of a nonvolatile memory device according to an embodiment of the present invention.

3 is a waveform diagram of an applied voltage for explaining a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

A method of programming a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 2 and 3 as follows.

First, a program order is set based on a set word line (for example, word line WL4) among a plurality of word lines WL0 to WL31. As an example, the word line WL0 is sequentially programmed from the set word line WL4. Thereafter, the last word line WL31 is sequentially programmed from the next word line WL5 of the set word line WL4.

First, the method of sequentially programming the word line WL0 from the set word line WL4 will be described in detail.

First, a source voltage applied to a source line is applied as a positive voltage (for example, 4.5V). Thereafter, a positive voltage (for example, 4.5V) is applied to the source select line SSL to turn on the source select transistor. As a result, generation of hot carriers generated by applying 0 V to the source select transistor can be suppressed. At this time, the drain select transistor is turned off by applying OV.

Thereafter, a program voltage (for example, 18V) is applied to the selected word line (for example, WL4), and a pass voltage is applied to the word lines (WL0 to WL3) adjacent to the source select line (SSL) than the selected word line (WL4). (Eg 10V) is applied. This causes the string's channel voltage to self-boost and rise to about 8V. In addition, 3V and 0V are applied to the word line after the word line WL4, that is, the selected word line WL4 and adjacent word lines (for example, WL5 and WL6) to turn off the memory cell. This reduces the total boosting capacitor of the string. This means that as the channel capacitor of the string decreases, the channel boosting potential decreases, so that the occurrence of hot carriers is suppressed. In this case, preferably, a voltage of 3V is applied to the next word line WLn + 1 of the selected word line WLn, and a voltage of 0V is preferably applied to the next word line WLn + 2. This is to suppress hot carrier generation due to a sudden channel cutoff by applying a voltage of 3V to the next word line WLn + 1.

Thereafter, the potential of the source select line SSL is discharged to 0V. Subsequently, applying a turn-on voltage of 0.7 V to the drain select line maintains or discharges the channel potential of the string according to the potential of the bit line. For example, if the data to be programmed is "1", the bit line maintains a high level (0.5V), and the string potential remains at the boosting level. If the data to be programmed is "0", the bit line is at a low level (0V). ), The string potential is lower than the boosting level. As a result, the memory cell connected to the selected word line WL4 is programmed.

The programming method described above is used to program the word line WL0 from the word line WL4 in the order of the word lines WL0.

After the program operation of the memory cell connected to the word line WL0 is completed, the program operation of the memory cell connected to the word line WL5 is performed. The program operation of the memory cell connected to the word line WL5 will be described in more detail. A voltage of 0V is applied to the source select line SSL and a turn-on voltage of 4.5V is applied to the drain select line DSL. At this time, the bit line is precharged to a high level. Thereafter, a program voltage 18V is applied to the word line WL5, and a pass voltage 10V is applied to the remaining word lines WL0 to WL31 except for WL5. As a result, the channel of the string is self-boosted, and the bit line potential is changed according to the program data so that the potential of the string is changed and programmed.

The above-described programming method is used to program the word lines WL5 to the word lines WL31 in this order.

In an embodiment of the present invention, the word line, which is a reference, is set to WL4, but the word line may be changed without being limited thereto.

4 is a graph illustrating an HCI disturb phenomenon of a word line WL0 according to a channel capacitor.

 Referring to FIG. 4, as channel capacitors decrease, HCI disturbance decreases, and when there are 15 or less boosting participating cells, HCI disappears. This is beneficial to boosting as the channel capacitor decreases, but the result is a decrease in channel boosting due to the increase in the boosting leakage current.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1 is a diagram illustrating a memory block and a program operation of a NAND flash memory device.

2 is a string structure illustrating a program method of a nonvolatile memory device according to an embodiment of the present invention.

3 is a waveform diagram of an applied voltage for explaining a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

4 is a graph illustrating an HCI disturb phenomenon of a word line WL0 according to a channel capacitor.

Claims (9)

A method of programming a nonvolatile memory device having a string structure in which a source select transistor, a plurality of memory cells, and a drain transistor are connected in series, Sequentially programming a memory cell adjacent to the source select transistor from an Nth memory cell of the plurality of memory cells in a direction of the source select transistor; And And sequentially programming a memory cell adjacent to the drain transistor from the N + 1 th memory cell toward the drain select transistor. The method of claim 1, Programming the N-th memory cell Applying a source voltage applied to a source line as a positive voltage; Turning on the source select transistor; And A program voltage is applied to a selected memory cell among the plurality of memory cells, and a pass voltage is applied to an unselected memory cell, and the N + 1 th memory cell and the N + 2 th memory cell are turned off to reduce the channel capacitor. A method for programming a nonvolatile memory device comprising the steps. The method of claim 2, And turning off the drain select transistor in the step of turning on the source select transistor. The method of claim 1, Sequentially programming the memory cells adjacent to the source select transistor from the Nth memory cell; A method of programming a nonvolatile memory device which supplies a channel voltage of a string by applying a positive voltage to a source line. The method of claim 1, Sequentially programming the memory cell adjacent to the drain transistor from the N + 1 th memory cell Precharging a bit line connected to the drain select transistor;  Turning on the drain select transistor; And And applying a program voltage to a selected memory cell of the plurality of memory cells, and applying a pass voltage to a non-selected memory cell. The method of claim 1, And randomly selecting the N-th memory cell prior to programming the N-th memory cell. A method of programming a nonvolatile memory device having a string structure in which a source select transistor, a plurality of memory cells, and a drain transistor are connected in series between a source line and a bit line, A first step of sequentially programming a memory cell adjacent to the source select transistor from an Nth memory cell of the plurality of memory cells; And A second step of sequentially programming a memory cell adjacent to the drain transistor from an N + 1 th memory cell; The program operation of the first step precharges the channel of the string structure through the source line, and the program operation of the second stage precharges the channel of the string structure through the bit line. . The method of claim 7, wherein The program operation of the first step is And turning off the M + 1 th memory cell and the M + 2 th memory cell during a program operation of the selected M th memory cell. The method of claim 8, And applying a 3 V word line voltage to the word lines of the M + 1 th memory cells and applying a 0 V word line voltage to the M + 2 th memory cells.

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