KR20110029922A - Organic electroluminescent display device - Google Patents

Abstract

PURPOSE: An organic electroluminescent display device is provided to relieve the delay deviation of a gate signal by forming a deviation control load in front of a gate link wiring. CONSTITUTION: In an organic electroluminescent display device, a first gate link wiring(122) is connected to one end of fist to m gate line(GL1-GLm) respectively. A first deviation control load(134) is connected between a gate signal generator and a first gate link wire. The fist deviation control load controls the delay deviation of gate lines. The first deviation control load is one of a resistor, capacitor, and a rise time control circuit. A gate signal generator(132) supplies a gate signal to the first gate link wire.

Description

Organic Electroluminescent Display Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display device, and more particularly, to an organic light emitting display device including a deviation control load for uniformizing signal delay variations between gate lines.

One of the new flat panel displays, the organic electroluminescent display device (OLED device) is a self-luminous type, so it has better viewing angle and contrast ratio than liquid crystal display device and does not require backlight. Light weight and thinness are possible, and it is advantageous in terms of power consumption. In addition, since it is possible to drive DC low voltage, fast response speed, and all solid, it is strong against external shock, wide use temperature range, and especially in terms of manufacturing cost. Such an organic light emitting display device is also referred to as an organic light emitting diode device (OLED device).

The organic light emitting display device is a deposition and encapsulation equipment because the process is very simple, unlike a liquid crystal display device or a plasma display panel device (PDP device).

In particular, in an active matrix type, a voltage controlling a current applied to a pixel is charged in a storage capacitor, and the gate is maintained by maintaining the voltage until the next frame signal is applied. It is driven to maintain the light emission state while one screen is displayed regardless of the number of wirings.

Therefore, in the active matrix system, since the same luminance is displayed even when a low current is applied, low power consumption, high definition, and large size can be obtained.

Hereinafter, the basic structure and operation characteristics of the active matrix organic light emitting display device will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram illustrating a conventional active matrix type organic light emitting display device.

As shown in FIG. 1, the conventional active matrix type organic light emitting display device 10 supplies a plurality of signals and power to the organic light emitting panel 20 and the organic light emitting panel 20 for displaying an image. It includes a drive unit 30 to.

The organic light emitting panel 20 includes first to mth gate lines GL1 to GLm, first to nth data lines DL1 to DLn, and first to nth intersecting each other to define the pixel region P. Referring to FIG. Power wirings PL1 to PLn are formed, and in each pixel area P, a first transistor T1, a second transistor T2, a storage capacitor Cst, and a light emitting diode Del are formed.

The gate electrode and the source electrode of the first transistor T1 are connected to the gate lines GL1 to GLm and the data lines DL1 to DLn, respectively, and the drain electrode of the first transistor T1 is connected to the second transistor T2. It is connected to the gate electrode.

The source electrode of the second transistor T2 is connected to the power wirings PL1 to PLn, and the storage capacitor Cst is connected between the gate electrode of the second transistor T2 and the power wirings PL1 to PLn.

The light emitting diode Del is connected to the drain electrode of the second transistor T2.

The first transistor T1 serves as a switching element for supplying a data signal supplied through the data lines DL1 to DLn to the second transistor T2 according to the gate signal supplied through the gate lines GL1 to GLm. The second transistor T2 serves as a driving device for supplying a power supply voltage supplied through the power wirings PL1 to PLn to the light emitting diode Del in accordance with a data signal applied to the gate electrode.

Accordingly, different gray scales are possible by supplying different power supply voltages depending on the data signal to the light emitting diode Del.

In addition, the organic light emitting panel 20 is formed with a gate link wiring 22 connected to one end of each of the first to m th gate lines GL1 to GLm to transfer a gate signal supplied from the driver 30.

The driver 30 generates a gate signal and a data signal and supplies the gate signal and the data signal to the organic light emitting panel 20 together with the power supply voltage, and is configured in the form of a printed circuit board (PCB) equipped with a plurality of electrical elements. Can be.

In particular, the driver 30 may include a gate signal generator 32 that generates a gate signal in the form of an integrated circuit (IC).

That is, the gate signal generator 32 of the driver 30 is connected to the gate link wiring 22 of the organic light emitting panel 20 to supply the gate signal to the first to mth gate wirings GL1 to GLm. .

Here, although the gate link wiring 22 of the organic light emitting panel 20 is formed of a conductive material, the conductive material does not actually have a specific resistance of 0, and therefore, there is a resistance proportional to the length of the gate link wiring 22. do.

Further, in the pixel area P of the organic light emitting panel 20, the intersection of the gate lines GL1 to GLm and the data lines DL1 to DLn, the gate lines GL1 to GLm, and the power lines PL1 to PLn. There are a plurality of parasitic capacitors, such as an intersection portion of the first thin film transistor and an overlapping portion of the gate electrode and the source electrode of the first thin film transistor.

Accordingly, the gate signal transmitted to the gate link wiring 22 of the organic light emitting panel 20 is controlled by the parasitic capacitance of the pixel region P connected to the gate link wiring 22 and the resistance of the gate link wiring 22. There is a delay, which will be described with reference to the drawings.

2 is a schematic equivalent circuit diagram of a conventional active matrix type organic light emitting display device. In FIG. 2, the resistances according to the lengths of the gate lines are not shown for convenience.

As shown in FIG. 2, the gate link wirings 22 connected to the first to mth gate wirings GL1 to GLm have a gate link resistance Rgl proportional to the length between adjacent gate wirings as an equivalent resistance. In addition, the parasitic capacitance Cp existing in each pixel region P can be interpreted as being connected to the gate link wiring 22 in parallel. (Here, Rgl denotes a resistance and a resistance value at the same time, and Cp denotes a capacitor and a capacitance at the same time.)

Accordingly, the gate signal transmitted to the gate link wiring 22 is delayed depending on a time constant expressed as a product of a resistor and a capacitor, and the gate link wiring to the first to mth gate wirings GL1 to GLm is delayed. Since the length of 22 and the resistance thereof are different, the gate signals supplied to the first to m th gate lines GL1 to GLm are delayed differently.

For example, the gate signal supplied to the first gate line GL1 is delayed depending on the n times product Rgl * nCp of the gate link resistance Rgl and the parasitic capacitance, and is delayed to the mth gate line GLm. The supplied gate signal is delayed depending on the product of m times the gay link resistance Rgl and n times the parasitic capacitance (mRgl * nCp).

That is, the delay of the gate signal increases from the first gate line GL1 to which the gate signal is first supplied to the mth gate line GLm to which the gate signal is last supplied.

Delay variation of the gate signal in the first to mth gate lines GL1 to GLm causes light leakage defects in the image display of the organic light emitting display device 10, which will be described with reference to the accompanying drawings.

3A and 3B are diagrams illustrating gate signals and data voltages of first and m-th gate lines of a conventional active matrix type organic light emitting display device, respectively, with reference to FIGS. 1 and 2.

As shown in Figs. 3A and 3B, the gate signal is a pulse in which the gate low voltage Vgl and the gate high voltage Vgh are the lowest and highest voltages, respectively, repeated every one frame time Tf. It is in the form of a rectangular wave.

As shown in FIG. 3A, the pulse of the first gate signal GS1 supplied to the first gate line GL1 is changed from the gate low voltage Vgl to the gate high voltage Vgh during the first rising time Trising1. It increases and maintains the gate high voltage Vgh for the first pulse duration Tpd1 and then decreases to the gate low voltage Vgl.

At this time, the first rise time Trising1 is 0 seconds in an ideal state in which no resistance or capacity exists, but in reality, a time constant by one gate link resistor Rgl and n parasitic capacitances Cp is used. This is a time that depends on (Rgl * nCp).

When the first gate signal GS1 becomes the gate high voltage Vgh, the first transistor T1 connected to the first gate line GL1 is turned on and the data lines DL1 to DLn. The data signal supplied through the first transistor T1 passes through the first transistor T1 and is charged to the gate electrode of the second transistor T2 with the first data voltage Vdata1.

In this case, the storage capacitor Cst connected to the first transistor T1 is also charged with the first data voltage Vdata1.

When the first gate signal GS1 becomes the gate low voltage Vgl, since the first transistor T1 is turned off, the data signal does not pass through the first transistor T1. As described above, the gate electrode of the second transistor T2 cannot be charged, but instead, the charge that is charged in the storage capacitor Cst charges the gate electrode of the second transistor T2, and thus the gate electrode of the second transistor T2. Maintains the first data voltage Vdata1 for the first data time Tdata1 until the next frame.

Here, the first rise time Trising1 may vary depending on the size of the organic light emitting display device 10, the number of pixels, the material of the wiring, the line width, and the thickness, similarly to the gate link resistance Rgl and the parasitic capacitance Cp. For example, the first rise time Trising1 may be about 20 nsec.

Meanwhile, as shown in FIG. 3B, the pulse of the m-th gate signal GSm supplied to the m-th gate line GLm is controlled from the gate-low voltage Vgl to the gate-high voltage Vgh during the m-th rising time Trism. The gate high voltage Vgh is maintained for the mth pulse duration Tpdm, and then decreases to the gate low voltage Vgl.

At this time, the mth rise time Trisingm is a time generated depending on the time constant mRgl * nCp by m gate link resistors Rgl and n parasitic capacitances Cp, and the first rise time Trising1. It is longer (Trisingm> Trising1), and thus, the mth pulse duration Tpdm, which is the remaining time of one pulse of the gate signal, is shorter than the first pulse duration Tpd1 (Tpdm <Tpd1).

When the m th gate signal GSm becomes the gate high voltage Vgh, the first transistor T1 connected to the m th gate line GLm is turned on and the data lines DL1 to DLn. The data signal supplied through the first transistor T1 is charged to the gate electrode and the storage capacitor Cst of the second transistor T2 with the mth data voltage Vdatam.

When the m th gate signal GSm becomes the gate low voltage Vgl, since the first transistor T1 is turned off, the data signal cannot pass through the first transistor T1. As described above, the gate electrode of the second transistor T2 cannot be charged, but instead, the charge that is charged in the storage capacitor Cst charges the gate electrode of the second transistor T2, and thus the gate electrode of the second transistor T2. Maintains the mth data voltage Vdatam for the mth data time Tdatam until the next frame.

That is, the first data voltage Vdata1 is applied to the gate electrode of the second transistor T2 connected to the first gate wiring GS1 of the portion where the gate signal is first transmitted, so that the light emitting diode ( The m-th data voltage Vdatam is applied to the gate electrode of the second transistor T2 connected to the m-th gate wiring GSm, which drives Del, and is connected to the last gate signal. It is applied to drive the light emitting diode Del.

However, since the first data time Tdata1 is longer than the m-th data time Tdatam due to the difference in the rise times of the gate signals in the first and m-th gate wirings GS1 and GSm (Tdata1 <Tdatam), The light emitting diode Del connected to the one gate wiring GS1 is driven to emit light longer than the light emitting diode Del connected to the m-th gate wiring GSm.

As a result, the luminance of the pixel region P connected to the first gate wiring GS1 may be greater than the luminance of the pixel region P connected to the m-th gate wiring GSm, and the luminance difference may cause light leakage defects. .

As described above, in the organic light emitting display device 10 according to the related art, the gate link resistance Rgl of the gate link wiring 22 between the adjacent gate wirings and the parasitic capacitance Cp existing in each pixel region P exist. As a result, a delay of the gate signal occurs, and the delay of the gate signal is varied in the portion where the gate signal is first transmitted and the gate signal is finally transmitted in the organic light emitting panel 20. For example, The delay of the gate signal increases from the first gate line GL1 through which the signal is first transmitted to the mth gate line GLm through which the gate signal is last transmitted.

Although not shown in the drawings, since the gate wiring also has an equivalent resistance and there is a difference in the equivalent resistance due to the difference in the length of the gate wiring between the portion where the gate signal is first input and the portion which is finally input, the first to mth gate wiring In the gate wiring of any one of (GL1 to GLm), the delay of the gate signal increases from one end to the other end connected to the gate link wiring 22, which is a portion where the gate signal is first input.

The deviation of the gate signal delay appears as a defect when the organic light emitting display device 10 displays an image. Particularly, when a low gray level image is displayed, a portion of the gate signal delay has a higher luminance than the surroundings. Appears.

For example, when the organic light emitting display device 10 displays low gray scales such as 7, 15, 23, 31, and 39 of 256 gray scales, the upper end of the organic light emitting panel 20 to which a gate signal is first transmitted is displayed. The portion A (FIG. 2) may exhibit higher luminance than the surroundings.

Although not shown in the drawings, gate signals are supplied from both ends of the driving unit 30, and the respective gate wirings GL1 to GLm are formed through first and second gate link wirings formed at both ends of the organic light emitting panel 20, respectively. When the gate signal is transmitted to both ends of the), the light leakage may occur at both ends of the upper portion of the organic light emitting panel 20 to which the gate signal input from the driver 30 is first transmitted.

The light leakage phenomenon causes deterioration of the image displayed by the organic light emitting display, and deteriorates the contrast ratio by increasing the brightness of the black image. As a result, the image quality of the organic light emitting display is degraded.

The present invention is to solve the above problems, in the organic light emitting display device, by forming a deviation control load in front of the gate link wiring, the gate signal delay deviation is alleviated to remove the light leakage phenomenon and the organic light emitting display It aims to improve the visibility, contrast ratio and picture quality of the device.

In order to achieve the above object, the present invention, a substrate; First to mth gate wirings, first to nth data wirings, and first to nth power wirings formed on the substrate to cross each other to define a pixel area; A first transistor, a second transistor, a storage capacitor, and a light emitting diode formed in the pixel region; A first gate link wire connected to one end of each of the first to m-th gate wires; A gate signal generator supplying a gate signal to the first gate link wiring; An organic light emitting display device connected between the gate signal generation unit and the first gate link line and including a first deviation control load configured to adjust a delay variation of the gate signal in the first to mth gate lines; to provide.

A portion of the first gate link line corresponding to an adjacent two of the first to m-th gate lines has a gate link resistance, the pixel area includes a parasitic capacitance, the first deviation regulating load, and the gate link. The rising time of the gate signal due to the resistance and the parasitic capacitance may be a value ranging from 20 times to 60 times the rise time of the gate signal due to the gate link resistance and the parasitic capacitance.

The first deviation regulating load may include one of a resistor, a capacitor, and a rise time regulating circuit.

Here, when the first deviation control load is a control resistor, the control resistor may be a value in the range of 100 times to 300 times the gate link resistance.

The organic light emitting display device may further include a second gate link wiring connected to the other end of each of the first to m-th gate wirings, and in this case, the first deviation adjusting unit may include the gate generator and the second gate wiring. It may be connected between the gate link wiring.

The organic light emitting display device may further include a second gate link line connected to the other end of each of the first to mth gate lines, and a second deviation control load connected between the gate generator and the second gate link line. It may further include.

The gate signal generator and the first deviation controller may be formed on a printed circuit board connected to the substrate, wherein the first transistor is one of the first to nth gate wirings and the first to nth gate wirings. The second transistor and the storage capacitor may be connected between the first transistor and one of the first to nth power wires, and the light emitting diode may be connected to the second transistor. have.

As described above, in the organic light emitting display device according to the present invention, by forming a deviation control load at the front end of the gate link wiring, the gate signal delay deviation can be alleviated to prevent light leakage and improve the luminance uniformity in the panel. .

In addition, by reducing the luminance of the black image of the organic light emitting display, the visibility and the image quality of the organic light emitting display may be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

4 is a schematic diagram illustrating an active matrix organic light emitting display device according to an embodiment of the present invention.

As shown in FIG. 4, the active matrix type organic light emitting display device 110 according to an embodiment of the present invention includes a plurality of organic light emitting panel 120 and an organic light emitting panel 120 displaying an image. It includes a driver 130 for supplying a signal and power.

The organic light emitting panel 120 has first to mth gate lines GL1 to GLm, first to nth data lines DL1 to DLn, and first to nth intersecting each other to define the pixel region P. Referring to FIG. Power wirings PL1 to PLn are formed, and in each pixel area P, a first transistor T1, a second transistor T2, a storage capacitor Cst, and a light emitting diode Del are formed.

Although not illustrated, the organic light emitting panel 120 may form a gate wiring, a data wiring, a transistor, a storage capacitor, and a light emitting diode on the first substrate through deposition, photolithography, and the like, and may form an element of the first substrate. The second substrate may be formed by bonding the second substrate to cover the substrate, and the gate wiring, the data wiring, the transistor, and the storage capacitor may be formed on the first substrate through deposition and photolithography, and the light emitting diode may be formed on the second substrate. Afterwards, the first and second substrates may be bonded to each other so that the elements of each substrate face each other.

The gate electrode and the source electrode of the first transistor T1 are connected to the gate lines GL1 to GLm and the data lines DL1 to DLn, respectively, and the drain electrode of the first transistor T1 is connected to the second transistor T2. It is connected to the gate electrode.

The source electrode of the second transistor T2 is connected to the power wirings PL1 to PLn, and the storage capacitor Cst is connected between the gate electrode of the second transistor T2 and the power wirings PL1 to PLn.

The light emitting diode Del is connected to the drain electrode of the second transistor T2.

The first transistor T1 serves as a switching element for supplying a data signal supplied through the data lines DL1 to DLn to the second transistor T2 according to the gate signal supplied through the gate lines GL1 to GLm. The second transistor T2 serves as a driving device for supplying a power supply voltage supplied through the power wirings PL1 to PLn to the light emitting diode Del in accordance with a data signal applied to the gate electrode.

Accordingly, different gray scales are possible by supplying different power supply voltages depending on the data signal to the light emitting diode Del.

In FIG. 4, two transistors T1 and T2 are formed in one pixel region P, but in another embodiment, three or more transistors may be formed in one pixel region.

In addition, the organic light emitting panel 120 is formed with a gate link wiring 122 connected to one end of each of the first to m-th gate lines GL1 to GLm to transfer a gate signal supplied from the driver 130.

In FIG. 4, one gate link wiring 122 is formed at one end of the organic light emitting panel 120, but in another embodiment, one gate link wiring is formed at both ends of the organic light emitting panel 120. In this case, the gate link wirings are connected to both ends of the gate wirings GL1 to GLm, respectively, to supply a gate signal.

The driver 130 generates a gate signal and a data signal and supplies the gate signal and the data signal to the organic light emitting panel 120 together with a power supply voltage. The driver 130 may be configured in the form of a printed circuit board (PCB) equipped with a plurality of electrical elements. Can be.

In particular, the driving unit 130 is a deviation control load connected between the gate signal generator 132 for generating a gate signal, the gate signal generator 132 and the gate link wiring 122 of the organic light emitting panel 120. (deviation-adjusting load: 134), wherein the deviation adjusting load 134 adjusts the delay variation of the gate signal in the first to mth gate lines GL1 to GLm due to the equivalent resistance of the gate link wiring. Play a role.

The gate signal generator 132 may be formed in the form of an integrated circuit (IC), and the deviation regulating load 134 may include a resistor, a capacitor, and a rising time control circuit. ) May be one of

Accordingly, the gate signal generator 132 of the driver 130 is connected to the gate link wiring 122 of the organic light emitting panel 120 through the deviation control load 134 and the gate signal generator of the driver 130. The gate signal generated at 132 is supplied to the first to m th gate lines GL1 to GLm of the organic light emitting panel 120 through the deviation control load 134 and the gate link wiring 22.

Here, a resistance proportional to the length is present in the gate link wiring 122, and an intersection portion of the gate wiring GL1 to GLm and the data wiring DL1 to DLn is disposed in the pixel area P of the organic light emitting panel 120. And parasitic capacitors such as an intersection of the gate lines GL1 to GLm and the power lines PL1 to PLn, and an overlapping portion of the gate electrode and the source electrode of the first thin film transistor T1. The gate signal transmitted to the gate link wiring 122 of the light emitting panel 120 is delayed by the resistance of the gate link wiring 122 and the parasitic capacitance of the pixel region P connected to the gate link wiring 122. In particular, although the delay of the gate signal varies depending on the positions of the gate lines GL1 to GLm, that is, the length of the gate link wiring 122, the deviation is controlled by the deviation adjusting load 134 of the driver 130. Is relaxed.

5 is a schematic equivalent circuit diagram of an active matrix type organic light emitting display device according to an exemplary embodiment of the present invention. In FIG. 5, the deviation control load 134 of the driver 130 is a resistor for convenience, and the equivalent resistance according to the length of each gate wiring is not shown.

As shown in FIG. 5, the gate link wiring 122 connected to the first to m th gate wirings GL1 to GLm uses a gate link resistance Rgl proportional to the length between adjacent gate wirings as an equivalent resistance. In addition, the parasitic capacitance Cp existing in each pixel region P can be interpreted as being connected to the gate link wiring 22 in parallel. (Here, Rgl denotes a resistance and a resistance value at the same time, and Cp denotes a capacitor and a capacitance at the same time.)

The gate link resistance Rgl and the parasitic capacitance Cp may vary depending on the size of the organic light emitting display device 110, the number of pixels, the material of the wiring, the line width and the thickness, and the like, for example, the gate link resistance Rgl. And the parasitic capacitance Cp may be about 1 W and about 0.2 pF, respectively.

In addition, the deviation control load 134 of the driving unit 130 has a control resistor (Rc), the control resistor (Rc) is a gate link resistance (Rgl) in the range that can prevent the light leakage failure without the last change of the overall brightness ), And may be determined in consideration of the parasitic capacitance Cp and the rising time of the pulse of the gate signal, and may be in a range of about 100 times to about 300 times the gate link resistance Rgl (100 Rgl <Rc <300 Rgl), For example, the value may be in the range of about 100W to about 300W.

Accordingly, the gate signal transmitted to the gate link wiring 122 is delayed depending on a time constant expressed as a product of a resistor and a capacitor, and the gate link wiring to the first to m-th gate wiring GL1 to GLm is delayed. Since the length of 122 and the resistance thereof are different, the gate signals supplied to the first to mth gate lines GL1 to GLm are delayed differently.

For example, the gate signal supplied to the first gate wiring GL1 depends on the sum of the regulating resistor Rc and the gate link resistor Rgl and the product of n times the parasitic capacitance (Rc + Rgl * nCp). Delayed, and the gate signal supplied to the m-th gate wiring GLm is a sum of m times the control resistor Rc and the gay link resistance Rgl and n times the parasitic capacitance ((Rc + mRgl) * nCp Depending on the delay.

That is, "the gate signal supplied to the m-th gate wiring GLm is the sum of m times the control resistor Rc and the gay link resistance Rgl and n times the parasitic capacitance. Since the sum of the gate link resistance (Rgl) and n times the parasitic capacitance is greater than ((Rc + mRgl) * nCp> (Rc + Rgl) * nCp), the first gate wiring to which the gate signal is first supplied ( The delay of the gate signal increases from GL1 to the m-th gate wiring GLm to which the gate signal is last supplied, resulting in a deviation of the gate signal delay.

However, in the organic light emitting display device 110 according to the exemplary embodiment of the present invention, since the value of the adjusting resistor Rc is much larger than the value of the gate link resistance Rgl (Rc >> Rgl), such a gate link wiring is performed. The equivalent resistance difference (Rgl vs mRgl) according to the length difference of (122) does not appear as a large difference in the overall equivalent resistance causing the gate signal delay ((Rc + Rgl) to (Rc + mRgl)), and as a result Delay deviation of the gate signal through the gate link wiring 122 is also alleviated and minimized.

The relaxation of the delay deviation of the gate signal in the first to mth gate lines GL1 to GLm will be described with reference to the drawings.

6A and 6B are diagrams illustrating gate signals and data voltages of first and m-th gate wirings of an active matrix type organic light emitting display device according to an exemplary embodiment of the present invention, respectively. It demonstrates with reference.

As shown in Figs. 6A and 6B, the gate signal is a pulse of which the gate low voltage (Vgl) and the gate high voltage (Vgh) are the minimum and maximum voltages, respectively, repeated every one frame time (Tf). It is in the form of a rectangular wave.

As shown in FIG. 6A, the pulse of the first gate signal GS1 supplied to the first gate wiring GL1 is controlled from the gate low voltage Vgl to the gate high voltage Vgh during the first rising time Trising1. The gate high voltage Vgh is maintained for the first pulse duration Tpd1 and then decreases to the gate low voltage Vgl.

At this time, the first rise time Trising1 is 0 sec in an ideal state in which there is no resistance or capacity, but in reality, the sum of the regulating resistor Rc and one gate link resistor Rgl and n parasitics It is a time that occurs depending on the time constant ((Rc + Rgl) * nCp) by the capacity Cp.

When the first gate signal GS1 becomes the gate high voltage Vgh, the first transistor T1 connected to the first gate line GL1 is turned on and the data lines DL1 to DLn. The data signal supplied through the first transistor T1 passes through the first transistor T1 and is charged to the gate electrode of the second transistor T2 with the first data voltage Vdata1.

In this case, the storage capacitor Cst connected to the first transistor T1 is also charged with the first data voltage Vdata1.

When the first gate signal GS1 becomes the gate low voltage Vgl, since the first transistor T1 is turned off, the data signal does not pass through the first transistor T1. As described above, the gate electrode of the second transistor T2 cannot be charged, but instead, the charge that is charged in the storage capacitor Cst charges the gate electrode of the second transistor T2, and thus the gate electrode of the second transistor T2. Maintains the first data voltage Vdata1 for the first data time Tdata1 until the next frame.

Here, the first rise time Trising1 may vary according to the size of the organic light emitting display device 110, the number of pixels, the material of the wiring, the line width, the thickness, and the like, as in the gate link resistance Rgl and the parasitic capacitance Cp. In particular, it may vary depending on the value of the adjusting resistor Rc of the deviation adjusting load 134 of the driving unit 130.

That is, the first rise time Trising1 is the first rise time of the case where the deviation regulating load 134 is not present (depending only on the gate link resistance Rgl and n parasitic capacitances Cp) (see FIG. 3A). Trising1) can range from about 20 times to about 60 times, and can be about 400 nsec.

On the other hand, as shown in FIG. 6B, the pulse of the m-th gate signal GSm supplied to the m-th gate line GLm is controlled from the gate-low voltage Vgl to the gate-high voltage during the m-th rising time Trism. Vgh) and maintains the gate high voltage Vgh for the mth pulse duration Tpdm, and then decreases to the gate low voltage Vgl.

At this time, the m-th rise time Trisingm depends on the sum of the regulating resistor Rc and the m gate link resistors Rgl and the time constant ((Rc + mRgl) * nCp) by n parasitic capacitances Cp. Time, which is strictly longer than the first rise time (Trising1).

However, in the organic light emitting display device 110 according to the embodiment of the present invention, since the value of the control resistor Rc is much larger than the value of the gate link resistance Rgl (Rc >> Rgl), the m-th rise time The time constant ((Rc + mRgl) * nCp) to determine (Trisingm) and the time constant ((Rc + Rgl) * nCp) to determine the first rise time (Trising1) are the control resistance (Rc) and n parasitic capacitances. Almost equal to the product of (Cp) (Rc * nCp), the difference between the two time constants is minimized (((Rc + mRgl) * nCp ~ Rc + Rgl) * nCp ~ Rc + mRgl) * nCp) The difference between the first rising time Trising1 and the mth rising time Trising, that is, the delay deviation of the gate signal is alleviated and minimized (Trisingm to Trising1).

The mth pulse duration Tpdm, which is the remaining time of one pulse of the gate signal, is also substantially the same value as the first pulse duration Tpd1 (Tpdm to Tpd1).

When the m th gate signal GSm becomes the gate high voltage Vgh, the first transistor T1 connected to the m th gate line GLm is turned on and the data lines DL1 to DLn. The data signal supplied through the first transistor T1 is charged to the gate electrode and the storage capacitor Cst of the second transistor T2 with the mth data voltage Vdatam.

When the m th gate signal GSm becomes the gate low voltage Vgl, since the first transistor T1 is turned off, the data signal cannot pass through the first transistor T1. As described above, the gate electrode of the second transistor T2 cannot be charged, but instead, the charge that is charged in the storage capacitor Cst charges the gate electrode of the second transistor T2, and thus the gate electrode of the second transistor T2. Maintains the mth data voltage Vdatam for the mth data time Tdatam until the next frame.

Here, since the m-th rising time Trisingm has almost the same value as the first rising time Trising1 (Trisingm to Trising1), the m-data time Tdatam, which is the remaining time of one frame time Tf, is also the first. It will have almost the same value as the data time Tdata1.

That is, in the organic light emitting display device 110 according to an exemplary embodiment of the present invention, a first data time is applied to the gate electrode of the second transistor T2 connected to the first gate line GS1 of the portion where the gate signal is first transmitted. The first data voltage Vdata1 is applied during the Tdata1 to drive the light emitting diode Del, and the gate of the second transistor T2 connected to the mth gate line GSm, which is a portion where the gate signal is finally transmitted. The m-th data voltage Vdatam is applied to the electrode during the m-th data time Tdatam to drive the light emitting diode Del. The first data time Tdata1 and the m-th data time Tdatam have substantially the same value. (Tdata1 to Tdatam), the light emitting diode Del connected to the first gate wiring GS1 and the light emitting diode Del connected to the mth gate wiring GSm are driven to emit light for substantially the same time.

As a result, in displaying gray scales, the pixel area P connected to the first gate line GS1 to which the gate signal is first transmitted and the pixel area connected to the m-th gate line GSm to which the gate signal is lastly transmitted are displayed. The luminance of (P) becomes substantially the same, and light leakage defects can be prevented.

Such light leakage failure prevention of the present invention will be described with reference to the measurement results.

7 is a graph illustrating luminance measurement of one upper end of an organic light emitting display device according to an exemplary embodiment of the present invention.

In FIG. 7, the luminance of the upper end of the organic electroluminescent panel of the organic light emitting display device, which is a portion where the gate signal is first transmitted, is measured according to the gray scale and the adjusting resistor Rc.

As shown in Fig. 7, as the control resistor Rc is increased from 0 W (i.e., in the case of the conventional organic electroluminescent device not including the deviation control load) to 200 W, all the low gradations (7, 15, 23) , 31 and 39, the luminance of the upper end is reduced, which indicates the prevention of light leakage failure at the upper end of the organic light emitting panel 120.

When the control resistor Rc is 300 W, the luminance of the entire organic light emitting panel 120 increases more than the desired gray scale due to excessive delay of the gate signal. As a result, the brightness of the upper end of the control resistor Rc is 200 W. Rather than increases, but light leakage does not appear.

Therefore, the deviation control load 134 may be determined in a range that minimizes fluctuations in the overall luminance of the organic light emitting panel 120 while preventing light leakage.

As described above, for example, the first rise time of the case where the deviation regulating load 134 is formed (depending on the regulating resistor Rc, the gate link resistance Rgl and n parasitic capacitances Cp) (Trising1) is about 20 times the first rise time (Trising1 in FIG. 3A) when the deviation control load 134 is not present (depending only on the gate link resistance Rgl and n parasitic capacitances Cp). The value of the deviation control load 134 (resistance value in case of resistance, capacitance in case of capacitor, circuit parameter in case of rise time control circuit) may be determined so as to be in a range of about 60 times.

Specifically, in the case where the deviation regulating load 134 is constituted by the regulating resistor Rc, the regulating resistor Rc is a gate link resistor (the equivalent resistance of the gate link wiring 122 between the adjacent gate wirings GL1 to GLm). Rgl) may range from about 100 to about 300 times.

As described above, in the organic light emitting display device 110 according to the exemplary embodiment of the present invention, the gate link wiring 122 is formed by forming the deviation control load 134 connected to the gate link wiring 122 in the driver 130. The delay deviation of the gate signal due to the gate link resistance Rgl and the parasitic capacitance Cp of each pixel region P can be alleviated and minimized.

Although not shown, gate signals are supplied from both ends of the driving unit 130, and the gate signals GL1 to GLm are connected through first and second gate link wirings formed at both ends of the organic light emitting panel 120, respectively. Even in the organic light emitting display device according to another embodiment of the present invention, the gate signal is input to both ends, the deviation control load 134 of the driver 130 is connected to both the first and second gate link wirings, or the driver By forming the first and second deviation control loads connected to the first and second gate link wirings at the 130, the light leakage of the upper ends of the organic light emitting panel can be prevented.

In addition, although the organic light emitting display device is taken as an example in FIGS. 4 to 6, the present invention may be applied to a liquid crystal display device in another embodiment.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

1 is a schematic view showing a conventional active matrix type organic light emitting display device.

2 is a schematic equivalent circuit diagram of a conventional active matrix type organic light emitting display device.

3A and 3B show gate signals and data voltages on first and m-th gate lines of a conventional active matrix type organic light emitting display device, respectively.

4 is a schematic diagram illustrating an active matrix organic light emitting display device according to an embodiment of the present invention.

5 is a schematic equivalent circuit diagram of an active matrix organic light emitting display device according to an embodiment of the present invention.

6A and 6B illustrate gate signals and data voltages in first and m-th gate wirings of an active matrix type organic light emitting display device according to an exemplary embodiment of the present invention, respectively.

7 is a graph of luminance measurement of one upper end of an organic light emitting display device according to an exemplary embodiment of the present invention.

Claims (8)

A substrate; First to mth gate wirings, first to nth data wirings, and first to nth power wirings formed on the substrate to cross each other to define a pixel area; A first transistor, a second transistor, a storage capacitor, and a light emitting diode formed in the pixel region; A first gate link wire connected to one end of each of the first to m-th gate wires; A gate signal generator supplying a gate signal to the first gate link wiring; A first deviation control load connected between the gate signal generation unit and the first gate link wiring to adjust a delay variation of the gate signal in the first to m-th gate wiring; An organic light emitting display device comprising a. The method of claim 1, A portion of the first gate link line corresponding to an adjacent two of the first to m-th gate lines has a gate link resistance, the pixel area includes a parasitic capacitance, the first deviation regulating load, and the gate link. And a rise time of the gate signal due to the resistance and the parasitic capacitance is in a range of 20 to 60 times the rise time of the gate signal due to the gate link resistance and the parasitic capacitance. The method of claim 2, The first deviation control load is one of a resistor, a capacitor and a rise time control circuit. The method of claim 3, wherein And when the first deviation control load is a control resistor, the control resistor is in a range of 100 times to 300 times the gate link resistance. The method of claim 1, The organic light emitting display may further include a second gate link line connected to the other end of each of the first to mth gate lines, and the first deviation controller may be connected between the gate generation unit and the second gate link line. Device. The method of claim 1, The organic light emitting display device further includes a second gate link line connected to the other end of each of the first to mth gate lines, and a second deviation control load connected between the gate generator and the second gate link line. . The method of claim 1, And the gate signal generator and the first deviation controller are formed on a printed circuit board connected to the substrate. The method of claim 1, The first transistor is connected to one of the first to nth gate wires and one of the first to nth data wires, and the second transistor and the storage capacitor are connected to the first transistor and the first to nth wires. An organic light emitting display device connected between one of power lines and the light emitting diode connected to the second transistor.

Images