KR20110029212A - Pulse peak detecting and holding circuit - Google Patents

Abstract

PURPOSE: A pulse peak detecting and maintaining circuit is provided to maintain a peak value of a detected pulse signal for a long time by compensating an error of a capacitor for detecting a pulse peak and a capacitor for maintaining the pulse peak. CONSTITUTION: A pulse peak detecting unit(510) comprises a capacitive device for detecting a pulse peak to detect the peak of an applied pulse signal. A pulse peak maintaining unit(520) comprises a capacitive device for maintaining the pulse peak to maintain the size of the pulse peak detected by the pulse peak detecting unit. The capacitance of the capacitive device for maintaining the pulse peak is larger than the capacitance of the capacitive device for detecting the pulse peak. The pulse peak detecting unit includes a voltage division circuit unit(511), a differential amplifier(512), the capacitive device for detecting the pulse peak, a uni-directional semiconductor device, and a resistor for limiting a charging current.

Description

Pulse peak detection and holding circuit {PULSE PEAK DETECTING AND HOLDING CIRCUIT}

TECHNICAL FIELD The present invention relates to a pulse peak detection and retention circuit, and more particularly, to a circuit for detecting and holding a peak value having a pulse width in extremely narrow nanoseconds.

The low-temperature plasma power supply device applied to the desulfurization and denitrification treatment system for exhaust gas treatment compresses and outputs high-voltage pulses of microseconds to nanoseconds by self-compression, and when a high-voltage of nano-pulse is applied between the discharge rod and the collecting electrode of the plasma reactor, Plasma discharge occurs. At this time, the peak of the output pulse is detected by the nano-pulse detection circuit and the detected signal is used for power control and measurement of the output current of the low-temperature plasma power supply.

Conventional pulse peak detection circuits generally employ one or more comparators and one capacitor. Therefore, there is a problem in that the peak value of the pulse stored in the capacitor is discharged easily and the time to hold after detecting the peak value of the pulse is short.

1 is a pulse peak detection circuit according to the prior art, and is composed of a comparator, a capacitor, and a diode.

The difference between the pulse applied to the comparator 11 and the feedback input of the peak detecting capacitor 13 is charged through the diode 12 to the peak detecting capacitor 13 and the peak detecting capacitor 13 is discharged. The pulse peak is detected using the interval maintained until.

Specifically, a pulse signal is input to the non-inverting terminal (+) of the comparator 11, a signal fed back from the feedback resistor 14 is input to the inverting terminal (-), and the diode 12 is connected in series to the output terminal. do. Since the diode 13 is connected in series from the output terminal of the comparator 12, the output current is conducted in one direction to charge the peak detection capacitor 13, and the peak detection capacitor 13 stores the peak value of the pulse. . The peak detecting capacitor 13 has a small capacitance of several pF, and the capacitor charges according to the magnitude of the pulse peak and naturally discharges according to the amount of energy stored in the capacitance of the capacitor. The signal fed back from the peak detecting capacitor 13 is applied to the inverting terminal (-) of the comparator 11 via the feedback resistor 14.

However, the pulse peak detection circuit according to the related art of FIG. 1 uses a charging phenomenon of a capacitor for a continuous pulse waveform. The pulse peak detection circuit is simple to implement and can detect pulse peaks, but the pulse width is short as nanoseconds. Hz), the pulse waveform has a disadvantage in that the pulse peak is not maintained by the discharge of the peak detection capacitor.

2 is a pulse peak input signal and output waveform diagram varying during a continuous period in a peak detection circuit according to the prior art.

The pulse peak waveform 22 is shown in which the magnitude of the pulse peak is maintained to the pulse waveform of the next period with respect to the input pulse waveform 21. The pulse peak is initially detected according to the operation characteristics of the comparator 11 of the peak detection circuit according to the prior art, and then, for a small pulse peak, the peak detection capacitor 13 is not charged by the comparator 11 and maintained. The charge potential gradually decreases as it discharges from the capacitor with small capacitance.

However, in the case where a pulse peak larger than the previous period is applied in the next period after the initial pulse peak detection, the magnitude of the pulse peak is gradually decreased after the magnitude of the pulse peak is maintained by the peak detecting capacitor 13. Therefore, the conventional peak detection circuit has a peak detection performance for the pulse signal of the continuous period by using a circuit simply composed of a comparator, a diode, and a capacitor.

3 is an output waveform diagram for a pulse peak input signal when a pulse having a small duty ratio according to the prior art has a discontinuous period or a long period and varies in size.

Here, a pulse having a small duty rate means a pulse width within 1 microsecond, and a long period means a frequency of several hundred hertz (Hz) in which the pulse is repeated every period of 1 millisecond (msec) or more.

That is, the output of the peak detection circuit according to the prior art has a peak capacitance capacitor having a small capacitance since the pulse width is short within 1 microsecond (usec), but the pulse repetition period is long by several milliseconds (msec). The energy stored in 13) is discharged before the next period in which the pulse is input so that the detected peak value is not maintained. Therefore, the pulse peak waveform 32 appears in the form of a triangular wave, and thus the magnitude of the detected pulse peak varies at each measurement point, which is not suitable for application to an input signal of the control device.

4 is another peak holding circuit diagram according to the related art, in which an input peak and a comparator output are added to detect and maintain a peak of a pulse input signal.

Specifically, the input peak and the comparator output are added to deliver a signal above the threshold voltage to the diode 9 to compensate for diode nonlinearity, to maintain the peak by the non-inverting amplifier 12, and to offset by the inverting amplifier 24. The guarantee and peak detection values are corrected, and the discharge cycle of the capacitor 10 is set by the timing circuit 24.

However, in the peak holding circuit of FIG. 4, the circuit configuration is complicated by adding an input signal and a comparator output signal and reprocessing them at a later stage, which causes errors in processing and additional power loss. In addition, a delay time must be provided for synchronization between the output signal of the comparator 16 and the output signal of the transistors 20 and 21, but it is very difficult to set the delay time. In addition, there is a problem in that a reference potential requiring a separate high precision is required for the comparator 16, and a plurality of electrical paths connected to the peak holding capacitor 10 are provided. That is, there is a problem that it is difficult to secure a sufficient peak holding time due to the large number of discharge paths due to leakage current.

The present invention devised to solve the above problems provides a pulse peak detection and holding circuit that makes it easy to detect the peak value of a narrow pulse using the difference in capacitance of a plurality of capacitors and to maintain the detected peak value. There is a purpose.

According to one aspect of the present invention, a pulse peak detection and retention circuit includes: a pulse peak detection unit including a pulse peak detection capacitance element for detecting a peak value of an applied pulse signal; And a pulse peak holding unit configured to hold a pulse peak holding capacitance element for holding the magnitude of the detected pulse peak value output from the pulse peak detecting unit, wherein the capacitance of the pulse peak holding capacitance element is included. Is greater than the capacitance of the pulse peak detection capacitance element.

Preferably, the pulse peak detection unit, the voltage divider circuit portion for reducing the magnitude of the pulse without distorting the applied pulse signal; A differential amplifier receiving the divided output of the divided circuit unit as a non-inverting terminal; A capacitive element for pulse peak detection charged with an output of the differential amplifier and coupled to an inverting terminal of the differential amplifier; And a unidirectional semiconductor element and a charge current limiting resistor connected in series between the output terminal of the differential amplifier and the capacitive element for detecting the pulse peak.

Preferably, the pulse peak holding unit, an error amplifier for receiving the output signal of the differential amplifier as a non-inverting terminal; A pulse peak holding switch controlled to an output signal of the error amplifier; A pulse peak holding capacitance element charged according to an operation of the pulse peak holding switch; And a charging resistor disposed between the pulse peak holding switch and the pulse peak holding capacitance element, wherein an output of the pulse peak holding switch is applied to an inverting terminal of the error amplifier.

Preferably, the capacitance of the pulse peak holding capacitance element is thousands to tens of thousands times larger than the capacitance of the pulse peak detection capacitance element.

Preferably, the pulse peak holding capacitance element is several to several tens of picofarads.

Preferably, the semiconductor device further includes a resistor for direct current coupling disposed between the node between the unidirectional semiconductor element and the resistor for limiting the charging current and the capacitive element for maintaining the pulse peak.

Preferably, the energy is charged in the pulse peak holding capacitive element connected in parallel with the pulse peak holding capacitance element and switched every time to an externally applied switching signal to detect a peak of a new pulse. A discharge switch further comprises.

Moreover, the pulse peak detection and retention circuit which concerns on another aspect of this invention is a pulse peak detection unit comprised by the pulse peak detection capacitance element for detecting the peak value of the pulse signal applied; A pulse peak holding unit configured to include a pulse peak holding capacitance element for holding the magnitude of the detected pulse peak value output from the pulse peak detecting unit; A DC coupling unit disposed between the pulse peak detecting unit and the pulse peak holding unit to provide a charge / discharge path between the pulse peak detecting capacitance element and the pulse peak holding capacitance element, and to adjust a charging time; And the capacitance of the pulse peak holding capacitance device is thousands to tens of thousands times larger than the capacitance of the pulse peak detection capacitance device.

Preferably, the DC coupling unit, one side is coupled to the power supply voltage applied from the outside, the other side is electrically coupled with the error amplifier in the pulse peak holding unit is offset correction resistor for correcting the offset of the error amplifier ; A DC coupling resistor coupled between the other side of the offset correction resistor and the pulse peak holding capacitance element; And a discharge switch connected in parallel with the pulse peak holding capacitor and discharging energy charged in the pulse peak holding capacitor to detect a peak of a new pulse by switching every switching period to an externally applied switching signal. It includes.

According to the present invention, nanosecond pulse width peak detection is possible using a pulse peak detection capacitor having a small capacitance. In addition, the application of the pulse peak holding capacitor having a larger capacitance than the pulse peak detecting capacitor enables the storage and maintenance of the detected pulse peak energy having a long period. In addition, the peak value of the detected pulse signal can be maintained for a long time by compensating for the error of the pulse peak holding capacitor and the pulse peak detecting capacitor by the transistor current amplifier connected to the error comparator and the error comparator output terminal of the pulse peak holding unit.

In addition, it is possible to maintain the linearity of the output signal and adjust the pulse peak detection speed compared to the pulse signal input through the DC coupling of the pulse peak detection unit and the fill peak holding unit. In addition, by configuring the voltage dividing circuit portion of the pulse peak detection unit with a capacitive element, it is possible to minimize the attenuation of the original signal due to the high frequency characteristic and to correct the offset of the DC component. In addition, since the output of the DC signal that matches the peak of the input pulse waveform, the reliability is high, and the A / D conversion of the main controller to process it is easy, thereby improving the main controller processing speed and memory capacity can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only one of the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

5 is a block circuit diagram of a pulse peak detection and retention circuit in accordance with the present invention.

The pulse peak detecting and holding circuit according to the present invention includes a pulse peak detecting unit 510 for detecting a peak value of a pulse, a pulse peak holding unit 520 for keeping a detected pulse peak value constant, and a pulse peak detecting unit 510. ) And a DC coupling unit 530 for directly coupling the pulse peak holding unit 520.

The pulse peak detection unit 510 according to the present invention includes a voltage divider 511, a differential amplifier 512, a capacitor charging diode 513, and a pulse peak detection capacitor 514.

The voltage dividing circuit unit 511 attenuates only the magnitude of the pulse signal without distortion of the pulse waveform within the input range of the differential amplifier 512. The voltage dividing ratio of the high frequency input signal is fixed according to the design value by using a capacitor connected in series. The DC offset included in the input pulse signal is removed by using the DC component removal characteristic of the capacitor.

The differential amplifier 512 receives the output voltage of the voltage divider circuit 511 as the non-inverting terminal (+) and receives the voltage applied to the pulse peak detection capacitor 514 as the inverting terminal (-) to generate a difference therebetween. Outputs

The capacitor charging diode 513 provides a path for charging the output of the differential amplifier 513 to the pulse peak detection capacitor 514 by using the characteristic of the device to conduct current in one direction.

Meanwhile, the pulse peak holding unit 520 according to the present invention includes an error amplifier 521, a pulse peak holding switch 522, and a pulse peak holding capacitor 523.

The error amplifier 521 receives the output signal of the differential amplifier 512 through the non-inverting terminal (+) and receives the voltage applied to the pulse peak holding capacitor 523 through the inverting terminal (-). Amplify.

The pulse peak holding switch 522 charges the pulse peak holding capacitor 523 using the output signal of the error amplifier 521 as a control signal of the switch 522. According to one embodiment of the invention, the pulse peak holding switch may be a transistor. Further, according to another embodiment of the present invention, the pulse peak holding switch may be a FET.

The pulse peak holding capacitor 523 is a storage device for holding the detected pulse peak signal and has a capacitance that is thousands to tens of thousands times larger than the capacitance of the pulse peak detection capacitor 514.

In addition, the DC coupling unit 530 uses the DC coupling of the pulse peak detection unit 510 and the pulse peak holding unit 520 to perform the pulse peak detection capacitor 514 and the pulse peak holding capacitor 523 during circuit operation. It adjusts the time constant of and controls the linearity of the peak value detection speed of the pulse and the output signal compared to the input pulse signal.

6 is a detailed circuit diagram of a pulse peak detection and retention circuit according to an embodiment of the present invention.

Pulse peak detection unit 510 according to an embodiment of the present invention is a voltage divider 611, a differential amplifier 612, a capacitor charging diode 613, a capacitor charge current limiting resistor 614, pulse peak detection Capacitor 615 is included.

 When a pulse signal is applied to the input terminal, the voltage dividing circuit unit 611 divides the pulse signal to a low voltage so as to satisfy the input voltage range of the differential amplifier 612. The voltage divider circuit 611 is composed of a capacitor voltage divider circuit, so that the signal attenuation due to voltage dividing is small with respect to an input high frequency signal, thereby providing a stable voltage division ratio. You can remove the offset.

The differential amplifier 612 receives the divided pulse signal through the non-inverting terminal (+), and the output signal of the differential amplifier 520 pulses through the capacitor charging diode 613 and the capacitor charging current limiting resistor 614. The peak detection capacitor 615 is applied to charge the pulse peak detection capacitor 615. The charging voltage of the pulse peak detecting capacitor 615 is input to the inverting terminal (-) of the differential amplifier 612, and the differential amplifier 520 compares the inputs of the inverting terminal (+) and the non-inverting terminal (-). To generate an output signal.

In addition, the pulse peak holding unit 520 according to an embodiment of the present invention includes an output signal delay resistor 621, an error amplifier 622, a switch driving diode 623, a smoothing capacitor 624, and a pulse peak. The holding switch 625, the pulse peak holding capacitor charging resistor 626, and the pulse peak holding capacitor 627.

The non-inverting terminal (+) of the error amplifier 622 receives the output signal of the differential amplifier 612 applied through the output signal delay resistor 621, and the inverting terminal (-) receives the pulse peak holding switch ( The output current of 625 is applied, and these are compared and output.

The output signal output from the error amplifier 622 is applied to the smoothing capacitor 624 and the pulse peak holding switch 625 via the switch driving diode 623. The smoothing capacitor 624 keeps the output signal of the error amplifier 622 applied to the pulse peak holding switch 625 constant.

The pulse peak holding switch 625 may be configured as an emitter follower current amplifier. The output current of the pulse peak holding switch 625 is fed back to the inverting terminal (-) of the error amplifier 622 to compensate for the error of the pulse peak holding unit 520. The output current of the pulse peak holding switch 625 is charged to the pulse peak holding capacitor 627 via the pulse peak holding capacitor charging resistor 626.

The pulse peak holding capacitor 627 is a device for storing and maintaining the detected pulse peak, and has a capacitance of several tens to several tens of nF, which is thousands to tens of thousands times larger than the peak detecting capacitor 615 having a capacitance of several pF. Has a capacitance. The output signal of the pulse peak detecting and holding circuit according to the present invention means a voltage across the pulse peak holding capacitor 627.

The DC coupling unit 530 includes a discharge switch 631, a DC coupling resistor 632, and an offset correction resistor 633 for an error amplifier.

On the other hand, the DC coupling resistor 632 is charged and discharged between the pulse peak detecting capacitor 615 and the pulse peak holding capacitor 627 through DC coupling of the pulse peak detecting unit 510 and the pulse peak holding unit 520. Form a route and adjust the charging time.

The error amplifier offset correction resistor 633 and the output signal delay resistor 621 divide an externally applied DC offset correction power supply voltage 634 and apply them to the non-inverting terminal (+) of the error amplifier 622. Correct the existing DC offset output of amplifier 622.

The discharge switch 631 is controlled by a switching signal applied externally to detect and maintain a peak of a new pulse every cycle to discharge and reset the energy charged in the pulse peak holding capacitor 627 to the ground side.

7 is a small signal equivalent circuit diagram of a pulse peak detection and retention circuit according to the present invention.

The small signal equivalent circuit of the pulse peak detection and sustaining circuit according to the present invention includes a differential amplifier output impedance 710, a pulse peak detecting capacitor 720, a DC coupling resistor 730, and a pulse peak holding capacitor 740. Include. Here, the error amplifier 622 and the pulse peak holding switch 625 can be omitted because the input impedance is large.

In the initial state, there is no energy charged in the pulse peak detecting capacitor 720 and the pulse peak holding capacitor 740 and thus a short state.

In this case, the applied pulse signal is divided by the differential amplifier output impedance 710 and the DC coupling resistor 730 to charge the pulse peak detection capacitor 720. This is because the capacitance of the pulse peak holding capacitor 740 is thousands to tens of thousands times larger than the capacitance of the pulse peak detecting capacitor 720.

On the other hand, since the time constant formed by the DC coupling resistor 730 and the pulse peak holding capacitor 740 is much longer than the time constant consisting of the differential amplifier output impedance 710 and the pulse peak detecting capacitor 720, the capacitor for pulse peak detecting After the charging voltage 720 reaches the peak value of the input signal, the pulse peak holding capacitor 740 is charged.

8 is an output waveform diagram when a pulse having a short duty width and a long period is input according to the present invention.

Here, the short duty width means a pulse width within 1 microsecond (usec), the long period means a frequency of several hundred Hz having a period of 1 millisecond (msec) or more.

In FIG. 8, the pulse peak waveform 82 is output while the magnitude of the pulse peak is maintained until the pulse waveform of the next period with respect to the input pulse waveform 81, and the peak of the pulse detected by the pulse peak detection unit 510 is represented. It is confirmed that the pulse peak holding unit 520 is not attenuated by the operation and is kept constant until the next input pulse signal.

Therefore, since the detected pulse peak output is constant for each pulse applied every cycle, it can have high reliability as a control input, and the A / D conversion processing of the main controller which processes it is simple, thereby improving the execution speed of the control program.

9 is an output waveform diagram of a pulse peak signal applied when an operation of the discharge switch 631 according to the present invention is added.

In FIG. 9, the output of the pulse peak detecting unit 510 is constantly maintained by the operation of the pulse peak holding unit 520, and then the energy charged in the pulse peak holding capacitor 627 is discharged by the operation of the discharge switch 631. The detected pulse peak signal is initialized. Then, when the pulse signal of the next period is applied, the pulse peak is detected and maintained by the operation of the pulse peak detection unit 510 and the pulse peak holding unit 520, and this process is repeated.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Various modifications and variations are possible within the scope of equivalents of the claims to be described.

Pulse peak detection circuit according to the prior art of FIG.

2 is a pulse peak input signal and an output waveform diagram varying during a continuous period in a peak detection circuit according to the prior art;

3 is an output waveform diagram for a pulse peak input signal when a pulse having a small duty ratio according to the prior art has a discontinuous period or a long period and varies in size.

4 is a peak hold circuit diagram according to another prior art;

5 is a block circuit diagram of a pulse peak detection and retention circuit in accordance with the present invention;

6 is a detailed circuit diagram of a pulse peak detection and retention circuit according to an embodiment of the present invention;

7 is a small signal equivalent circuit diagram of a pulse peak detection and retention circuit according to the present invention;

8 is an output waveform diagram when a pulse having a short duty width and a long period is input according to the present invention; and

9 is an output waveform diagram of a pulse peak signal applied when an operation of a discharge switch according to the present invention is added.

* Brief description of the main parts of the drawing *

510: pulse peak detection unit 511: voltage divider circuit

512: differential amplifier 513: capacitor charging diode

514: capacitor for detecting pulse peak 520: pulse peak holding unit

521: error amplifier 522: pulse peak maintenance switch

523: capacitor for pulse peak holding 530: DC coupling unit

Claims (10)

A pulse peak detection unit including a pulse peak detection capacitance element for detecting a peak value of an applied pulse signal; And A pulse peak holding unit configured to include a pulse peak holding capacitance element for maintaining the magnitude of the detected pulse peak value output from the pulse peak detecting unit, And the capacitance of the pulse peak holding capacitance element is larger than that of the pulse peak detection capacitance element. The method of claim 1, wherein the pulse peak detection unit, A voltage divider circuit for reducing the magnitude of the pulse without distorting the applied pulse signal; A differential amplifier receiving the divided output of the divided circuit unit as a non-inverting terminal; A capacitive element for pulse peak detection charged with an output of the differential amplifier and coupled to an inverting terminal of the differential amplifier; And A unidirectional semiconductor device and a charge current limiting resistor connected in series between an output terminal of the differential amplifier and the capacitive device for detecting pulse peaks Pulse peak detection and retention circuit comprising a. The method of claim 2, And said divider circuit portion is a plurality of capacitors connected in series. The method of claim 2, wherein the pulse peak holding unit, An error amplifier receiving the output signal of the differential amplifier as a non-inverting terminal; A pulse peak holding switch controlled to an output signal of the error amplifier; A pulse peak holding capacitance element charged according to an operation of the pulse peak holding switch; And A charging resistor disposed between the pulse peak holding switch and the pulse peak holding capacitance element; And an output of the pulse peak holding switch is applied to an inverting terminal of the error amplifier. The method according to any one of claims 1 to 4, And the capacitance of the pulse peak holding capacitance element is thousands to tens of thousands times larger than the capacitance of the pulse peak detection capacitance element. The method of claim 5, The pulse peak holding capacitive element is a pulse peak detection and holding circuit, characterized in that several to tens of picofarads. The method of claim 5, And a DC coupling resistor disposed between the node between the unidirectional semiconductor element and the charge current limiting resistor and the pulse peak holding capacitance element. The method of claim 5, A discharge switch connected in parallel with the pulse peak holding capacitor and switched every time to an externally applied switching signal to discharge energy charged in the pulse peak holding capacitor to detect a peak of a new pulse; Pulse peak detection and retention circuitry further. A pulse peak detection unit including a pulse peak detection capacitance element for detecting a peak value of an applied pulse signal; A pulse peak holding unit configured to include a pulse peak holding capacitance element for holding the magnitude of the detected pulse peak value output from the pulse peak detecting unit; A DC coupling unit disposed between the pulse peak detecting unit and the pulse peak holding unit to provide a charge / discharge path between the pulse peak detecting capacitance element and the pulse peak holding capacitance element and to adjust a charging time; Including; And the capacitance of the pulse peak holding capacitance element is thousands to tens of thousands times larger than the capacitance of the pulse peak detection capacitance element. The method of claim 9, wherein the DC coupling unit, An offset correction resistor, one side of which is coupled to a power supply voltage applied from the outside and the other side of which is electrically coupled with an error amplifier in the pulse peak holding unit to correct an offset of the error amplifier; A DC coupling resistor coupled between the other side of the offset correction resistor and the pulse peak holding capacitance element; And A discharge switch connected in parallel with the pulse peak holding capacitive element and discharging the energy charged in the pulse peak holding capacitive element to be switched at every cycle to an externally applied switching signal to detect a peak of a new pulse; Pulse peak detection and retention circuit comprising a.

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