JPH11316248A - Peak detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a peak detecting circuit for facilitating a countermeasure to a low input signal with several Hz to dozens of Hz without providing any outside capacitive element for holding a hold voltage, to manufacture this peak detecting circuit in a semiconductor integrated circuit in a simple process, and to attain the miniaturization of this system, the reduction of the number of parts, and the cost reduction of the device. SOLUTION: This peak detecting circuit is provided with a peak hold circuit 100 having a capacitive element connected with a peak hold node for holding the peak value of an input signal, capacitive element 210 connected with a voltage source in a prescribed level, and switched capacitor 200 having a switch circuit 220 for switching the connected state of the capacitive element 210 and the hold node of the peak hold circuit 100.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a peak detection circuit for detecting a peak voltage of an input signal.

[0002]

2. Description of the Related Art A peak detection circuit can detect an envelope of an input signal by detecting a peak voltage of an analog input signal, and can control an optimum gain of an amplification stage and an optimum comparison voltage. Therefore, the circuit is useful in a processing system for an analog signal having an input amplitude that is not constant. For this reason, it is used as a peak detection circuit for processing analog signals read by various sensors, such as for communication, servo control, and reproduction from a recording medium.

As a peak detection circuit, as shown in FIG. 22, a circuit PD10 which basically comprises a peak hold circuit 10, or as shown in FIG. 23, a buffer BUF10 is provided at an output of the peak hold circuit 10. A circuit PD10a configured by connecting a sample-and-hold circuit 20 through the circuit is known.

These peak detecting circuits PD10 and PD1
The peak hold circuit 10 used for Oa includes an operational amplifier (hereinafter, referred to as an operational amplifier), a rectifying element, and a capacitive element as main components. The rectifying element is, for example, a diode or a MOS formed in a semiconductor substrate.
It is composed of transistors.

[0005] The peak hold circuit holds new peak values one after another when the amplitude of the input signal gradually increases. However, when the amplitude of the input signal gradually decreases, the following holds. The new peak value cannot be held unless the hold voltage is once smaller than the peak value. Therefore, a high resistance (Rrst) for automatically attenuating the hold voltage or a MOS transistor (NTrst, PTrst) controlled by a reset signal
Such a reset circuit is required. When the hold voltage is attenuated with a high resistance, the degree of attenuation is determined by setting the time constant of Chold · Rrst. However, it is necessary to set it in consideration of the fluctuation of the cycle and amplitude of the input signal. In the case where the hold voltage is attenuated by the reset circuit, means for synchronizing with the input signal and generating a reset signal before the next peak is input is required. Further, when the power is turned on or noise is input, an amplitude larger than the peak value of the input signal may be held and a malfunction may occur. Therefore, a reset circuit is required. When a peak hold circuit is formed by discrete elements, the design range for the signal frequency is easy because the selectable range of the capacitance value Chold of the capacitive element and the high resistance value Rrst is wide.

FIGS. 24 and 25 are circuit diagrams showing a configuration example of a generally used peak hold circuit. FIG. 24 shows a rectifying element as a p-channel MOS (PMOS).
FIG. 25 is a circuit diagram of an upper limit peak hold circuit using a transistor PMOS, and FIG.
FIG. 3 is a circuit diagram of a peak hold circuit for a lower limit using an (NMOS) transistor.

More specifically, the upper limit peak hold circuit 10a is an operational amplifier in which an analog input signal IN is supplied to a non-inverting input terminal (+) and the voltage of the hold node ND11a is fed back to the inverting input terminal (-). AMP11
a, a PMOS transistor PT11a as a rectifying element, which is connected between the output side of the operational amplifier AMP11a and the hold node ND11a, has a gate and a drain connected, and has a substrate connected to a supply line of the power supply voltage V _DD ;
The capacitor C11a connected between the hold node ND11a and the ground GND is configured as a main component. The PMO of the peak hold circuit 10a for the upper limit value
The rectifying element including the S transistor PT11a is connected to the hold node ND11 from the output side of the operational amplifier AMP11a.
It is connected so that it may become a forward direction toward a.

Similarly, the lower limit peak hold circuit 10
b denotes an operational amplifier AMP11b in which the analog input signal IN is supplied to the non-inverting input terminal (+) and the voltage of the hold node ND11b is fed back to the inverting input terminal (-), the output side of the operational amplifier AMP11b, and the hold node ND1.
1b, the gate and the drain are connected,
NMOS transistor NT11 as a rectifier whose substrate is connected to a supply line of power supply voltage V _SS (ground level)
and a capacitive element C11b connected between the hold node ND11b and the ground GND as main components. The rectifying element composed of the NMOS transistor NT11b of the lower limit peak hold circuit 10b is
From the hold node ND11b to the operational amplifier AMP11b
Are connected in a forward direction toward the output side.

Further, in the peak hold circuits of FIGS. 24 and 25, once the amplitude larger than the peak value of the true input signal is held at power-on or when noise is input, the correct peak value is immediately obtained. Because it does not return, malfunction may occur. Therefore, the NMO as a switch for lowering the hold voltage to the voltage VRST is provided in the peak hold circuit 10a on the upper limit value side.
S transistor NT11a (substrate connected to the supply line of the ground voltage V _SS or the voltage VRST), PMOS transistor PT11b (substrate supply voltage as a switch for the peak hold circuit 10b of the lower limit side to increase the hold voltage to the voltage VRST V _DD or voltage VRS
(Connected to the T supply line). The voltage VRST is set to a voltage that does not detect a noise component when the input signal is in a no-signal state, for example.

In the case of the peak hold circuit 10a on the upper limit value side, when the input signal IN becomes larger than the hold voltage, the output of the operational amplifier AMP11a becomes P higher than the input signal IN.
While oscillating around a voltage approximately as high as the threshold value of the rectifier element including the MOS transistor PT11a, the hold voltage is increased so as to follow the input signal IN. When the input signal IN exceeds the peak value, the operational amplifier AMP11a outputs a voltage near the lower limit of the dynamic range.
Although the operation of the peak hold circuit on the upper limit value side in FIG. 24 is an example, the polarity of the operation of the peak hold circuit on the lower limit value side is inverted.

The sample-and-hold circuit 20 includes a switch circuit that is turned on / off by a sampling clock, and a capacitor.

FIG. 26 is a circuit diagram showing an example of the configuration of the sample hold circuit 20.
This is a circuit using an S-type analog switch.

The switch circuit 21 has a gate connected to the sampling clock signal SC via the inverter INV21.
An NMOS transistor NT21 connected to the input line of K, a substrate connected to the supply line of the power supply voltage V _DD , a gate connected to the input line of the sampling clock signal SCK, and a substrate grounded.
21 is connected to the source / drain. The switch circuit 21 is connected between the input line of the signal SIN and the hold node ND21, and a capacitor 22 is connected between the hold node ND21 and the ground line.
Is connected.

FIGS. 27 and 28 are waveform diagrams showing an operation example of a peak detection circuit PD10 constituted by a peak hold circuit for attenuating the hold voltage with high resistance.
9 shows an operation example of a circuit for detecting the envelope by setting the time constant of Chold · Rrst to a small value and detecting individual peaks. FIG. 28 shows an operation example of a peak detection circuit in which the time constant of Chold · Rrst is set to a large value so as to detect the entire peak value.

FIG. 29 is a waveform diagram showing an operation example of a peak detection circuit PD10a composed of a peak hold circuit 10 controlled by a reset signal RST and a sample hold circuit 20 controlled by a sampling clock signal SCK. is there. As shown in FIG. 29, the peak detection circuit PD10a detects the envelope by generating a sampling clock signal SCK and a reset signal RST each time a peak is input. When the sample-hold circuit is formed by discrete elements, the capacitance value Chold of the capacitance element can be set to a relatively large value, so that it is easy to obtain required hold voltage holding characteristics.

[0016]

With the recent reduction in size and weight of systems, analog signal processing circuits have also been incorporated as part of semiconductor integrated circuits. However, in a semiconductor integrated circuit in which it is difficult to form a large capacitance element, the capacitance element used to hold the voltage of the peak hold circuit and the sample hold circuit constituting the peak detection circuit is limited to several pF to several hundred pF at most. Will be done. In a semiconductor integrated circuit, it is possible to use a peak hold circuit for a communication analog signal processing circuit having a high signal frequency to be handled by a conventional circuit technology. It is very difficult to use a peak hold circuit for the processing circuit because the hold voltage holding characteristic becomes strict in inverse proportion to the signal frequency.

That is, in a semiconductor integrated circuit, when a capacitance value such as a discrete capacitor is to be formed on a semiconductor chip, a large layout area or a processing step dedicated to a high-capacity element is required.
The production cost of the semiconductor chip is not worth it. For this reason, the design is performed with the capacitance value of the capacitance element within a range where the manufacturing cost of the semiconductor chip is commensurate, and the peak detection circuit is extremely small in capacitance value of the capacitance element as compared with a case where the circuit is formed by discrete elements. Must be designed. When handling a high signal frequency, the time during which the hold voltage must be held may be short, so that it has been easy to implement a semiconductor integrated circuit. However,
Even if a semiconductor integrated circuit attempts to handle a low signal frequency of several Hz to several tens of Hz, it has been difficult with conventional circuit technology because the holding time becomes long in inverse proportion to the frequency. For example, when trying to attenuate the hold voltage with a high resistance, a high resistance on the order of giga is required, but if the resistance becomes high on that order, the dispersion increases, making it difficult to obtain the required characteristics stably. It is. Further, even in a circuit that does not use a high resistance, the held voltage changes with time due to a leak current generated in a rectifying element and a reset MOS transistor connected to the hold node, and a required hold voltage holding characteristic is required. Was difficult to achieve.

The present invention has been made in view of the above circumstances, and an object of the present invention is to be able to cope with a low input signal of several Hz to several tens of Hz without externally providing a capacitor for holding a hold voltage. In addition, it is an object of the present invention to provide a peak detection circuit which can be manufactured in a semiconductor integrated circuit by a simple process, can reduce the size of the system, reduce the number of components, and can reduce the cost of the apparatus.

[0019]

To achieve the above object, a peak detection circuit according to the present invention has a peak hold circuit having a capacitance element connected to a hold node and holding a peak value of an input signal, A switched capacitor including an attenuating capacitive element connected to the level voltage source, and a switch circuit for switching a connection / disconnection state between the attenuating capacitive element and the hold node of the peak hold circuit.

The peak detection circuit of the present invention has two input terminals, a signal input operational amplifier in which a signal is input to one input terminal and the potential of the hold node is fed back to the other input terminal. A peak rectifier comprising: a rectifying element for hold having one terminal connected to the output side of the operational amplifier for signal input and the other end connected to the hold node; and a capacitive element for hold connected to the hold node. A switched capacitor including a circuit, an attenuating capacitive element connected to a voltage source of a predetermined level, and a switch circuit for switching a connection / disconnection state between the attenuating capacitive element and the hold node of the peak hold circuit. Having.

Further, in the present invention, the capacitance value of the attenuation capacitance element is set to a value smaller than the capacitance value of the hold capacitance element, and the switching operation of the switch circuit is repeatedly performed.

In the present invention, the voltage source supplies a voltage obtained by subtracting a fixed voltage from the hold voltage of the peak hold circuit.

Further, in the present invention, the switched capacitor has a second switch circuit for switching a connection / disconnection state between the attenuation capacitor and the voltage source.

In the present invention, the voltage of the output node of the operational amplifier for signal input of the rectifier element may be a voltage between analog ground and a hold voltage or an output of the operational amplifier for signal input during a hold period. There is provided a voltage adjusting means for adjusting the voltage which has passed over to an analog ground voltage.

In the present invention, the voltage adjusting means includes:
A voltage between the analog ground and the hold voltage, or a reference voltage corresponding to a voltage from the analog ground rather than a voltage at which the output of the signal input operational amplifier has fallen during the hold period, receives the reference voltage corresponding to the voltage from the analog ground. It is constituted by a clamp circuit that clamps the voltage of the output side node to the reference voltage.

According to the present invention, the clamp circuit includes:
A clamping operational amplifier having two input terminals, one input terminal receiving the reference voltage and the other input terminal receiving the voltage of the output node of the signal input operational amplifier; It has a rectifying element connected to the output side of the operational amplifier for clamping and the other terminal connected to a connection point between the output side node of the operational amplifier for signal input and the other input terminal of the operational amplifier for clamping. Further, the clamp circuit has a resistance element connected between the output side of the signal input operational amplifier and the other input terminal of the clamp operational amplifier. The resistance element of the clamp circuit is constituted by an insulated gate field effect transistor having a gate supplied with a control signal.

Further, in the present invention, the control signal causes the insulated gate field effect transistor to be held in a conductive state during a hold period, and turns off the insulated gate field effect transistor when the hold node is reset. This is a signal to be held.

In the present invention, the rectifying element is connected so as to be in a forward direction from an output node side of the signal input operational amplifier toward a hold node, and is connected to an output node of the signal input operational amplifier. Is connected to a pull-up circuit.

In the present invention, the rectifying element is connected so as to be in a forward direction from the hold node toward the output node of the signal input operational amplifier, and is connected to the output node of the signal input operational amplifier. Is connected to a pull-down circuit.

In the present invention, one terminal of the rectifier is connected to the output of the operational amplifier for signal input.
The hold node is connected to the other terminal side, the gate is connected to any one of the one terminal side or the other terminal side, and the gate is connected.The insulated gate field effect transistor is used as the rectifying element. The bulk terminal has an intermediate voltage generating circuit for supplying an intermediate voltage between the analog ground and the hold voltage or an intermediate voltage from the analog ground rather than a voltage at which the output of the operational amplifier for signal input during the hold period is cut off.

In the present invention, one terminal of the rectifier is connected to the output of the operational amplifier for signal input.
The hold node is connected to the other terminal side, the gate is connected to any one of the one terminal side or the other terminal side, and the gate is connected.The insulated gate field effect transistor is used as the rectifying element. An intermediate voltage between the analog ground and the hold voltage, or an intermediate voltage from the analog ground that is lower than the voltage at which the output of the operational amplifier for signal input during the hold period has run out during the hold period, and clamps the intermediate voltage to the bulk terminal. And an intermediate voltage generating circuit for supplying the reference voltage to the circuit.

In the present invention, the switch circuit for switching the connection state of the switched capacitor with the hold node is constituted by an insulated gate field effect transistor, and is connected to a bulk terminal of the insulated gate field effect transistor of the switch circuit. An intermediate voltage generating circuit is provided which supplies an intermediate voltage between the analog ground and the hold voltage or an intermediate voltage from the analog ground which is lower than the voltage at which the output of the operational amplifier for signal input during the hold period is cut off.

In the present invention, one terminal of the rectifier is connected to the output of the operational amplifier for signal input.
The hold node is connected to the other terminal side, the gate is connected to either the one terminal side or the other terminal side, and the gate is connected to the switch node. A switch circuit for switching a connection state is constituted by an insulated gate field effect transistor. The bulk terminal of the insulated gate field effect transistor as the rectifier element and the bulk terminal of the insulated gate field effect transistor of the switch circuit are held from analog ground. An intermediate voltage generating circuit for supplying an intermediate voltage between the voltages or an intermediate voltage from the analog ground rather than a voltage at which the output of the operational amplifier for signal input during the hold period is cut off.

In the present invention, one terminal of the rectifier is connected to the output of the operational amplifier for signal input.
The hold node is connected to the other terminal side, the gate is connected to either the one terminal side or the other terminal side, and the gate is connected to the switch node. A switch circuit for switching a connection state is constituted by an insulated gate field effect transistor. The bulk terminal of the insulated gate field effect transistor as the rectifying element and the bulk terminal of the insulated gate field effect transistor of the reset circuit are held from analog ground. An intermediate voltage between the voltages, or an intermediate voltage from the analog ground which is higher than the voltage at which the output of the operational amplifier for signal input during the hold period has been cut off, and the intermediate voltage is supplied to the clamp circuit as the reference voltage. And the intermediate voltage generation circuit To.

Further, the peak detection circuit of the present invention has two input terminals, a signal is input to one input terminal, and a potential of the first hold node is fed back to the other input terminal. An operational amplifier for signal input, and one terminal
A first hold rectifying element connected to the output side of the operational amplifier for signal input and the other terminal side connected to the first hold node; and a first hold connected to the first hold node. A first peak hold circuit including a capacitive element for use and an attenuating means for attenuating a hold voltage at the time of reset; and two input terminals. The input signal is input to one input terminal, and the other input terminal. A second signal input operational amplifier having a terminal to which the potential of the second hold node is fed back, one terminal connected to the output side of the second signal input operational amplifier, and the other terminal connected to the second signal input operational amplifier. A second hold rectifier connected to the hold node; a second hold capacitor connected to the second hold node; and a peak value held by at least the first peak hold circuit. The potentials of the first holding node of the first peak hold circuit and a second peak hold circuit comprising a load means for transmitting to the second hold node.

In the present invention, the attenuating means is constituted by a first switch connecting the first hold node to a reset potential at the time of reset, and the load means is provided at the time of loading by the second hold node. Is the first
And a second switch connected to the first hold node of the peak hold circuit.

In the present invention, the first rectifying element of the first peak hold circuit has one terminal connected to the output of the first signal input operational amplifier and the other terminal connected to the first terminal. And a first insulated gate field effect transistor that functions as a rectifying element when the gate is connected to either the one terminal side or the other terminal side, and the second peak hold The second rectifier element of the circuit has one terminal connected to the output of the second signal input operational amplifier and the other terminal connected to the second terminal.
And a second insulated gate field effect transistor that functions as a rectifying element when the gate is connected to either the one terminal side or the other terminal side. Connects the gate of either one terminal or the other terminal of the first insulated gate type field effect transistor to function as a first rectifier element, and resets the first hold node when the first hold node is reset. The load means is constituted by a reset / hold switching circuit for holding either the terminal side or the other terminal side and the gate in a non-connected state and holding the first insulated gate type field effect transistor in a conductive state. During the hold period, the gate is connected to either one terminal or the other terminal of the second insulated gate field effect transistor. Connected to function as a second rectifying element, and at the time of loading, one of the one terminal side or the other terminal side and the gate are kept in a non-connected state, so that the second insulated gate field effect transistor is turned on. And a load / hold switching circuit for connecting the first hold node of the first peak hold circuit to one terminal of the second insulated gate field effect transistor.

In the present invention, the attenuating means is constituted by a first switch for connecting the first hold node to a reset potential at the time of reset, and the second rectifying element of the second peak hold circuit comprises one switch. The terminal side is connected to the output side of the second signal input operational amplifier, the other terminal side is connected to the second hold node, and the rectification is performed when the gate is connected to either the one terminal side or the other terminal side. The load means comprises an insulated gate type field effect transistor functioning as an element, and the load means connects the gate to either one terminal side or the other terminal side of the insulated gate type field effect transistor during a hold period to form a second element. During loading, either the one terminal side or the other terminal side and the gate are kept in a non-connected state, and the insulating gate is connected. And a load / hold switching circuit for connecting the first hold node of the first peak hold circuit to one terminal of the insulated gate field effect transistor while keeping the transistor in a conductive state. I have.

In the present invention, the first rectifying element of the first peak hold circuit has one terminal connected to the output of the first signal input operational amplifier and the other terminal connected to the first terminal.
Is connected, and the gate is connected to either the one terminal side or the other terminal side, and is constituted by an insulated gate type field effect transistor which functions as a rectifying element, and the attenuating means is provided during a hold period. Connecting the gate to either the one terminal side or the other terminal side of the first insulated gate field effect transistor to function as a first rectifying element, and resetting the one terminal when resetting the first hold node. And a reset / hold switching circuit for holding the gate in a non-connected state with either the side or the other terminal side and holding the insulated gate field effect transistor in a conductive state. A second switch for connecting the second hold node to the first hold node of the first peak hold circuit; And it is made of.

According to the present invention, in at least one of the first peak hold circuit and the second peak hold circuit, a voltage at an output node of the operational amplifier for signal input of the rectifier element is held from analog ground. There is provided a voltage adjusting means for adjusting a voltage between the voltages or a voltage from the analog ground to a voltage from which the output of the operational amplifier for signal input during the hold period has swung off.

Further, according to the present invention, the voltage adjusting means includes:
A voltage between the analog ground and the hold voltage, or a reference voltage corresponding to a voltage from the analog ground rather than a voltage at which the output of the signal input operational amplifier has fallen during the hold period, receives the reference voltage corresponding to the voltage from the analog ground. It is constituted by a clamp circuit that clamps the voltage of the output side node to the reference voltage.

Further, according to the present invention, the clamp circuit includes:
A clamping operational amplifier having two input terminals, one input terminal receiving the reference voltage and the other input terminal receiving the voltage of the output node of the signal input operational amplifier; A rectifying element is connected to the output side of the operational amplifier for clamping and has another terminal connected to a connection point between the output node of the operational amplifier for signal input and the other input terminal of the operational amplifier for clamping. Also,
The clamp circuit has a resistance element connected between the output side of the signal input operational amplifier and the other input terminal of the clamp operational amplifier. The resistance element of the clamp circuit is constituted by an insulated gate field effect transistor having a gate supplied with a control signal.

Further, in the present invention, the control signal causes the insulated gate field effect transistor to be held in a conductive state during a hold period, and turns off the insulated gate field effect transistor when the hold node is reset. This is a signal to be held.

In the present invention, the control signal is a clamp assist voltage signal set according to the output voltage of the clamp operational amplifier.

Further, in the present invention, in at least one of the first peak hold circuit and the second peak hold circuit, the rectifying element is arranged from the output node side of the signal input operational amplifier toward the hold node. The pull-up circuit is connected so as to be in a forward direction, and is connected to an output node of the operational amplifier for signal input.

Further, in the present invention, in at least one of the first peak hold circuit and the second peak hold circuit, the rectifier element is arranged from a hold node toward an output node of the signal input operational amplifier. The pull-down circuit is connected so as to be in the forward direction, and is connected to the output node of the operational amplifier for signal input.

According to the present invention, in at least one of the first peak hold circuit and the second peak hold circuit, the rectifying element has one terminal connected to the output side of the signal input operational amplifier, The hold node is connected to the other terminal side, the gate is connected to any one of the one terminal side or the other terminal side, and the gate is connected.The insulated gate field effect transistor is used as the rectifying element. The bulk terminal has an intermediate voltage generating circuit for supplying an intermediate voltage between the analog ground and the hold voltage or an intermediate voltage from the analog ground rather than a voltage at which the output of the operational amplifier for signal input during the hold period is cut off.

Further, in the present invention, in at least one of the first peak hold circuit and the second peak hold circuit, the rectifying element has one terminal connected to the output side of the signal input operational amplifier, The hold node is connected to the other terminal side, the gate is connected to any one of the one terminal side or the other terminal side, and the gate is connected.The insulated gate field effect transistor is used as the rectifying element. An intermediate voltage between the analog ground and the hold voltage, or an intermediate voltage from the analog ground that is lower than the voltage at which the output of the operational amplifier for signal input during the hold period has run out during the hold period, and clamps the intermediate voltage to the bulk terminal. And an intermediate voltage generating circuit for supplying the reference voltage to the circuit.

Further, in the present invention, the attenuating means is constituted by an insulated gate type field effect transistor comprising a first switch connecting the first hold node to a reset potential at the time of resetting, and the loading means comprises a load. Occasionally, the second hold node is constituted by an insulated gate type field effect transistor comprising a second switch connecting the second hold node to the first hold node of the first peak hold circuit, and at least one of the attenuation means or the load means Supply the intermediate voltage between the analog ground and the hold voltage to the bulk terminal of the insulated gate type field effect transistor, or the intermediate voltage from the analog ground that is lower than the voltage at which the output of the operational amplifier for signal input during the hold period is cut off It has an intermediate voltage generation circuit.

In the present invention, in at least one of the first peak hold circuit and the second peak hold circuit, one terminal of the rectifier is connected to the output of the operational amplifier for signal input. The hold node is connected to the other terminal side, the gate is connected to one of the one terminal side or the other terminal side, and the gate is connected to the other. Is connected to a reset potential, the insulated gate type field effect transistor comprising a first switch, and the load means connects the second hold node to the first node during loading.
, And a bulk terminal of the insulated gate field effect transistor as the rectifying element and the attenuating means or the loading means. The intermediate voltage between the analog ground and the hold voltage at the bulk terminal of at least one of the insulated gate type field effect transistors, or the intermediate voltage from the analog ground which is lower than the voltage at which the output of the operational amplifier for signal input during the hold period is cut off And an intermediate voltage generating circuit for supplying the same.

Further, in the present invention, in at least one of the first peak hold circuit and the second peak hold circuit, the rectifying element has one terminal connected to the output side of the signal input operational amplifier, The hold node is connected to the other terminal side, the gate is connected to one of the one terminal side or the other terminal side, and the gate is connected to the other. Is connected to a reset potential, the insulated gate type field effect transistor comprising a first switch, and the load means connects the second hold node to the first node during loading.
, And a bulk terminal of the insulated gate field effect transistor as the rectifying element and the attenuating means or the loading means. The intermediate voltage between the analog ground and the hold voltage at the bulk terminal of at least one of the insulated gate type field effect transistors, or the intermediate voltage from the analog ground which is lower than the voltage at which the output of the operational amplifier for signal input during the hold period is cut off And an intermediate voltage generating circuit for supplying the intermediate voltage to the clamp circuit as the reference voltage.

According to the present invention, the peak hold circuit
When the amplitude of the input signal gradually increases, the new peak value is held one after another, but when the amplitude of the input signal gradually decreases, the hold voltage is not once reduced below the next peak value. Since a new peak value cannot be held, a switched capacitor for attenuating the hold voltage at the hold node of the peak hold circuit is connected to the hold node, whereby the hold voltage is attenuated and peak detection is reliably performed.

Further, according to the present invention, for example, in the first peak hold circuit, the potential of the first hold node is attenuated by the attenuating means every time a pulse of the input signal is input, and the peak value of the pulse of the input signal is reduced. Are detected one after another regardless of the increase or decrease in the amplitude. On the other hand, in the second peak hold circuit, the load voltage output of the first peak hold circuit is transmitted to the second hold node by the load means. Then, when the amplitude of the input signal gradually increases, the peak value is quickly held through the operational amplifier constituting the second peak hold circuit. On the other hand, when the amplitude of the input signal gradually decreases, the load voltage output of the first peak hold circuit is transmitted to the second hold node of the second peak hold circuit by the load means.

According to the present invention, the provision of the voltage adjustment means allows the output of the operational amplifier to output the intermediate voltage between the analog ground and the hold voltage by the voltage adjustment means, or the output of the operational amplifier for signal input during the hold period. Since the output voltage is adjusted to the reference voltage corresponding to the voltage from the analog ground rather than the voltage at which the output has been swung, a voltage near the reference voltage is output from the output of the operational amplifier when the input signal exceeds the peak value. As a result, the voltage difference between the node on the operational amplifier side of the rectifying element and the hold node is smaller than that of a conventional circuit that does not include voltage adjusting means such as a clamp circuit, and the leakage current in the rectifying element is reduced,
Good holding characteristics are obtained.

According to the present invention, when the resistance element of the clamp circuit is constituted by an insulated gate field effect transistor having a gate supplied with a control signal, the insulated gate field effect transistor is turned on during the hold period. State, and the insulated gate field effect transistor is held in a non-conductive state at the time of reset. This ensures that the reset is performed, and prevents the hold voltage from changing in the reverse direction even when it takes time for the output of the operational amplifier to return to the intermediate potential immediately after the reset is released.

According to the present invention, when the resistance element of the clamp circuit is constituted by an insulated gate type field effect transistor having a gate supplied with a control signal, the control signal is output from the clamp operational amplifier. When the clamp assist voltage signal is set according to the voltage, when the output of the operational amplifier for signal input swings greatly, the clamp assist voltage signal is used to reduce the current capability of the sum of the resistance elements during the clamp operation. Is done.

According to the present invention, the rectifying element of the peak hold circuit is constituted by an insulated gate field effect transistor and / or resets the hold voltage. In the case where the attenuating means and the load means comprising an insulated gate type field effect transistor as a switch to be provided are provided, the bulk terminal of the insulated gate type field effect transistor as a rectifying element and the bulk of the insulated gate type field effect transistor of the reset circuit The terminal is supplied with an intermediate voltage between the analog ground and the hold voltage, or an intermediate voltage from the analog ground that is higher than the voltage at which the output of the operational amplifier for signal input during the hold period is cut off. As voltage It is fed. Thereby, the leak current in the rectifier and the reset circuit is reduced.

[0058]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing a first embodiment of a peak detection circuit according to the present invention, and FIG. 2 is a circuit showing a specific configuration example of the peak detection circuit. FIG. The specific circuit shown in FIG. 2 according to the first embodiment is for the upper limit value. The peak detection circuit PD100 according to the first embodiment includes a peak hold circuit 100, as shown in FIGS.
And a peak detection circuit with an attenuation function configured by a switched capacitor 200 for attenuating the hold voltage.

As shown in FIG. 2, the peak hold circuit 100 includes an operational amplifier 110, a rectifying element 120, and a holding capacitive element 130.

In the operational amplifier 110, the input signal IN is input to the non-inverting input terminal (+), and the inverting input terminal (-)
, The voltage of the hold node ND101 is fed back.

The rectifier 120 is connected between the output of the operational amplifier 110 and the hold node ND101. Rectifier 120 is formed of, for example, a diode formed in a semiconductor substrate and connected in a forward direction from the output of operational amplifier 110 toward hold node ND101.

The hold capacitive element 130 has one electrode connected to the hold node ND101 and the other electrode grounded, and holds the signal voltage of the input signal IN via the operational amplifier 110.

In the switched capacitor 200, when the amplitude of the input signal gradually increases, the peak hold circuit 100 holds new peak values one after another, but the amplitude of the input signal gradually decreases. At this time, since the new peak value cannot be held unless the hold voltage is once smaller than the next peak value, the peak voltage is provided to attenuate the hold voltage at the hold node ND101 of the peak hold circuit 100.
Switched capacitor 200 having such a function
As shown in FIG. 2, a connection between the node ND201 and the hold node ND101 of the peak hold circuit 100, and an attenuation capacitor 210 for attenuating a hold voltage connected between the node ND201 and the ground line,
A first switch circuit 220 for switching a non-connection state according to a signal φrdc, and a connection / non-connection state between the node ND201 and a voltage source of VRST or AGND for a signal φr
The second switch circuit 230 switches according to dcz.

The capacitance value Chold of the hold capacitance element
The ratio of the capacitance value of the attenuating capacitance element to the capacitance value Crdc determines how much the hold voltage is attenuated.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. The input signal IN is supplied to a non-inverting input terminal (+) of the operational amplifier 110. The input signal level gradually increases from the analog ground AGND level, and the hold voltage (hold node ND)
When the output voltage of the operational amplifier 110 becomes higher than the input signal (PHOLD), the output of the operational amplifier 110 oscillates near a voltage higher than the input signal by about the threshold value of the rectifying element 120 and lowers the hold voltage so as to follow the input signal.

At this time, in the switched capacitor 200, as shown in FIGS. 3B and 3C, the signal φr
dc is supplied to the first switch circuit 220 at a low level, and the signal φrdcz is supplied to the second switch circuit 230 at a high level. As a result, the first switch circuit 220 is kept in a non-conductive state, and the second switch circuit 230 is kept in a conductive state. Therefore, attenuating capacitive element 210 (node ND201) is connected to, for example, VR
It is connected to the voltage source of ST, and the potential of the node ND201 is held at VRST.

When the peak value is held by the peak hold circuit 100, the signal φrdcz is supplied to the second switch circuit 230 at a low level, as shown in FIGS. The signal φrdc is supplied to the first switch circuit 220 for a predetermined period while the signal φrdc is at a high level during a period in which the switch circuit 230 is kept in a non-conductive state. As a result, the first switch circuit 220 is held in a conductive state, and the hold node ND101 and the attenuation capacitor 210 (node ND201) are held in a connected state. Accordingly, the charge of the holding capacitor 130 is redistributed to the holding capacitor 130 and the attenuation capacitor 210, and the potential of the node ND101 is attenuated.

Next, in the switched capacitor 200, as shown in FIGS. 3B and 3C, the signal φrdc
Is supplied to the first switch circuit 220 at a low level,
When the signal φrdcz is at a high level and the second switch circuit 23
0 is supplied. As a result, the first switch circuit 2
20 is held in a non-conductive state, and the second switch circuit 23
0 is held in the conductive state, and the hold node ND101
And the attenuating capacitive element 210 are switched to a non-connected state. In this state, the next signal is input to the peak hold circuit 100 and, for example, the peak value PHOLD = (Vhold−V
RST) + VRST = Vhold is the holding capacitive element 13
It is held at 0.

Then, as shown in FIGS. 3B and 3C, the signal φrdcz is supplied to the second switch circuit 230 at a low level, and the second switch circuit 230 is held in a non-conductive state. During this period, the signal φrdc is at a high level and is supplied to the first switch circuit 220 for a predetermined period. As a result, the first switch circuit 220 is held in a conductive state, and the hold node ND101 and the attenuation capacitor 210 (node ND201) are held in a connected state. As a result, charge is accumulated in the hold node ND101 in the attenuating capacitance element 210, and the potential of the node node ND101 is attenuated. At this time, the potential of the hold node ND101 attenuates to a level represented by the following equation.

[0070]

## EQU1 ## PHOLD = (Vhold−VRST) ＳＴChold
/ (Chold + Crdc)｝ + VRST

The above hold and attenuation operations are repeatedly performed.

The capacitance value Crdc of the attenuating capacitance element is designed to be considerably smaller than the capacitance value Chold of the holding capacitance element 130, and the switching operation is repeated many times, so that the attenuation is made pseudo high resistance. It is also possible to operate as described.

As described above, according to the first embodiment, the input signal IN is input to the non-inverting input terminal (+), and the voltage of the hold node ND101 is fed back to the inverting input terminal (-). Operational amplifier 110, operational amplifier 110
A rectifier element 120 connected between the output of the IGBT and the hold node ND101, and one electrode connected to the hold node ND101, the other electrode grounded, and a signal voltage of the input signal IN via the operational amplifier 110. A peak hold circuit 100 having a hold capacitance element 130 for holding the voltage, an attenuation capacitance element 210 for attenuating a hold voltage connected between the node ND201 and the ground line, and holding the node ND201 and the peak hold circuit 100. Connection with the node ND101,
First switch circuit 220 for switching the non-connection state in accordance with signal φrdc, and nodes ND201 and VRST
Alternatively, the second switch circuit 230 that switches the connection / disconnection state with the voltage source of AGND according to the signal rdcz.
And the switched capacitor 200 for attenuating the hold voltage is provided, so that the hold voltage of the peak hold circuit constituting the peak detection circuit can be attenuated without using a high resistance. Moreover, depending on how the reset is applied, a certain percentage of the hold voltage is attenuated according to the amplitude of the input signal regardless of the fluctuation of the cycle of the input signal, or the resistance is attenuated as the input signal cycle becomes longer, such as a resistor. It is possible to

Second Embodiment FIG. 4 is a circuit diagram showing a second embodiment of the peak detection circuit according to the present invention. The peak detection circuit PD100a according to the second embodiment is for a lower limit value. Basically, as shown in FIG. 1, a peak hold circuit 100a and a switched capacitor 20 for attenuating a hold voltage are used.
0 is a peak detection circuit with an attenuation function constituted by 0.

In the peak detection circuit for the lower limit according to the second embodiment, the rectifier element 120 is not forwarded from the output of the operational amplifier 110 to the hold node ND101, but is forwardly directed from the hold node ND101 to the output of the operational amplifier 110. It is connected so that it may become.

FIG. 5 is a timing chart showing an operation example of the circuit of FIG. The operation of the lower limit side peak detection circuit in FIG. 4 is the one in which the polarity in the case of the upper limit side peak detection circuit shown in FIG. 3 is inverted. It is a figure in case switching is repeated many times. Therefore, a specific description is omitted here.

According to the second embodiment, the first embodiment
The same effect as that of the embodiment can be obtained.

Third Embodiment FIG. 6 is a circuit diagram showing a third embodiment of the peak detection circuit according to the present invention. The peak detection circuit PD100b according to the second embodiment is for an upper limit value.

The difference between the third embodiment and the first embodiment shown in FIG. 2 is that the voltage source connected to the capacitive element 210 of the switched capacitor 200 via the second switch circuit 230 has a peak. It is provided as a circuit 300 that receives the hold voltage of the hold node ND101 of the hold circuit 100 and subtracts a certain voltage from the hold voltage.

With such a configuration, it is also possible to attenuate a fixed voltage such as 100 mV or 200 mV from the initial hold voltage. That is, according to the third embodiment, in a semiconductor integrated circuit, it is possible to attenuate the hold voltage of the peak hold circuit without making a high-resistance device of an order that is not easy to realize. Unavailable damping is also possible.

Fourth Embodiment FIG. 7 is a block diagram showing a peak detection circuit according to a fourth embodiment of the present invention, and FIG. 8 is a circuit diagram showing a specific configuration example of the peak detection circuit. The specific circuit shown in FIG. 8 according to the fourth embodiment is for the upper limit value.

The peak detection circuit P according to the fourth embodiment
D100c is a peak hold circuit multiplex type peak detection circuit. As shown in FIGS. 7 and 8, two first and second peak hold circuits 100-1 and 100-2 are provided.
Are connected in parallel to the input line of the signal IN, a reset function is added to the first peak hold circuit 100-1, and the hold node ND101-1 of the first peak hold circuit 100-1 is connected to the buffer BUF100. The voltage is supplied to the second peak hold circuit 100-2 via the second node and the potential of the hold node ND101-2 is attenuated.

The first peak hold circuit 100-1
As shown in FIG. 8, the operational amplifier 110-1, the rectifying element 1
20-1, the holding capacitance element 130-1, and the hold node ND101-1 in response to the reset signal RST.
Is connected to a voltage source of a predetermined voltage VRST or AGND, and is configured by an attenuation circuit 140-1 for attenuating (resetting) the hold voltage.

The second peak hold circuit 100-2
As shown in FIG. 8, the operational amplifier 110-2, the rectifier 1
20-2, the switching capacitor 14 that receives the hold capacitance element 130-2, and connects the hold node ND101-2 to the output of the buffer BUF100 in response to the load signal LD.
1-2, and comprises an attenuation circuit 140-2 for attenuating (resetting) the hold voltage.

Next, the operation according to the fourth embodiment will be described with reference to the timing chart of FIG. First,
The reset signal RST is active and supplied to the attenuating circuit 140-1 of the first peak hold circuit 100-1, and the potential of the hold node ND101-1 is maintained at VRST, and the input signal IN is changed to the first and second signals. Operational amplifier 110 of the peak hold circuits 100-1 and 100-2
-1 and 110-2 are supplied in parallel to the non-inverting input terminals (+).

In the first peak hold circuit 100-1, as shown in FIGS. 8A and 8B, each time a pulse of the input signal IN is input, the potential of the hold node ND101-1 is reset by the reset signal RST. Input signal IN
Are detected one after another regardless of the increase or decrease in the amplitude.

On the other hand, the second peak hold circuit 100-
In FIG. 8, as shown in FIGS. 8A and 8C, the hold voltage output of the first peak hold circuit 100-1 is transmitted to the hold node ND101-2 via the buffer BUF100 by the load signal LD. When the amplitude of the input signal IN gradually increases, the peak value is quickly held through the operational amplifier 110-2 included in the second peak hold circuit 100-2. On the other hand, when the amplitude of the input signal IN gradually decreases, the first peak hold circuit 1
The hold voltage output of 00-1 appears at the hold node ND100-2 of the second peak hold circuit 100-2.

The second peak hold circuit 100-2
Is pseudo-similar to the operation of the sample-and-hold circuit, but it is excellent in that when the amplitude of the input signal gradually increases, it can respond quickly without any control.
Also, in terms of change over time of the hold voltages in the peak detection circuit, sample-hold circuit, if the switching element is an analog switch V also _DD side attached to V _SS side (CMOS, bulk terminal of the MOS transistor Is V _DD and V _SS ), it is not known whether the direction of the change of the hold voltage with time changes to the V _DD side or the V _SS side depending on the variation of the leak current of the device forming each switching element. However, when the peak hold circuit functions as a sample hold circuit,
As described later, for the rectifying element and the switching element, an NMOS transistor is used in the peak hold circuit of the upper limit value, and a PMOS transistor is used in the peak hold circuit of the lower limit value.
As of using transistors, by selecting the proper polarity, so as to change the V _SS side in the peak hold circuit upper limit value, also designed to vary V _DD side peak hold circuit lower limit It is possible to
This means that it is possible to construct a circuit in which a semiconductor integrated circuit is essentially unlikely to malfunction when a semiconductor integrated circuit is used, which is equivalent to a very high order of high resistance for attenuation.

According to the fourth embodiment, the peak detection circuit PD100c is connected in parallel to the input line of the input signal, and has a function of attenuating the hold voltage to the reset voltage by the reset signal RST. , Input signal I
Every time N pulse is input, it is attenuated by the reset signal.
A first peak hold circuit 1 for successively detecting the peak value of the pulse of the input signal IN regardless of the increase or decrease of the amplitude
00-1 and a function to receive the hold voltage output of the first peak hold circuit 100-1 by the load signal LD. When the amplitude of the input signal gradually increases, the peak value is quickly held through the operational amplifier 100-2. However, when the amplitude of the input signal gradually decreases, the first peak hold circuit 1
The hold voltage output of 00-1 is connected to the hold node ND10.
Second peak hold circuit 100-2 received by 1-2
Thus, it is possible to realize a peak detection circuit that can quickly respond to an increase in the amplitude of the input signal and that can also handle a signal having a noise component or another signal component immediately behind the input signal. Also, by making the peak hold circuit simulate the function of the sample hold circuit, the sample hold circuit can change the direction of the change over time of the hold voltage due to the leak current that cannot be determined whether going to the _VDD side or the _VSS side. towards always V _SS side when holding the voltage of the upper limit value, also, it is possible to design to vary toward always V _DD side in the case of holding the voltage of the lower limit. For this reason, there is an advantage that a peak detection circuit in which a malfunction does not easily occur can be realized without using a high resistance.

Fifth Embodiment FIG. 10 is a circuit diagram showing a fifth embodiment of the peak detection circuit according to the present invention. The peak detection circuit according to the fourth embodiment is a peak hold circuit multiplex type peak detection circuit for the lower limit value.

The fifth embodiment differs from the fourth embodiment in that the first peak hold circuit 100-1
In the above, the rectifying element 120-1 is constituted by the PMOS transistor PT121-1, and instead of providing the attenuation (reset) circuit, a switch which is turned on / off by the reset signal RST between the gate and the drain of the PMOS transistor PT121-1 A reset / hold switching circuit 150-1 having a switch circuit 152-1 that is turned on / off by a reset signal RST is provided between the circuit 151-1 and the gate of the PMOS transistor PT121-1 and the supply line of the on signal TRON; In the second peak hold circuit 100-2, the rectifying element 120-2 is replaced with a PMOS.
Instead of providing an attenuation (reset) circuit with the transistor PT121-2, a PMOS transistor PT12-2 is used.
Load signal LD between gate and drain of 121-2
Circuit 151-2 turned on / off by PMOS, PMOS
The gate of the transistor PT121-2 and the ON signal TRO
A switch circuit 152-2 that is turned on / off by a load signal LD between the supply line N and the buffer line BUF100c
Output and rectifier element operational amplifier side node ND102-2
And a switch circuit 152-4 which is turned on / off by the load signal LD between the output of the operational amplifier 110-2 and the node ND102-2. The load / hold switching circuit 150-2 is provided.

Next, the operation according to the fifth embodiment will be described with reference to the timing chart of FIG. Also in this case, similarly to the fourth embodiment, the input signal IN is applied to the first and second peak hold circuits 100-1 and 100-2.
Are supplied in parallel to the non-inverting input terminals (+) of the operational amplifiers 110-1 and 110-2.

In the first peak hold circuit 100-1, a reset signal is supplied inactive during the hold period, so that the switch circuit 151-1 is kept on and the switch circuit 152-1 is kept off. This allows
The PMOS transistor PT121-1 functions as a rectifier, and performs a peak hold operation of an input signal. Then, as shown in FIGS. 11A and 11B, the input signal I
Each time a pulse of N is input, a reset signal RST is actively supplied for a predetermined period, so that the switch circuit 151-1 is kept off and the switch circuit 152-1 is kept on. Thereby, the PMOS transistor PT121
-1 functions as a transfer gate, and the peak hold circuit 1
In 00-1, the output terminal of the operational amplifier 110-1 and the non-inverting input terminal (-) are short-circuited, so that it operates not as a peak hold circuit but as a voltage follower circuit. That is, the hold node ND101-11 is held at the voltage of the input signal at the time of reset release (reset).

On the other hand, the second peak hold circuit 100-
2, the load signal LD is supplied inactive during the hold period, and the switch circuits 151-1 and 154-
2 is on, the switch circuits 152-2 and 153-
2 is kept off. As a result, the PMOS transistor PT121-1 functions as a rectifier, and a peak hold operation of the input signal is performed. And FIG.
As shown in (a) and (c), the load signal LD is actively supplied for a predetermined period, the switch circuits 151-1 and 154-2 are kept in the off state, and the switch circuits 152-2 and 153-2 are kept in the on state. Is done. This allows P
The MOS transistor PT121-1 functions as a transfer gate, and the output side of the operational amplifier 110-2 is disconnected. The hold voltage output of the first peak hold circuit 100-1 is transferred to the node ND102-2 via the buffer BUF100. The signal is transmitted to the hold node ND101-2 via the PMOS transistor PT121-2 as a transfer gate.

According to the fifth embodiment, the fourth embodiment
The same effect as that of the embodiment can be obtained.

Sixth Embodiment FIG. 12 is a block diagram showing a peak detection circuit according to a sixth embodiment of the present invention. FIG. 13 is a circuit diagram showing a specific configuration example of the peak detection circuit. The specific circuit shown in FIG. 13 according to the twelfth embodiment is for the upper limit value.

The sixth embodiment is different from the first embodiment in that the rectifying element of the peak hold circuit 100 is constituted by the NMOS transistor NT121, and receives the clamp reference voltage Vcramp during the hold period. The voltage on the output side (node ND102) of the operational amplifier 110 of the rectifier element 120 is set to a voltage between the analog ground and the hold voltage, or a voltage from the analog ground (hereinafter referred to as a voltage higher than the voltage at which the output of the operational amplifier 110 during the hold period is cut off). , This voltage is called the intermediate voltage) V
A clamp circuit 400 for clamping to a clamp and a voltage between the analog ground and the hold voltage, or an intermediate voltage from the analog ground that is lower than the voltage at which the operational amplifier output has swung during the hold period, and the rectifier element 120 of the peak hold circuit Is provided as a voltage VP-well to the bulk terminal of the NMOS transistor NT121 constituting the intermediate voltage generator, a clamp reference voltage Vcramp to the clamp circuit 400, and an attenuation voltage VRST to the switched capacitor 200. Further, the pull-up circuit 600 is connected to the output node of the operational amplifier 110.

As shown in FIG. 13, the clamp circuit 400 includes an operational amplifier 410, a resistor 420, and a rectifier 430.

Non-inverting input terminal (+) of operational amplifier 410
Is connected to the supply line of the clamp reference voltage Vcramp,
The inverting input terminal (-) is connected to the amplifier node ND102 of the rectifier 120.

The resistance element 420 is connected between the output of the operational amplifier 110 and the node ND102. The resistance element 420 is not limited to a resistor. For example, in the case of an upper limit peak hold circuit, as shown in FIG.
It can be constituted by a PMOS transistor PT421. In the case of the lower limit peak hold circuit, the NMOS
It can be constituted by a transistor. Further, the PMOS transistor PT421 as a resistance element also functions as a saturation element, and its gate is grounded.

In the case of the peak hold circuit for the upper limit value, the rectifying element 430 is connected from the output side of the operational amplifier 410 to a connection point (hereinafter, referred to as a node) ND401 between the node ND102 and the inverting input terminal (−) of the operational amplifier 410. They are connected in the forward direction. Note that in the case of the lower limit peak hold circuit, the connection is made so as to be forward from the node ND401 toward the output side of the operational amplifier 410. In the circuit of FIG. 13, the rectifying element 430 includes a PMOS transistor PT431 whose drain and gate are connected to the node ND401 and whose source is connected to the output of the operational amplifier 410.

The intermediate voltage generating circuit 500 includes an operational amplifier 501 having a connection between an inverting input terminal (-) and an output terminal and functioning as a so-called voltage follower;
Resistance elements 502 and 503 and a PMOS transistor P connected in series between a supply line of _DD and ground GND.
T501, the inverter INV501, and the resistance element 50
2, a resistance element 504 connected between the connection point of 503 and the non-inverting input terminal (+) of the operational amplifier 501, the non-inverting input terminal (+) of the operational amplifier 501, and the ground line GND.
And a stabilizing capacitance element C501 connected between the two. Then, the PMOS transistor PT501
Of the power-on signal PWO supplied at a high level during the power-on period via the inverter INV201
N supply lines.

In the intermediate voltage generating circuit 500, the voltage V
RST (VP-well, Vcramp) is the resistance element 502,5
The voltage VRST is set at the connection point between the resistance elements 502 and 503 by resistance division during the power-on period, and this voltage is supplied from the operational amplifier 501 as a voltage follower to the clamp circuit 40.
0, NMOS transistor NT as rectifying element 120
121 bulk terminal and switched capacitor 20
0 is supplied.

A PMOS transistor PT601 and a resistor R60 are connected between the supply line of the power supply voltage V _DD and the output of the operational amplifier 110 of the peak hold circuit 100.
1 are connected in series. The gate of the PMOS transistor PT601 is connected to the supply line of the power-on signal PWON supplied at a high level during the power-on period via the inverter INV601.

FIG. 14 is a circuit diagram showing a specific configuration example of the operational amplifier 501 of the intermediate voltage generating circuit 500. Since the operational amplifier 410 of the clamp circuit 400 and the operational amplifier 110 of the peak hold circuit 100 can be configured in the same manner, the configuration of the operational amplifier 501 will be described here as an example.

The operational amplifier 501 includes PMOS transistors PT701 to PT712 and an NMOS transistor NT7.
01 to NT707, a resistor R701, a phase compensation capacitance element C701, and serially connected inverters INV701 and IN constituting an input stage of a power-on signal PWON.
V702.

PMOS transistors PT701 to PT7
05, PT711 are connected to the supply line of the power supply voltage V _DD and the NMOS transistors NT702 to NT702 are connected.
5, NT707, and PMOS transistor PT70
The drain 9 is connected to the supply line of the power supply voltage V _SS . Further, the output of the inverter INV701 constituting the input stage of the power-on signal PWON is connected to the gate of the PMOS transistor PT710 and the NMOS transistor NT.
702 is connected to the gate. The output of the inverter INV702 is the PMOS transistor PT70
1, PT705 and PT712 and the gates of NMOS transistors NT701 and NT706.

The drain of the PMOS transistor PT701 is connected to the PMOS transistors PT702, PT703, P
The gate of T704 is connected to the source of the PMOS transistor PT706 and its substrate. The drain of the PMOS transistor PT702 is connected to the source of the PMOS transistor PT706, and the drain of the PMOS transistor PT706 is connected to its own gate and the drains of the NMOS transistors NT701 and NT703. The source of the NMOS transistor NT701 is connected to the drain of the NMOS transistor NT702 and NM.
It is connected to the gate of the OS transistor NT703. These PMOS transistors PT701, PT7
02, PT706 and NMOS transistor NT70
1 to NT703 constitute a bias circuit BIC701.

The drain of the PMOS transistor 703 is connected to the sources of the PMOS transistors PT707 and PT708, the gate of the PMOS transistor PT707 forms an inverting input terminal (-), and the gate of the PMOS transistor PT708 forms the non-inverting input terminal (+).
Is configured. The drain of the PMOS transistor PT707 is the drain of the NMOS transistor NT704, and the drains of the NMOS transistors NT704 and NT70
5 gates. Then, the PMOS transistor PT708 and the NMOS transistor NT70
5 are connected to each other, and these connection points are
An NMOS transistor connected to an output node ND701 via a phase compensation resistor R701 and a capacitor C701 connected in series with the gate of the OS transistor PT709 and an NMOS transistor NT706 as a transfer gate It is connected to the gate of NT707. PM connected as above
OS transistors PT703, PT707, PT708
The NMOS transistors NT704 and NT705 form a differential amplifier circuit DFA701.

The drain of the PMOS transistor PT704 is connected to the source of the PMOS transistor PT709 and its substrate. The PMOS transistors PT704 and PT709 constitute a so-called source follower SSF701. The drain of the PMOS transistor PT704 and the PMOS transistor P704
The connection point with the source of T709 is PM as a transfer gate.
The drain of the PMOS transistor PT705 via the OS transistor PT710 and the PMOS transistor PT705
711 gate and PMOS transistor PT71
2 sources. The drain of the PMOS transistor PT712 is connected to the NMOS transistor NT.
707 is connected to the gate. Then, the drain of the PMOS transistor PT711 and the drain of the NMOS transistor NT707 are connected to each other to
D701 is configured. P connected as above
A so-called push-up output stage PPL is formed by the MOS transistor PT711 and the NMOS transistor NT707.
701 is constituted.

The operational amplifier 501 having such a configuration
When the power-on signal PWON is supplied at an active high level, the output of the inverter INV701 goes low and the output of the inverter INV702 goes high, so that the PMOS transistor PT70
3 becomes conductive, and the differential amplifier circuit DFA 701 becomes active.

In this state, the PMOS transistor PT708 as the non-inverting input terminal (+) of the operational amplifier 501
, For example, is supplied with a voltage VRST, and its output is fed back to a PMOS transistor PT707 as an inverting input terminal (-). Thereby, the operational amplifier 501
Functions as a voltage follower, the bulk voltage of the NMOS transistor NT121 as the rectifying element 120 is held at the intermediate voltage VP-well, the intermediate voltage VCamp is supplied to the operational amplifier 410 of the clamp circuit 400, and the clamp operation is performed. In addition, the switched capacitor 20
0 is supplied with the intermediate voltage VRST and the hold node ND
The operation of attenuating the potential of 101 is performed.

That is, the peak detection circuit PD100e
Then, the output of the operational amplifier 110 is clamped by the clamp circuit 400 to the clamp reference voltage Vcramp. Thus, when the input signal IN passes the peak value, the operational amplifier 1
10, the clamp reference voltage Vcramp (= VR
ST) is output. In addition, the rectifying element 120
The intermediate voltage is supplied to the bulk terminal of the NMOS transistor NT121 as a reference.

Therefore, according to the sixth embodiment,
It is possible to reduce a leak current that hinders the hold voltage holding characteristic of the peak hold circuit. As a result, without using a capacitor for holding the hold voltage externally, several Hz
The peak hold circuit that can support input signals as low as several tens of Hz can be manufactured in a semiconductor integrated circuit by a simple CMOS process, and as a result, the system can be downsized, the number of parts can be reduced, and the cost of the device can be reduced. is there. Further, since the pull-up circuit 600 is connected to the output of the operational amplifier 110 of the peak hold circuit 100, there is an advantage that the input voltage range of the peak hold circuit capable of holding and outputting can be expanded according to the input amplitude.

For example, the switched capacitor 20
0 switch circuit can be configured using MOS transistors, but in this case, the hold node ND1
01 may be directly connected, so that the voltage of the bulk terminal is also preferably maintained at the intermediate voltage supplied from the intermediate voltage generating circuit 500.

In many cases, the hold node of the peak hold circuit is directly connected to the minus input terminal of the operational amplifier. In a bipolar transistor type operational amplifier, leakage current flows from the input terminal.
It is disadvantageous to apply it to a peak hold circuit that handles low frequencies. In a gate-type MOS operational amplifier, since the leakage current from the input terminal is very small, there is no problem in applying it to a peak hold circuit that handles a low frequency. FIG. 14 shows a configuration example of a gate-input MOS operational amplifier for such a reason. Needless to say, any other operational amplifier may be used as long as leakage current from an input terminal does not matter.

Seventh Embodiment FIG. 15 is a block diagram showing a peak detection circuit according to a seventh embodiment of the present invention. FIG. 16 is a circuit diagram showing a specific configuration example of the peak detection circuit. The specific circuit shown in FIG. 16 according to the seventh embodiment is for the lower limit.

The seventh embodiment differs from the fourth embodiment in the following points. That is, the first difference is that the rectifying element 120-1 of the first peak hold circuit 100-1 is configured by the PMOS transistor PT121-1 and receives the reset signal RST to set the hold node ND101-1 to a predetermined voltage. VRST (or A
Switch circuit 141-connected to the supply line of the GND).
1 comprising a PMOS transistor PT141-1 and N
A reset signal RST is applied to the gates of the MOS transistor NT421-1 and the PMOS transistor PT141-1.
And the second peak hold circuit 100-
2 rectifier element 120-2 is connected to a PMOS transistor PT1.
21-2, and receives the load signal LD and changes the hold node ND101-2 to the buffer BUF100.
-1 connected to the output of PMO
The NMOS transistor NT421-2 and the PMOS transistor P are constituted by the S transistor PT141-2.
The load signal LD is supplied to the gate of T141-2.

The second difference is that the clamp reference voltage Vcram
In response to p, the operational amplifier 110 of the rectifier 120-1 during the hold period of the first peak hold circuit 100-1
Is clamped to the intermediate voltage Vcramp from the analog ground rather than the voltage between the analog ground and the hold voltage or the voltage at which the output of the operational amplifier 110-1 is cut off during the hold period. The clamp circuit 400-1a receives the clamp reference voltage Vcramp, and receives the rectifier element 120- during the hold period of the second peak hold circuit 100-2.
2 on the output side of the operational amplifier 110-2 (node ND102
-2) the voltage between the analog ground and the hold voltage, or the operational amplifier 11 during the hold period.
Clamp circuit 4 that clamps the output voltage of 0-2 to the intermediate voltage Vcramp from the analog ground rather than the voltage that has passed.
00-2a.

The third difference is that a voltage between the analog ground and the hold voltage or an intermediate voltage from the analog ground which is higher than the voltage at which the operational amplifier output is swung during the hold period is generated. Rectifier element 120-of peak hold circuits 100-1 and 100-2
PMOS transistor PT1 forming the first transistor 120-2
21-1, bulk terminal of PT121-2, and reset and load PMOS transistor PT141-
1, the voltage Vwell is supplied to the bulk terminal of PT141-2, the voltage is supplied to the clamp circuits 400-1a and 400-2a as the clamp reference voltage or Vcramp, and the reset (attenuation) PMOS transistor PT141-1 is provided.
Intermediate voltage generating circuit 5 for applying as a voltage for attenuation to the source of the circuit
00a.

The fourth difference is that the first and second
Are connected to the outputs of the operational amplifiers 110-1 and 110-2 of the peak hold circuits 100-1 and 100-2, respectively.

As shown in FIG. 16, the clamp circuit 400-1a has an operational amplifier 410-1 and a gate connected to a reset signal RST supply line.
1 connected to the output of node 1 and node ND 102-1
Resistance element 4 composed of MOS transistor NT421-1
20-1 and a rectifying element 430-1 including an NMOS transistor NT431-1 whose gate is connected to the node ND102-1. Operational amplifier 4
10-1 non-inverting input terminal (+) is the clamp reference voltage V
The inverting input terminal (-) is connected to the amplifier side node ND102-1 of the rectifying element 120-1. The rectifying element 430-1 is connected in a forward direction from the node ND102-1 toward the output side of the operational amplifier 410-1.

As shown in FIG. 16, the clamp circuit 400-2a has an operational amplifier 410-2, a gate connected to the supply line of the load signal LD, and a connection between the output of the operational amplifier 410-2 and the node ND102-2. NMO
Resistance element 420 including S transistor NT421-2
-2, and a rectifying element 430-2 including an NMOS transistor NT431-2 having a gate connected to the node ND102-2. Operational amplifier 410
-2 non-inverting input terminal (+) is the clamp reference voltage Vcram
p, and the inverting input terminal (-) is connected to the amplifier-side node ND102-2 of the rectifying element 120-2. The rectifying element 430-2 is connected to the node ND.
It is connected so that it may become a forward direction from 102-2 to the output side of operational amplifier 410-2.

The intermediate voltage generating circuit 500a includes an operational amplifier 501 connected as an inverting input terminal (-) and an output terminal, which functions as a so-called voltage follower, and a series connection between a supply line of the power supply voltage V _DD and the ground GND. The connected resistance elements 502 and 503 and the NMOS transistor NT501, the resistance element 504 connected between the connection point of the resistance elements 502 and 503 and the non-inverting input terminal (+) of the operational amplifier 501, and the non-inverting of the operational amplifier 501 It comprises a stabilizing capacitance element C501 connected between the input terminal (+) and the ground line GND. And NM
The gate of the OS transistor NT501 is connected to a supply line for a power-on signal PWON supplied at a high level during the power-on period. In addition, the operational amplifier 501
And pull-up circuit 600 also provides power-on signal P
WON is received at a high level, and is kept in the operating state.

In this intermediate voltage generation circuit 500a, the voltage VRST (VN-well, Vcramp) is
The voltage VRST is set at the connection point of the resistance elements 502 and 503 by the resistance division during the power-on period, and this voltage is supplied from the operational amplifier 501 as a voltage follower to the clamp circuit 40 during the power-on period.
0-1a, 400-2a, PM as rectifying element 120
The bulk terminals of the OS transistors PT121-1 and PT121-2 and the PMOS transistor PT141-
1, PT 141-2 are supplied to the bulk terminals.

The pull-down circuit 600-1a includes a resistor R601-1 connected between the output of the operational amplifier 110-1 and the ground line, and a gate connected to the power-on signal PW.
NMOS transistor N connected to ON supply line
It is composed of T601-1.

The pull-down circuit 600-2a includes a resistor R601-2 connected between the output of the operational amplifier 110-2 and the ground line, and a gate connected to the power-on signal PW.
NMOS transistor N connected to ON supply line
It is composed of T601-2.

FIG. 17 is a circuit diagram showing a specific configuration example of the operational amplifier 501 of the intermediate voltage generating circuit 500a.
Since the operational amplifier 410 of the clamp circuit 400 and the operational amplifier 110 of the peak detection circuit 100 can be similarly configured, the configuration of the operational amplifier 501 will be described here.

The operational amplifier 501 includes PMOS transistors PT801 to PT810 and an NMOS transistor NT8.
01 to NT809, a resistor R801, a phase compensation capacitance element C801, and serially connected inverters INV801 and IN constituting an input stage of a power-on signal PWON.
V802.

PMOS transistors PT801 to PT8
04, PT810 are connected to the supply line of the power supply voltage V _DD , and the NMOS transistors NT 802 to NT 802 are connected.
5, NT808, and PMOS transistor PT80
The drain 8 is connected to the supply line of the power supply voltage V _SS . The output of the inverter INV801 constituting the input stage of the power-on signal PWON is connected to the gate of the PMOS transistor PT809 and the NMOS transistor NT.
802, NT807, and NT808. The output of the inverter INV802 is PMO
It is connected to the gate of the S transistor PT801 and the gates of the NMOS transistors NT801 and NT806.

The drain of the PMOS transistor PT801 is connected to the PMOS transistors PT802, PT803, P
The gate of T804, the source of the PMOS transistor PT805, and its substrate are connected. The drain of the PMOS transistor PT802 is connected to the source of the PMOS transistor PT805, and the drain of the PMOS transistor PT805 is connected to its own gate and the drains of the NMOS transistors NT801 and NT803. The source of the NMOS transistor NT801 is connected to the drain of the NMOS transistor NT802 and NM.
It is connected to the gate of the OS transistor NT703. These PMOS transistors PT801, PT8
02, PT805 and NMOS transistor NT80
1 to NT803 constitute a bias circuit BIC801.

The drain of the PMOS transistor 803 is connected to the sources of the PMOS transistors PT806 and PT807, the gate of the PMOS transistor PT806 forms an inverting input terminal (-), and the gate of the PMOS transistor PT807 forms the non-inverting input terminal (+).
Is configured. The drain of the PMOS transistor PT806 is the drain of the NMOS transistor NT804, and the NMOS transistors NT804 and NT80
5 gates. Then, the PMOS transistor PT807 and the NMOS transistor NT80
5 are connected to each other, and these connection points are
An NMOS transistor connected to an output node ND801 via a phase compensation resistor R801 and a capacitor C801 connected in series with the gate of the OS transistor PT808 and an NMOS transistor NT806 as a transfer gate It is connected to the source of NT807, the drain of NMOS transistor NT808, and the gate of NMOS transistor NT809. The PMOS transistors PT803, PT806, PT807 and NMOS connected as described above
The transistors NT804 and NT805 form a differential amplifier circuit DFA801.

The drain of the PMOS transistor PT804 is connected to the source of the PMOS transistor PT808 and its substrate. A so-called source follower SSF801 is constituted by the PMOS transistors PT804 and PT808. Further, the drain of the PMOS transistor PT804 and the PMOS transistor P804
The connection point with the source of T808 is PM as a transfer gate.
The drain of the NMOS transistor NT807 and the gate of the PMOS transistor PT810 are connected via the OS transistor PT809. Also, NMO
The source of the S transistor NT807 is connected to the drain of the NMOS transistor NT808. And
Drain of PMOS transistor PT810 and NMOS
The output nodes ND801 are configured by connecting the drains of the transistors NT809. The PMOS transistors PT810 and NMO connected as described above
A so-called push-pull output stage PPL801 is constituted by the S transistor NT809.

The operational amplifier 501 having such a configuration
In this case, when the power-on signal PWON is supplied at an active high level, the output of the inverter INV801 goes low and the output of the inverter INV802 goes high, so that the PMOS transistor PT80
3 becomes conductive, and the differential amplifier circuit DFA 801 becomes active.

In this state, the PMOS transistor PT807 as the non-inverting input terminal (+) of the operational amplifier 501
, For example, is supplied with a voltage VRST, and its output is fed back to a PMOS transistor PT806 as an inverting input terminal (-). Thereby, the operational amplifier 501
Function as voltage followers, and PMOS transistors PT121-1, PT12 as rectifying elements 120
1-2, the bulk voltage of the PMOS transistors PT141-1 and PT141-2 for reset and load is held at the intermediate voltage VN-well, and the clamp circuit 150
Is supplied as a reference voltage Vcramp to the operational amplifier 151, and a clamping operation is performed. Also reset (decay)
The source of the PMOS transistor PT141-1 is supplied as an attenuation voltage.

Since the peak detection operation including the damping action of the hold node according to the seventh embodiment is performed in the same manner as the operation described in the fourth embodiment, the description is omitted here.

According to the seventh embodiment, the fourth embodiment
As in the first embodiment, a peak detection circuit can be realized that can quickly respond to an increase in the amplitude of the input signal, and can also handle a signal with a noise component or another signal component immediately after the input signal, Also, by making the peak hold circuit work like a sample hold circuit,
In the sample-and-hold circuit, the direction of the temporal change of the hold voltage due to the leak current that does not know whether to go to the V _DD side or the V _SS side is always directed toward the V _SS side when the voltage of the upper limit is held. When the voltage of the lower limit value is held, it is possible to design such that the voltage always fluctuates toward the _VDD side. Therefore, there is an advantage that a peak detection circuit in which a malfunction does not easily occur can be realized without using a high resistance. In addition, a leakage current of a rectifying element that hinders a hold voltage holding characteristic of the peak hold circuit and a reset MOS transistor are provided. Can be reduced, the reset operation can be ensured when a reset signal is input, and even if it takes time for the output of the operational amplifier 110 to return to the intermediate potential, the hold voltage is reversed. Can be prevented.

The peak hold circuits 100-1 and 100-1
Since the pull-down circuits 600-1a and 600-2a are connected to the outputs of the operational amplifiers 110-1 and 100-2 of 00-2, the input voltage range of the peak hold circuit capable of holding output in accordance with the input amplitude is expanded. There are advantages that can be.

Eighth Embodiment FIG. 18 is a circuit diagram showing an eighth embodiment of the peak detection circuit according to the present invention. The circuit according to the eighth embodiment is for the lower limit.

The eighth embodiment is different from the seventh embodiment in that the load signal LD is supplied to the gate of the NMOS transistor NT421-2 as the resistance element 152 of the clamp circuit 400-2a. Clamp assist voltage generation circuit 44 for level-shifting the output voltage of operational amplifier 410-2 of clamp circuit 400-2b
0, the voltage generated by the clamp assist voltage generation circuit 440 is supplied to the gate of the NMOS transistor NT421-2 as the voltage Vcr_as to assist the clamping function, and the intermediate voltage generation circuit 500b is connected to the operational amplifier 501 and the resistance element. 502 to 504, the NMOS transistor NT501, and the capacitor C501, an operational amplifier 505, resistance elements 506, 50
7, switch circuits 508 and 509, and capacitive element C5
02, and the intermediate voltage VRST from the operational amplifier 501 is supplied to the bulk terminals of the PMOS transistors PT121-1 and PT141-1 of the first peak hold circuit 100-1;
It is supplied to the source of the PMOS transistor PT141-1 and the clamp 400-1a,
RST, PHOLD2, and (a · VRST + b · P
The intermediate voltage set to (HOLD2) / (a + b) is applied to the bulk terminal of the NMOS transistor NT421-2 of the second peak hold circuit 100-2 and the clamp circuit 4.
00-2b and the second peak hold circuit 1
The bulk terminal of the PMOS transistor PT141-2 of 00-2 is connected to the output line of the hold voltage PHOLD1 of the first peak hold circuit 100-1.

FIG. 19 is a circuit diagram showing a configuration example of the clamp assist voltage generation circuit 440. As shown in FIG. 19, the clamp assist voltage generation circuit 440 includes a supply line of the power supply voltage V _DD and a signal Vcr_ of the operational amplifier 410-2.
out, the resistance elements 442, 441 and the NMOS transistor NT44 connected in series
1, NT442. The NMOS transistor NT441 is diode-connected with its gate and drain connected to each other.
Gate 2 is connected to the supply line of the power-on signal PWON.

This clamp assist voltage generation circuit 440
When the power-on signal PWON is supplied at an active high level, the NMOS transistor NT442 is turned on, and the signal Vcr_as can be output. Then, the operational amplifier 4 is connected from the connection point of the resistance elements 441 and 442.
A signal signal Vcr_as obtained by level-shifting the output signal of 10-2 by resistance division is the NM as the resistance element 420-2.
This is supplied to the gate of the OS transistor NT421-2.

Other operations in this case are the same as those in FIG. 16, and a detailed description thereof will be omitted.

As in the eighth embodiment, the following effects can be obtained by employing the configuration of 400-2b in which the clamp assist voltage generation circuit 440 is connected to the clamp circuit 400-2a. That is, in the other clamp circuit, during the clamp operation, the output of the operational amplifier 110-2 of the peak hold circuit and the output of the operational amplifier 410-2 of the clamp circuit 400-2b are connected between the resistance element 420-2 of the clamp circuit 400-2b. However, they will compete. That is, the operational amplifier 1 of the peak hold circuit
The output of 10-2 interferes with the clamping operation,
There is a problem that a large output current flows between the two operational amplifiers 110-2 and 410-2. Especially Vcramp = H
In order to perform OLD, it is necessary to perform a clamping operation in a wide voltage range, and this problem becomes an obstacle.

The output of the operational amplifier 410-2 fluctuates greatly as the current for clamping through the rectifying element increases. When this voltage is fed back to the gate input of the NMOS transistor NT421-2 used as the resistance element 420-2 of the clamp circuit 400-2b through the clamp assist voltage generation circuit 440, the current capability on the resistance element side during the clamp operation is reduced. Thus, there is no need to supply a very large current to the rectifying element side for clamping, and the above problem can be solved.

In the intermediate voltage generating circuit 500b, the voltage of the voltage VRST is set by the ratio between the resistance values of the resistance elements 502 and 503. When the switch circuit 508 is on and the switch circuit 509 is off, Vcramp = VR
In ST, the switch circuit 508 is off, and the switch circuit 5
When 09 is ON, Vcramp = PHOLD2. When both of the switch circuits 508 and 509 are on, Vcramp = (a · VRST + b · HOLD) /
(A + b) is output. Note that a and b are the resistance elements 50
2,503,506 and the reciprocal of the combined resistance value and the resistance element 50
7 is the reciprocal of the resistance value.

As described above, the clamp reference voltage Vcramp is set to VRST, PHOLD2, and (a · VRST + b ·
With the configuration that can be set to (PHOLD2) / (a + b), the clamp reference voltage during the hold period can be made closer to the hold voltage, and Vcramp = VRST
Compared to FIG. 16, the voltage difference between the hold node and the node on the amplifier side of the rectifying element can be further reduced from about 1/2 to less even when the amplitude of the input signal is large. is there.

According to the eighth embodiment, the first embodiment
In addition to the effects of the seventh embodiment, when a signal obtained by level-shifting the output of the clamp circuit is input, the voltage range that can be clamped can be expanded, and even when the amplitude of the input signal is large, the hold can be performed. The voltage difference between the node and the node on the amplifier side of the rectifying element can be further reduced.

Ninth Embodiment FIGS. 20 and 21 are block diagrams showing an example in which the peak detection circuit according to the present invention is applied as a part of a semiconductor integrated circuit for servo control.

FIG. 20 shows signals recorded on a recording medium 901 in a magnetic disk or magnetic tape reproducing apparatus.
The motor 90 is used for reading by a sensor 902 such as a head.
3 shows a portion of a semiconductor integrated circuit 910 including a voltage amplifying stage and a voltage control unit that servo-controls a rotation speed of a magnetic disk and a running speed of a magnetic tape under a load of 3, for example.
FIG. 21 is a block diagram showing an example of a semiconductor integrated circuit (one-chip microcomputer) 910 including an amplifier circuit used for the above control.

The peak detection circuit according to the present invention is used as a peak voltage detection circuit 911 in the semiconductor integrated circuit 910 of FIG. 21 to detect the signal amplitude at the output of the amplification stage. If the amplitude of the analog input signal input from the sensor 902 varies greatly, the signal amplitude at the output of the amplification stage also varies, so that the judgment by the comparator cannot be performed correctly. Circuit feedback is performed based on the voltage detected by the peak detection circuit, or A
After being digitized once by the D converter 916, the CPU 91
By giving feedback softly in 9
The gain of the amplification stage 912 and the reference voltage of the comparator are adjusted by the gain control circuit 913 and the comparator reference voltage control circuit 9.
15 to set the optimum one, so that the digital signal can be correctly converted.

In the case where the data is digitized by the AD converter 916 and the feedback is applied in a software manner, the AD converter
There is an advantage that the peak voltage only needs to be held during the period of reading in step 6. However, since the AD converter must be controlled in synchronization with the input signal, the AD converter having a general-purpose analog input such as an AV microcomputer can be used. Further, it is difficult to perform such processing because the control program becomes complicated. On the other hand, when applying feedback in a circuit, it does not become very complicated in terms of software, but it is necessary to hold the peak voltage at least during the period from the input of a peak to the input of the next peak. A peak detection circuit with good performance is required. By applying the peak detection circuit according to the present invention, it is possible to cope with such strict specifications.

In each of the above embodiments, a simple C
The purpose is to realize a peak detection circuit that can be used at a low frequency even with the MOS process structure as it is by devising it from a circuit point of view. By
Furthermore, it does not deny realizing a peak detection circuit having good hold voltage holding characteristics. Further, it is not denied that the case where the semiconductor device is not a complete semiconductor integrated circuit but partially includes discrete components.

[0154]

As described above, according to the present invention,
It is possible to attenuate the hold voltage of the peak hold circuit constituting the peak detection circuit without using a high resistance. Moreover, depending on how the reset is applied, a certain percentage of the hold voltage is attenuated according to the amplitude of the input signal regardless of the fluctuation of the cycle of the input signal, or the resistance is attenuated as the input signal cycle becomes longer, such as a resistor. It is possible to Further, it is possible to reduce a change with time of the hold voltage due to a leak current of the peak detection circuit, and a semiconductor integrated circuit can realize a peak detection circuit capable of handling a low-frequency signal having a variation in amplitude and cycle. Furthermore, a peak detection circuit that can quickly respond to an increase in the amplitude of the input signal and that can also handle a signal having a noise component or another signal component immediately after the input signal can be realized. Further, a peak detection circuit in which a malfunction does not easily occur can be realized without using a high resistance.

Therefore, a peak hold circuit capable of responding to an input signal as low as several Hz to several tens of Hz without using an external capacitor for holding a hold voltage is provided by a simple CMOS.
It can be manufactured in a semiconductor integrated circuit by a process, so that the size of the system can be reduced and the number of components can be reduced. Therefore, the cost of the apparatus can be reduced. In addition, by incorporating it in a semiconductor integrated circuit, there is an advantage that a higher function can be achieved, for example, a function of shortening a test time or adding a power down function.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a peak detection circuit according to the present invention.

FIG. 2 is a diagram illustrating a specific circuit configuration of an upper limit value peak detection circuit according to the first embodiment.

FIG. 3 is a timing chart for explaining the operation of the circuit of FIG. 2;

FIG. 4 is a circuit diagram showing a second embodiment of a peak detection circuit according to the present invention.

FIG. 5 is a timing chart for explaining the operation of the lower limit value peak detection circuit of FIG. 4;

FIG. 6 is a circuit diagram showing a third embodiment of a peak detection circuit according to the present invention.

FIG. 7 is a block diagram showing a fourth embodiment of the peak detection circuit according to the present invention.

FIG. 8 is a diagram illustrating a specific circuit configuration of an upper limit value peak detection circuit according to a fourth embodiment.

9 is a timing chart for explaining the operation of the upper limit value peak detection circuit of FIG. 8;

FIG. 10 is a circuit diagram showing a fifth embodiment of a peak detection circuit according to the present invention.

FIG. 11 is a timing chart for explaining the operation of the peak detection circuit of FIG. 10;

FIG. 12 is a block diagram showing a peak detection circuit according to a sixth embodiment of the present invention.

FIG. 13 is a diagram illustrating a specific circuit configuration of an upper limit value peak detection circuit according to a sixth embodiment.

FIG. 14 is a circuit diagram showing a specific configuration example of an operational amplifier applied to a peak hold circuit, an intermediate voltage generation circuit, and a clamp circuit which constitute the upper limit value peak detection circuit.

FIG. 15 is a block diagram showing a seventh embodiment of the peak detection circuit according to the present invention.

FIG. 16 is a diagram illustrating a specific circuit configuration of a lower limit value peak detection circuit according to a seventh embodiment.

FIG. 17 is a circuit diagram showing a specific configuration example of an operational amplifier applied to a peak hold circuit, an intermediate voltage generation circuit, and a clamp circuit that constitute a lower limit value peak detection circuit.

FIG. 18 is a circuit diagram showing an eighth embodiment of a peak detection circuit according to the present invention.

FIG. 19 is a circuit diagram illustrating a configuration example of a clamp assist voltage generation circuit in FIG. 18;

FIG. 20 is a block diagram showing an example in which the peak hold circuit according to the present invention is applied as a part of a semiconductor integrated circuit for servo control.

FIG. 21 is a block diagram showing an example in which the peak detection circuit according to the present invention is applied as a part of a semiconductor integrated circuit for servo control.

FIG. 22 is a block diagram illustrating a first configuration example of a conventional peak detection circuit.

FIG. 23 is a block diagram illustrating a second configuration example of a conventional peak detection circuit.

FIG. 24 is a circuit diagram showing a configuration example of a conventional peak hold circuit for an upper limit.

FIG. 25 is a circuit diagram showing a configuration example of a conventional lower limit value peak hold circuit.

FIG. 26 is a circuit diagram illustrating a configuration example of a sample and hold circuit.

FIG. 27 is a diagram showing operation waveforms of a peak detection circuit constituted by a peak hold circuit.

FIG. 28 is a diagram showing operation waveforms of a peak detection circuit constituted by a peak hold circuit.

FIG. 29 is a diagram showing operation waveforms of a peak detection circuit including a peak hold circuit and a sample hold circuit.

[Explanation of symbols]

PD100, PD100a to PD100f ... peak detection circuits, 100, 100-1, 100-2, 100-1
a, 100-2a: peak hold circuit, 110: operational amplifier, 120: rectifying element, 130: holding capacitive element, 140-1, 140-2: attenuation (reset) circuit,
150-1: reset / hold switching circuit, 150-2
... load / hold switching circuit, 200 ... switched capacitor, 300 ... voltage source, 400, 400-1a, 40
0-2a, 400-2b: Clamp circuit, 440: Clamp assist voltage generation circuit, 500, 500a, 500
b: intermediate voltage generating circuit, 600: pull-up circuit, 60
0-1a, 600-2a ... pull-down circuit

Claims (46)

[Claims] 1. A peak hold circuit having a capacitor connected to a hold node and holding a peak value of an input signal, an attenuation capacitor connected to a voltage source having a predetermined level, and the attenuation capacitor And a switch circuit for switching between a connection state and a non-connection state with the hold node of the peak hold circuit. 2. The peak detection circuit according to claim 1, wherein the capacitance value of the attenuation capacitance element is set to a value smaller than the capacitance value of the hold capacitance element, and the switching operation of the switch circuit is repeatedly performed. 3. The peak detection circuit according to claim 1, wherein said voltage source supplies a voltage obtained by subtracting a fixed voltage from a hold voltage of said peak hold circuit. 4. The peak detection circuit according to claim 1, wherein said switched capacitor has a second switch circuit for switching between a connection state and a non-connection state between said attenuation capacitance element and said voltage source. 5. The peak detection circuit according to claim 2, wherein the switched capacitor has a second switch circuit for switching between a connection state and a non-connection state between the attenuation capacitor and the voltage source. 6. The peak detection circuit according to claim 3, wherein the switched capacitor has a second switch circuit for switching between a connection state and a non-connection state between the attenuation capacitor and the voltage source. 7. The peak detection circuit according to claim 4, wherein a switch circuit for switching a connection state with the hold node is switched to a connection state while the second switch circuit is in a non-connection state. 8. An operational amplifier for signal input having two input terminals, a signal is input to one input terminal, and the potential of a hold node is fed back to the other input terminal, and one terminal is connected to the signal input operational amplifier. A peak hold circuit including a hold rectifier connected to the output side of the operational amplifier and the other end connected to the hold node, a hold capacitor connected to the hold node, and a voltage source having a predetermined level A peak detection circuit comprising: an attenuating capacitive element connected to the peak hold circuit; and a switched capacitor including a switch circuit for switching a connection / disconnection state between the attenuating capacitive element and a hold node of the peak hold circuit. 9. The peak detection circuit according to claim 8, wherein a capacitance value of the attenuation capacitance element is set to a value smaller than a capacitance value of the hold capacitance element, and the switching operation of the switch circuit is repeatedly performed. 10. The peak detection circuit according to claim 8, wherein said voltage source supplies a voltage obtained by subtracting a fixed voltage from a hold voltage of said peak hold circuit. 11. The peak detection circuit according to claim 8, wherein the switched capacitor has a second switch circuit that switches between a connection state and a non-connection state between the attenuation capacitor and the voltage source. 12. The peak detection circuit according to claim 9, wherein said switched capacitor has a second switch circuit for switching between a connection state and a non-connection state between said attenuation capacitor and said voltage source. 13. The peak detection circuit according to claim 10, wherein said switched capacitor has a second switch circuit for switching between a connection state and a non-connection state between said attenuation capacitance element and said voltage source. 14. The peak detection circuit according to claim 11, wherein a switch circuit for switching a connection state with the hold node is switched to a connection state while the second switch circuit is in a non-connection state. 15. A voltage at an output node of the operational amplifier for signal input of the rectifier element is higher than a voltage between analog ground and a hold voltage or a voltage at which an output of the operational amplifier for signal input during a hold period is cut off. 9. The peak detection circuit according to claim 8, further comprising voltage adjusting means for adjusting the voltage to a voltage higher than the analog ground. 16. A reference voltage corresponding to a voltage between the analog ground and a voltage between the analog ground and the hold voltage or a voltage from the output of the operational amplifier for signal input during the hold period. 16. The peak detection circuit according to claim 15, further comprising a clamp circuit that receives the signal and clamps a voltage at an output node of the signal input operational amplifier to the reference voltage. 17. The clamp circuit has two input terminals. One input terminal is supplied with the reference voltage, and the other input terminal is supplied with a voltage of an output node of the operational amplifier for signal input. And a connection point between the output node of the signal input operational amplifier and the other input terminal of the clamp operational amplifier, the other terminal side of which is connected to the output side of the operational amplifier for clamp. 17. The peak detection circuit according to claim 16, further comprising: 18. The peak detection circuit according to claim 17, wherein the clamp circuit has a resistance element connected between the output side of the operational amplifier for signal input and the other input terminal of the operational amplifier for clamp. 19. The peak detection circuit according to claim 18, wherein the resistance element of the clamp circuit is constituted by an insulated gate field effect transistor having a gate supplied with a control signal. 20. The control signal is a signal for holding the insulated gate field effect transistor in a conductive state during a hold period, and holding the insulated gate field effect transistor in a non-conductive state when the hold node is reset. 20. The peak detection circuit according to claim 19, wherein: 21. The rectifying element is connected in a forward direction from an output node side of the signal input operational amplifier toward a hold node, and a pull-up circuit is connected to an output node of the signal input operational amplifier. 9. The peak detection circuit according to claim 8, wherein? 22. The rectifying element is connected in a forward direction from a hold node toward an output node of the operational amplifier for signal input, and a pull-down circuit is provided at an output node of the operational amplifier for signal input. 9. The peak detection circuit according to claim 8, wherein the peak detection circuit is connected. 23. The rectifying element, wherein one terminal side is connected to the output side of the operational amplifier for signal input, the other terminal side is connected to the hold node, and one of the one terminal side or the other terminal side and a gate are connected. Is connected to a bulk terminal of the insulated gate field effect transistor as the rectifying element, an intermediate voltage between analog ground and a hold voltage, or a signal input operation during the hold period. 9. The peak detection circuit according to claim 8, further comprising an intermediate voltage generation circuit that supplies an intermediate voltage from the analog ground rather than a voltage at which the output of the amplifier has been cut off. 24. The rectifier element, wherein one terminal side is connected to the output side of the signal input operational amplifier, the other terminal side is connected to the hold node, and either the one terminal side or the other terminal side is connected to the gate. Is connected to a bulk terminal of the insulated gate field effect transistor as the rectifying element, an intermediate voltage between analog ground and a hold voltage, or a signal input operation during the hold period. 17. The peak detection circuit according to claim 16, further comprising: an intermediate voltage generation circuit that supplies an intermediate voltage from an analog ground rather than a voltage at which the output of the amplifier has cut off, and supplies the intermediate voltage to the clamp circuit as the reference voltage. 25. A switch circuit for switching a connection state of the switched capacitor with the hold node is constituted by an insulated gate field effect transistor, and a bulk terminal of the insulated gate field effect transistor of the switch circuit is held from analog ground. 9. The peak detection circuit according to claim 8, further comprising: an intermediate voltage generating circuit for supplying an intermediate voltage between the voltages or an intermediate voltage from the analog ground rather than a voltage at which the output of the operational amplifier for signal input during the hold period is cut off. 26. The rectifier element, wherein one terminal side is connected to the output side of the signal input operational amplifier, the other terminal side is connected to the hold node, and either one of the one terminal side or the other terminal side and a gate are connected. And a switch circuit for switching a connection state of the switched capacitor with the hold node is formed of an insulated gate field effect transistor, and an insulated gate as the rectifying element. The intermediate voltage between analog ground and the hold voltage, or the voltage at which the output of the operational amplifier for signal input during the hold period is applied to the bulk terminal of the field-effect transistor and the bulk terminal of the insulated gate field-effect transistor of the switch circuit. While supplying an intermediate voltage from the analog ground rather than Peak detection circuit according to claim 8, further comprising a voltage generating circuit. 27. The rectifier element has one terminal side connected to the output side of the operational amplifier for signal input, the other terminal side connected to the hold node, and one of the one terminal side or the other terminal side and a gate. And a switch circuit for switching a connection state of the switched capacitor with the hold node is formed of an insulated gate field effect transistor, and an insulated gate as the rectifying element. The intermediate voltage between analog ground and the hold voltage, or the voltage at which the output of the operational amplifier for signal input during the hold period is applied to the bulk terminal of the field effect transistor and the bulk terminal of the insulated gate field effect transistor of the reset circuit. Supply an intermediate voltage from the analog ground Moni, claim 16 and an intermediate voltage generating circuit for supplying the intermediate voltage as the reference voltage to the clamping circuit
The described peak detection circuit. 28. A first signal input operational amplifier having two input terminals, a signal being input to one input terminal, and a potential of a first hold node being fed back to the other input terminal. A first hold rectifying element having a terminal connected to the output of the first signal input operational amplifier and the other terminal connected to the first hold node; and a terminal connected to the first hold node. A first holding capacitive element;
A first peak hold circuit having an attenuating means for attenuating or resetting the hold voltage at the time of resetting; and a first peak hold circuit having two input terminals, the signal being input to one input terminal, and the other input terminal being connected to the other input terminal. A second signal input operational amplifier to which the potential of the second hold node is fed back, one terminal connected to the output side of the second signal input operational amplifier, and the other terminal connected to the second hold node , A second hold capacitor connected to the second hold node, and at least a first peak held by the first peak hold circuit. And a second peak hold circuit having load means capable of transmitting the potential of the first hold node of the peak hold circuit to the second hold node. Road. 29. The attenuating means includes a first switch for connecting the first hold node to a reset potential at the time of reset, and the load means sets the second hold node to the first potential at the time of loading. 29. The peak detection circuit according to claim 28, comprising a second switch connected to the first hold node of the peak hold circuit. 30. The first peak hold circuit according to claim 1, wherein:
Has one terminal connected to the output of the first signal input operational amplifier, the other terminal connected to the first hold node, and gated to either the one terminal or the other terminal. Is connected, a first insulated gate field effect transistor that functions as a rectifying element, and one terminal side of the second rectifying element of the second peak hold circuit is used for the second signal input. A second insulated gate that is connected to the output side of the operational amplifier, connected to the other terminal side to the second hold node, and functions as a rectifying element when the gate is connected to either the one terminal side or the other terminal side The attenuating means is connected to either one terminal or the other terminal of the first insulated gate field effect transistor during the hold period. Are connected to each other to function as a first rectifying element, and at the time of resetting the first hold node, one of the one terminal side or the other terminal side and the gate are kept in a non-connected state, and the first A reset that keeps the insulated gate field effect transistor conductive
The load means is configured as a second rectifier element by connecting one of the terminal and the other terminal of the second insulated gate field effect transistor to a gate during a hold period. Function, and at the time of loading, either the one terminal side or the other terminal side and the gate are kept in a disconnected state,
A load for holding the second insulated gate field effect transistor in a conductive state and connecting a first hold node of the first peak hold circuit to one terminal of the second insulated gate field effect transistor; 29. The peak detection circuit according to claim 28, comprising a hold switching circuit. 31. The attenuating means is constituted by a first switch for connecting the first hold node to a reset potential at the time of reset. The second rectifying element of the second peak hold circuit has one terminal side. When the second hold node is connected to the output side of the second signal input operational amplifier, the other terminal side is connected, and the gate is connected to one of the one terminal side or the other terminal side, the rectifier element is used. The load means comprises a second rectifier which connects one of a terminal side and another terminal side of the insulated gate type field effect transistor to a gate during a hold period. The element functions as an element, and at the time of loading, either the one terminal side or the other terminal side and the gate are kept in a non-connected state, and the insulated gate type electrode is held. A load / hold switching circuit for holding the effect transistor in a conductive state and connecting a first hold node of the first peak hold circuit to one terminal of the insulated gate field effect transistor. 28. The peak detection circuit according to 28. 32. The first peak hold circuit according to claim 1, wherein
Has one terminal connected to the output of the first signal input operational amplifier, the other terminal connected to the first hold node, and gated to either the one terminal or the other terminal. Is connected, and is constituted by an insulated gate field effect transistor functioning as a rectifying element, and the attenuating means is connected to either one terminal side or the other terminal side of the insulated gate field effect transistor during a hold period. Connecting the gate with the gate to function as a first rectifying element, and when resetting the first hold node, holding either the one terminal side or the other terminal side and the gate in a non-connected state; And a reset / hold switching circuit for holding the conduction type field effect transistor in a conductive state. Second peak detecting circuit according to claim 28, wherein being configured by a switch connected to the first holding node of the first peak hold circuit Rudonodo. 33. In at least one of the first peak hold circuit and the second peak hold circuit, a voltage of an output side node of the signal input operational amplifier of the rectifier element is set between an analog ground and a hold voltage. 29. The peak detection circuit according to claim 28, further comprising voltage adjustment means for adjusting the voltage or the voltage of the output of the operational amplifier for signal input during the hold period to a voltage higher than the analog ground voltage. 34. The voltage adjusting means, comprising: a reference voltage corresponding to a voltage between analog ground and a hold voltage, or a voltage from analog ground to a voltage higher than the voltage at which the output of the operational amplifier for signal input during the hold period is cut off. 34. The peak detection circuit according to claim 33, further comprising a clamp circuit that clamps the voltage of the output node of the operational amplifier for signal input to the reference voltage. 35. The clamp circuit has two input terminals, one of the input terminals is supplied with the reference voltage, and the other input terminal is supplied with a voltage of an output node of the operational amplifier for signal input. And a connection point between the output node of the signal input operational amplifier and the other input terminal of the clamp operational amplifier, the other terminal side of which is connected to the output side of the operational amplifier for clamp. 35. The peak detection circuit according to claim 34, further comprising: a rectifier connected to the peak detection circuit. 36. The peak detection circuit according to claim 35, wherein the clamp circuit has a resistance element connected between the output side of the operational amplifier for signal input and the other input terminal of the operational amplifier for clamp. 37. The peak detection circuit according to claim 36, wherein the resistance element of the clamp circuit comprises an insulated gate field effect transistor having a gate supplied with a control signal. 38. The control signal is a signal for holding the insulated gate field effect transistor in a conductive state during a hold period, and holding the insulated gate field effect transistor in a non-conductive state when the hold node is reset. The peak detection circuit according to claim 37. 39. The peak detection circuit according to claim 37, wherein the control signal is a clamp assist voltage signal set according to an output voltage of the operational amplifier for clamping. 40. In at least one of the first peak hold circuit and the second peak hold circuit, the rectifier element is in a forward direction from the output node side of the signal input operational amplifier toward the hold node. 29. The peak hold circuit according to claim 28, wherein a pull-up circuit is connected to the output node of the operational amplifier for signal input. 41. In at least one of the first peak hold circuit and the second peak hold circuit, the rectifier element is in a forward direction from a hold node toward an output node side of the signal input operational amplifier. 29. The peak detection circuit according to claim 28, wherein a pull-down circuit is connected to an output node of the operational amplifier for signal input. 42. In at least one of the first peak hold circuit and the second peak hold circuit, the rectifying element has one terminal connected to the output of the signal input operational amplifier and the other terminal connected to the other terminal. The hold node is connected, and the gate is connected to either the one terminal side or the other terminal side, and the gate is connected. The bulk terminal of the insulated gate field effect transistor as the rectifier element is connected to the analog terminal. 29. The peak according to claim 28, further comprising: an intermediate voltage generating circuit for supplying an intermediate voltage between the ground and the hold voltage or an intermediate voltage from the analog ground rather than a voltage at which the output of the operational amplifier for signal input during the hold period is cut off. Detection circuit. 43. In at least one of the first peak hold circuit and the second peak hold circuit, the rectifier has one terminal connected to the output of the signal input operational amplifier and the other terminal connected to the other terminal. The hold node is connected, and the gate is connected to either the one terminal side or the other terminal side, and the gate is connected. The bulk terminal of the insulated gate field effect transistor as the rectifying element is connected to the analog terminal. An intermediate voltage between the ground and the hold voltage, or an intermediate voltage from the analog ground which is higher than the voltage at which the output of the operational amplifier for signal input during the hold period has run out, and the intermediate voltage is supplied to the clamp circuit as the reference voltage. 35. The peak detection according to claim 34, further comprising an intermediate voltage generation circuit for supplying a voltage. Road. 44. The attenuating means is constituted by an insulated gate field effect transistor comprising a first switch connecting the first hold node to a reset potential at the time of reset, and the loading means is configured to load the first hold node at the time of loading. And an insulated gate field effect transistor comprising a second switch connecting the second hold node to the first hold node of the first peak hold circuit, wherein at least one of the attenuating means and the load means is insulated gate type. Intermediate voltage between analog ground and hold voltage to the bulk terminal of the field effect transistor, or
29. The peak detection circuit according to claim 28, further comprising an intermediate voltage generation circuit that supplies an intermediate voltage from an analog ground to a voltage at which the output of the operational amplifier for signal input during the hold period has fallen. 45. In at least one of the first peak hold circuit and the second peak hold circuit, the rectifier has one terminal connected to the output of the signal input operational amplifier and the other terminal connected to the other terminal. The hold node is connected, the gate is connected to one of the one terminal side or the other terminal side, and the gate is connected. The attenuating means is configured to reset the first hold node at the time of reset. An insulated gate field effect transistor comprising a first switch connected to a reset potential, wherein the load means connects the second hold node to a first hold node of the first peak hold circuit during loading. The insulated gate field effect transistor comprising a second switch to be connected; An intermediate voltage between analog ground and a hold voltage to a bulk terminal of the insulated gate field effect transistor as an element and a bulk terminal of the insulated gate field effect transistor of at least one of the attenuation means or the load means, or during a hold period. 29. The peak detection circuit according to claim 28, further comprising: an intermediate voltage generation circuit that supplies an intermediate voltage from an analog ground rather than a voltage at which the output of the signal input operational amplifier has cut off. 46. In at least one of the first peak hold circuit and the second peak hold circuit, the rectifier has one terminal connected to the output of the signal input operational amplifier and the other terminal connected to the other terminal. The hold node is connected, the gate is connected to one of the one terminal side or the other terminal side, and the gate is connected. The attenuating means is configured to reset the first hold node at the time of reset. An insulated gate field effect transistor comprising a first switch connected to a reset potential, wherein the load means connects the second hold node to a first hold node of the first peak hold circuit during loading. The insulated gate field effect transistor comprising a second switch to be connected; An intermediate voltage between analog ground and a hold voltage to a bulk terminal of the insulated gate field effect transistor as an element and a bulk terminal of the insulated gate field effect transistor of at least one of the attenuating means and the loading means, or during a hold period. 35. An intermediate voltage generating circuit according to claim 34, further comprising: an intermediate voltage generating circuit that supplies an intermediate voltage from the analog ground rather than a voltage at which the output of the signal input operational amplifier has run off and supplies the intermediate voltage to the clamp circuit as the reference voltage. Peak detection circuit.