KR20110025338A - Redundancy control circuit for semiconductor memory apparatus - Google Patents

Redundancy control circuit for semiconductor memory apparatus Download PDF

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Publication number
KR20110025338A
KR20110025338A KR1020090083351A KR20090083351A KR20110025338A KR 20110025338 A KR20110025338 A KR 20110025338A KR 1020090083351 A KR1020090083351 A KR 1020090083351A KR 20090083351 A KR20090083351 A KR 20090083351A KR 20110025338 A KR20110025338 A KR 20110025338A
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KR
South Korea
Prior art keywords
redundancy
signal
word line
drive control
control signal
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Application number
KR1020090083351A
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Korean (ko)
Inventor
최원준
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090083351A priority Critical patent/KR20110025338A/en
Publication of KR20110025338A publication Critical patent/KR20110025338A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring

Abstract

PURPOSE: A redundancy control circuit for a semiconductor memory apparatus is provided to perform exactly a test by activating and deactivating a redundancy word line regardless of variation of PVT(Process Voltage Temperature). CONSTITUTION: A redundancy driving control signal generating unit(31) generates a redundancy driving control signal. The redundancy driving control signal is activated during a period of inputting an active command. A redundancy word line controller(32) generates a redundancy word line enable signal. A word line clear signal is deactivated during an active operation period. A word line clear signal is activated during a precharge operation period.

Description

REDUNDANCY CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and to a technique for controlling redundancy word lines.

In general, a compression test is used to shorten the test time of the semiconductor memory device. In the Compress Test mode, a plurality of memory banks are simultaneously accessed to perform a corresponding test operation.

1 is a configuration diagram of a redundancy control circuit of a conventional semiconductor memory device.

Referring to FIG. 1, a redundancy control circuit of a semiconductor memory device includes a redundancy drive control signal generator 11 and a redundancy word line controller 12.

The redundancy drive control signal generator 11 is composed of an inverter INV1 and a NAND gate NAND1. The redundancy drive control signal generator 11 generates a redundancy drive control signal TM_XREDB by negatively multiplying the inverted signal of the compression test signal TST_COMPB and the redundancy select signal XRED_SEL. For reference, the Compress Test accesses and tests a plurality of memory banks simultaneously, resulting in an unused bank address channel. Therefore, the redundancy select signal XRED_SEL is applied through this redundant bank address channel and is used as a signal for selectively testing the redundancy logic or the normal logic.

In addition, the redundancy word line control unit 12 may include pull-up driving units MP1 and MP2 for pull-up driving the first node N1 under the control of the redundancy driving control signal TM_XREDB and the word line clear signal WLCLRB. Pull-down driving units MN1 and MN2 for pull-down driving the first node N1 under the control of the pulse signal ACTP and the redundancy enable signal XHIT, and a first under the control of the redundancy driving control signal TM_XREDB. The latch units INV3 and NAND2 for latching signals output from the node N1 are configured. The active pulse signal ACTP is activated at the input point of the active command and pulses for a predetermined time, and the redundancy enable signal XHIT is output from the fuse set to determine whether the redundancy word line is used. In this example, it is assumed that the redundancy enable signal XHIT is activated.

FIG. 2 is a timing diagram illustrating an operation of the redundancy control circuit of FIG. 1.

Referring to the timing diagram of FIG. 2 and FIG. 1, the main operations of the redundancy control circuit will be described.

The first timing diagram 21 of FIG. 2 illustrates a case in which an internal operation is normally performed. Referring to the first timing diagram 21, the normal operation state is as follows.

Since the redundancy drive control signal TM_XREDB is activated by the redundancy select signal XRED_SEL applied through the extra bank address channel, it is activated based on the active command ACT (REDUNDANCY).

When the redundancy driving control signal TM_XREDB is activated at the low level by applying the active command ACT (REDUNDANCY), the first node N1 is pulled down by the word line clear signal WLCLRB and the active pulse signal ACTP. do. Accordingly, the finally output redundancy word line activation signal BS_HIT is activated at a high level, and the redundancy word line is accessed by the redundancy word line activation signal BS_HIT.

Next, when the precharge command PCG is applied, the word line clear signal WLCLRB is activated at a low level, so that the first node N1 is pulled up. Accordingly, the finally output redundancy word line activation signal BS_HIT is deactivated to a low level, and access to the redundancy word line is stopped by the redundancy word line activation signal BS_HIT.

Next, when the active command ACT (NORMAL) is applied again to test the normal word line instead of the redundancy word line, the redundancy word line activation signal BS_HIT is inactive so that the corresponding normal word line of the selected memory bank is accessed. do.

Meanwhile, the second timing diagram 22 of FIG. 2 illustrates a case where an internal operation is abnormally performed. An abnormal operation state will be described with reference to the second timing diagram 22.

The second timing diagram 22 illustrates a case where the redundancy drive control signal TM_XREDB is delayed due to the influence of PVT (Process Voltage Temperature) change.

When the redundancy driving control signal TM_XREDB is activated at the low level by applying the active command ACT (REDUNDANCY), the first node N1 is pulled down by the word line clear signal WLCLRB and the active pulse signal ACTP. do. Accordingly, the finally output redundancy word line activation signal BS_HIT is activated at a high level, and the redundancy word line is accessed by the redundancy word line activation signal BS_HIT.

Next, when the precharge command PCG is applied, the word line clear signal WLCLRB is activated at a low level. At this time, since the redundancy driving control signal TM_XREDB is delayed, the first node N1 cannot be pulled-up and the redundancy word line activation signal BS_HIT is continuously maintained at a high level.

In this state, when the active command ACT (NORMAL) is applied again to test the normal word line, the redundancy word line activation signal BS_HIT is continuously activated so that the redundancy word line is accessed instead of the normal word line. do.

As illustrated, the redundancy drive control signal TM_XREDB and the word line clear signal WLCLRB are both generated based on the active command as a common reference, and therefore, the redundancy word line is accessed when the redundancy drive control signal TM_XREDB is delayed. As soon as the normal wordline is inaccessible, the test pattern is constrained.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above conventional problem, and an object thereof is to provide a redundancy control circuit of a semiconductor memory device capable of efficiently controlling redundancy word lines.

According to an aspect of the present invention for achieving the above technical problem, a redundancy drive control signal generation unit for generating a redundancy drive control signal that is activated during the input period of the active command in the redundancy test state; And a redundancy word line control unit configured to generate a redundancy word line activation signal in response to the word line clear signal, the redundancy drive control signal and the active pulse signal, which are deactivated in the active operation period and activated in the precharge operation period. A control circuit is provided.

The redundancy control circuit of the semiconductor memory device according to the present invention can activate / deactivate the redundancy word line at a required time irrespective of a change in the process voltage temperature (PVT), thereby enabling a more accurate test operation. In addition, test efficiency can be improved by eliminating the additional internal operation to perform continuous tests.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In general, logic signals and binary data values of a circuit are classified into high level (high level) or low level (low level) corresponding to voltage level, and may be expressed as '1' and '0', respectively. . In addition, it is defined and described that it may additionally have a high impedance (Hi-Z) state and the like.

3 is a configuration diagram of a redundancy control circuit of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the redundancy control circuit of the semiconductor memory device includes a redundancy drive control signal generator 31 for generating a redundancy drive control signal TM_XREDB that is activated during an input period of an active command in a redundancy test state, and an active operation tool. Redundancy word line controller for generating a redundancy word line activation signal BS_HIT in response to the word line clear signal WLCLRB, the redundancy drive control signal TM_XREDB, and the active pulse signal ACTP, which are deactivated and activated during the precharge operation period. (32) is provided.

For reference, since the active command is input in response to the clock signal, the active command is input for one cycle (1 * tck) or half cycle (0.5 * tck) of the clock signal. The active pulse signal ACTP is a signal that is activated at an input point of an active command and pulses for a predetermined time. In general, the active pulse signal ACTP is an internal signal that is activated during the input period of the active command.

The detailed configuration and main operations of the redundancy control circuit of the semiconductor memory device configured as described above are as follows.

The redundancy drive control signal generation unit 31 generates a redundancy drive control signal TM_XREDB by logically combining the compression test signal TST_COMPB, the redundancy select signal XRED_SEL, and the active pulse signal ACTP. For reference, the Compress Test accesses and tests a plurality of memory banks simultaneously, resulting in an unused bank address channel. Therefore, the redundancy select signal XRED_SEL is applied through this redundant bank address channel and used as a signal for selectively testing the redundancy logic or the normal logic. In addition, in the present embodiment, the redundancy drive control signal TM_XREDB is generated by using the logical sum of the auto refresh pulse signal AREFP and the active pulse signal ACTP. The refresh operation is performed including the active operation. The internal operation by the auto refresh pulse signal AREFP and the active pulse signal ACTP is the same. Therefore, the description of logics NOR1 and INV2 for ORing the active pulse signal ACTP and the auto refresh pulse signal AREFP will be omitted, and only the internal operation by the active pulse signal ACTP will be described.

The logic unit constituting the redundancy drive control signal generation unit 31 includes the negative logic unit NAND1 for inputting the inverted signal of the compression test signal TST_COMPB and the redundancy select signal XRED_SEL, and the active pulse signal ACTP. ) And the redundancy drive control signal TM_XREDB as input to the negative logic sum means NOR2, which inputs the compression test signal TST_COMPB, and the output signals of the negative logic means NAND1, and the negative logic sum means NOR2. It consists of logical sum means (NOR3, INV3) for output.

The redundancy word line control unit 32 further includes a pull-up driving unit MP1 and MP2 for pull-up driving the first node N1 in response to the redundancy drive control signal TM_XREDB and the word line clear signal WLCLRB. Pull-down driving units MN1 and MN2 for pull-down driving the first node N1 in response to the pulse signal ACTP and the redundancy enable signal XHIT, and the first node in response to the redundancy driving control signal TM_XREDB. And latch portions INV5 and NAND5 for latching the signal output from N1). The redundancy enable signal XHIT is a signal that is output from the fuse set to determine whether or not the redundancy word line is used. In the present embodiment, it is assumed that the redundancy enable signal XHIT is activated.

4 is a timing diagram illustrating an operation of the redundancy control circuit of FIG. 3.

Referring to the timing diagram of FIG. 4 and FIG. 3, the main operations of the redundancy control circuit of the semiconductor memory device will be described below.

Since the redundancy drive control signal TM_XREDB is activated by the redundancy select signal XRED_SEL and the active pulse signal ACTP applied through the extra bank address channel, the redundancy drive control signal TM_XREDB is activated during the input period of the active command ACT (REDUNDANCY). It is a pulse signal.

When the redundancy driving control signal TM_XREDB is activated at the low level by applying the active command ACT (REDUNDANCY), the first node N1 is pulled down by the word line clear signal WLCLRB and the active pulse signal ACTP. do. Accordingly, the finally output redundancy word line activation signal BS_HIT is activated at a high level, and the redundancy word line is accessed by the redundancy word line activation signal BS_HIT.

Next, when the precharge command PCG is applied, the word line clear signal WLCLRB is activated at a low level, so that the first node N1 is pulled up. Accordingly, the finally output redundancy word line activation signal BS_HIT is deactivated to a low level, and access to the redundancy word line is stopped by the redundancy word line activation signal BS_HIT.

Next, when the active command ACT (NORMAL) is applied again to test the normal word line instead of the redundancy word line, the redundancy word line activation signal BS_HIT is inactive so that the corresponding normal word line of the selected memory bank is accessed. do.

Both of the redundancy driving control signal TM_XREDB and the word line clear signal WLCLRB are signals generated based on the common command as a common reference, and the redundancy word line activation signal BS_HIT is generated according to the control of the two signals. In the present embodiment, since the redundancy drive control signal TM_XREDB is a short pulse type signal that is activated during the input period of the active command, the redundancy word line control unit 32 may be internal even if the signal is delayed due to the change of PVT (Process Voltage Temperature). It does not affect the operation.

In the above, the specific description was made according to the embodiment of the present invention. Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

For example, although not directly related to the technical spirit of the present invention, in order to explain the present invention in more detail, an embodiment including an additional configuration may be illustrated. In addition, the configuration of an active high or an active low for indicating an activation state of a signal and a circuit may vary according to embodiments. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as necessary. In addition, the configuration of the logic gate may be changed as necessary to implement the same function. That is, the negative logical means, the negative logical sum means, etc. may be configured through various combinations such as NAND GATE, NOR GATE, and INVERTER. Such a change of circuit is too many, and since the change can be easily inferred by a person skilled in the art, the enumeration thereof will be omitted.

1 is a configuration diagram of a redundancy control circuit of a conventional semiconductor memory device.

FIG. 2 is a timing diagram illustrating an operation of the redundancy control circuit of FIG. 1.

3 is a configuration diagram of a redundancy control circuit of a semiconductor memory device according to an embodiment of the present invention.

4 is a timing diagram illustrating an operation of the redundancy control circuit of FIG. 3.

* Explanation of symbols for the main parts of the drawings

31: redundancy drive control signal generator

32: redundancy word line control

In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.

Claims (6)

A redundancy drive control signal generation unit for generating a redundancy drive control signal activated during an input period of an active command in a redundancy test state; And Redundancy word line controller for generating a redundancy word line activation signal in response to the word line clear signal, the redundancy drive control signal and the active pulse signal, which are deactivated in the active operation section and activated in the precharge operation section. Redundancy control circuit of a semiconductor memory device having a. The method of claim 1, And the active command is input in response to a clock signal. The method according to claim 1 or 2, And the active pulse signal is a signal that is activated at an input point of the active command and pulses for a predetermined time. The method of claim 1, The redundancy drive control signal generator, And a logic unit for generating a redundancy drive control signal by logically combining a compression test signal, a redundancy select signal, and the active pulse signal. The method of claim 4, wherein The logic unit, Negative logic means for inputting an inverted signal of the compression test signal and the redundancy select signal; Negative logic means for inputting the active pulse signal and the compression test signal; And And redundancy means for outputting the redundancy drive control signal by inputting the negative logic means and the output signal of the negative AND logic means. The method of claim 1, The redundancy word line control unit, A pull-up driver configured to pull-up a first node in response to the redundancy drive control signal and the word line clear signal; A pull-down driver configured to pull-down the first node in response to the active pulse signal and the redundancy enable signal; And And a latch unit for latching a signal output from the first node in response to the redundancy drive control signal.
KR1020090083351A 2009-09-04 2009-09-04 Redundancy control circuit for semiconductor memory apparatus KR20110025338A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9373385B2 (en) 2014-03-28 2016-06-21 SK Hynix Inc. Semiconductor memory and method for operating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9373385B2 (en) 2014-03-28 2016-06-21 SK Hynix Inc. Semiconductor memory and method for operating the same

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