KR20110019321A - Semiconductor package and method of forming the same - Google Patents

Abstract

PURPOSE: A semiconductor package and a method for manufacturing the same are provided to reduce the horizontal/vertical size of the semiconductor package by omitting the formation of a dam preventing the flow of an under-fill resin. CONSTITUTION: A first substrate(202) includes a first surface part located in a first region(A) and a second surface part located in a second region(B). The first region is formed in a region between a semiconductor chip(150) and a second connection terminal(105b). The surface roughness of the first surface part is different from that of the second surface part. A first semiconductor chip is mounted on the first substrate. A first protective film fills a region between the first semiconductor chip and the first substrate.

Description

Semiconductor package and method of manufacturing the same {Semiconductor package and method of forming the same}

The present invention relates to a semiconductor package and a method of manufacturing the same.

With the development of the electronic industry, there is an increasing demand for high functional, high speed, and miniaturization of electronic components. In order to cope with this trend, current semiconductor mounting technologies have been emerging as a method of stacking and mounting a plurality of semiconductor chips on one semiconductor substrate or stacking a package on a package. However, this method has problems such as thickening of the entire package or inferior bonding stability. In addition, various studies have been conducted in the semiconductor package in order to prevent moisture or contamination from the outside.

The problem to be solved by the present invention is to provide a semiconductor package that can reduce the size and at the same time improve the stability.

The problem to be solved by the present invention is to provide a method for manufacturing a semiconductor package that can reduce the size and improve the stability.

In accordance with another aspect of the present invention, a semiconductor package includes a first region and a second region, and includes a first surface portion located in the first region and a first surface portion located in the second region. And a first substrate comprising a second surface portion to be connected, wherein the surface roughness of the first surface portion is different from that of the second surface portion.

The semiconductor package may include a first semiconductor chip mounted on the first substrate; And a first passivation layer filling the first semiconductor chip and the first substrate, wherein the first region may be adjacent to an end portion of the first semiconductor chip.

The surface roughness of the first surface portion is preferably smaller than the surface roughness of the second surface portion.

The first substrate may further include a third region overlapping the first semiconductor chip and a third surface portion disposed in the third region and connected to the first surface portion, wherein the surface roughness of the third surface portion is The surface roughness of the first and second surface portions may be different. The surface roughness of the third surface portion may be preferably smaller than the surface roughness of the first surface portion.

The second region may have at least one closed curve shape surrounding the first semiconductor chip or a bar shape disposed to be adjacent to one end of the first substrate. The first region may have a 'U' shape or a closed curve shape.

According to an example, the first substrate may include a substrate body including a first surface and a second surface; A first connecting terminal disposed on the first surface of the substrate body; And a first insulating film covering the first surface of the substrate body and exposing the first connection terminal, wherein the first insulating film has the first surface portion and the first and second portions, respectively, in the first region and the second region. It may include a second surface portion.

The first connection terminal may be disposed in the third region, and the semiconductor chip may be mounted on the first connection terminal.

The first substrate may further include a second connection terminal disposed on the first surface of the substrate body and spaced apart from the first connection terminal, wherein the second connection terminal is disposed in the second area and It may be exposed by the first insulating film.

According to another example, the semiconductor package may include: a second substrate disposed on the first substrate and electrically connected to the first substrate through the second connection terminal; And a second semiconductor chip mounted on the second substrate.

According to another example, the first substrate may include a third connecting terminal disposed on the second surface of the substrate body; And a second insulating film covering the second surface of the substrate body and exposing the third connection terminal, wherein the second insulating film has a fourth surface portion and a first surface in the first region and the second region, respectively. 5 surface portion, the surface roughness of the fourth surface portion may be different from the surface roughness of the fifth surface portion.

The semiconductor package may further include: a second semiconductor chip mounted on the third connection terminal under the first substrate; And a second passivation layer filling the second semiconductor chip and the first substrate, wherein the surface roughness of the fourth surface portion may be smaller than the surface roughness of the fifth surface portion.

Preferably the surface roughness of the third surface portion may preferably be about zero. Ra (center line average, center line average or Roughness average) of the surface roughness of the first surface portion is preferably about 0.01 to 0.5 탆, and very preferably about 0.086 탆. Rz (ten point height, ten point height) of the surface roughness of the first surface portion is preferably about 0.5 µm to 3 µm, and most preferably about 1.492 µm. The Rz value of the surface roughness of the second surface portion is preferably about 10 to 100 µm and very preferably about 18 µm.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package including a first region and a second region, wherein the first surface portion and the second region are located in the first region. Forming a substrate comprising a second surface portion connected with the first surface portion; And mounting a semiconductor chip on the substrate and forming a passivation layer filling the semiconductor chip and the substrate, wherein the second surface portion has a surface roughness different from that of the first surface portion. Form a substrate.

According to an example, the forming of the substrate may include preparing a substrate body; Forming a photosensitive insulating film on the entire surface of the substrate body; Performing an exposure process on the photosensitive insulating layer by using a gray photo mask that includes first and second portions respectively corresponding to the first region and the second region and having different light transmittances; And removing the exposed portion to form the first and second surface portions having different surface roughnesses on the photosensitive insulating layer.

According to another example, the forming of the substrate may include preparing a substrate body; Forming an insulating film on the front surface of the substrate body; And performing a first blasting process on the insulating layer in the first region. The forming of the substrate may further include performing a second blasting process on the insulating layer in the second region.

The forming of the substrate may include preparing a substrate body; Forming an insulating film on the entire surface of the substrate body; Performing a second blasting process on the insulating film in the second region; And performing a first blasting process on the first region and the insulating layer of the first region.

In the semiconductor package according to the embodiments of the present invention, the surface of the substrate has a different surface roughness for each region, so that the underfill resin solution does not invade unwanted regions when the protective film is formed. This eliminates the need for a dam or the like for preventing the flow of the underfill resin liquid. Therefore, the area occupied by structures such as dams can be excluded, thereby reducing the horizontal / vertical size of the semiconductor package and securing an area for redistribution, and at the same time, removing the semiconductor package from external moisture or contamination. The protective film which can be well protected can be formed efficiently.

1 shows a layout of a semiconductor package according to Embodiment 1 of the present invention.
FIG. 2A is a cross-sectional view taken along line II ′ of FIG. 1.
FIG. 2B is a cross-sectional view taken along line II-II ′ of FIG. 1.
FIG. 2C is an enlarged view illustrating a portion 'P' of FIG. 2A or 2B according to an embodiment of the present invention.
2D is an enlarged view illustrating a portion 'P' of FIG. 2A or 2B according to another example of the present invention.
2E is an enlarged view illustrating a portion 'P' of FIG. 2A or 2B according to another example of the present invention.
3A, 4A, 5A, and 6A are cross-sectional views sequentially illustrating a process of forming a semiconductor package having a cross section of FIG. 2A according to an example of the present invention.
3B, 4B, 5B, and 6B are enlarged views illustrating portions 'P' of FIGS. 3A, 4A, 5A, and 6A, respectively.
FIG. 4C is an enlarged view illustrating a portion 'P1' of FIG. 4B.
7A, 8A, and 9A are cross-sectional views sequentially illustrating a process of forming a semiconductor package having a cross section of FIG. 2A according to an example of the present invention.
7B, 8B, and 9B are enlarged views illustrating portions 'P' of FIGS. 7A, 8A, and 9A, respectively.
10 shows a layout of a semiconductor package according to Embodiment 2 of the present invention.
11A shows a layout of a semiconductor package according to Embodiment 3 of the present invention.
FIG. 11B is a cross-sectional view taken along the line II ′ of FIG. 11A.
12 shows a layout of a semiconductor package according to Embodiment 4 of the present invention.
13A shows a layout of a semiconductor package according to Embodiment 5 of the present invention.
FIG. 13B is a cross-sectional view taken along the line II ′ of FIG. 13A.
14 shows a layout of the semiconductor package according to the sixth embodiment of the present invention.
FIG. 15A is a cross-sectional view taken along the line II ′ of FIG. 14.
FIG. 15B is an enlarged view illustrating a portion 'P' of FIG. 15A.
16A is a cross-sectional view illustrating a process of manufacturing the semiconductor package having the cross section of FIG. 15A.
FIG. 16B is an enlarged view illustrating a portion 'P' of FIG. 16A.
17 shows a layout of the semiconductor package according to the seventh embodiment of the present invention.
18 shows a layout of a semiconductor package according to Embodiment 8 of the present invention.
19 is a sectional view of a semiconductor package according to Embodiment 9 of the present invention.
20 is a sectional view of a semiconductor package according to Embodiment 10 of the present invention.
21 is a sectional view of a semiconductor package according to Embodiment 11 of the present invention.
22 is a perspective view illustrating an electronic device having a semiconductor package according to an embodiment of the present invention.
23 is a system block diagram of an electronic device to which a semiconductor package according to an exemplary embodiment of the present invention is applied.
24 is a block diagram illustrating an example of an electronic device including a semiconductor package to which the technology of the present invention is applied.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thicknesses of the layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

<Structure Example 1>

1 shows a layout of a semiconductor package according to Embodiment 1 of the present invention. FIG. 2A is a cross-sectional view taken along line II ′ of FIG. 1. FIG. 2B is a cross-sectional view taken along line II-II ′ of FIG. 1. FIG. 2C is an enlarged view illustrating a portion 'P' of FIG. 2A or 2B according to an embodiment of the present invention.

1, 2A and 2B, the semiconductor package 400 according to Embodiment 1 of the present invention includes a substrate 200. The substrate 200 may include a first region A, a second region B, and a third region C. FIG. The third region C may include a chip mounting region (not shown). Surface roughnesses of the surface portions of the substrate 200 in the respective regions A, B, and C are different from each other. The substrate 200 includes a substrate body 100 including a first surface 100a and a second surface 100b. The substrate body 100 may be formed of, for example, a bismaleimide triazine resin, an alumina ceramic, or a glass ceramic. The substrate body 100 may include a single layer of insulating film or a plurality of layers of insulating films and conductive patterns interposed therebetween. The first connection terminal 105a and the second connection terminal 105b are disposed on the first surface 100a. The first connection terminal 105a may be disposed in the third region C. The second connection terminal 105b may be disposed in the second area B and spaced apart from the first connection terminal 105a. Third connection terminals 115 may be disposed on the second surface 100b. In the present exemplary embodiment, the third connection terminals 115 may be arbitrarily disposed regardless of the regions A, B, and C. Referring to FIG.

 The connection terminals 105a, 105b, and 115 may include, for example, copper as a conductive material. The first insulating layer 110 is disposed on the first surface 100a and exposes the first and second connection terminals 105a and 105b. The second insulating layer 120 is disposed on the second surface 100b and exposes the third connection terminals 115. The first and second connection terminals 105a and 105b may be electrically connected to the third connection terminals 115 through vias 107 penetrating through the substrate body 100. The semiconductor chip 150 may have a chip external connection terminal 155 contacting the first connection terminal 105a by a flip chip bonding method. The chip external connection terminal 155 may include a conductive bump, a solder ball, a conductive spacer, a pin grid array (PGA), and a lead grid array (LGA). ), And combinations thereof. The passivation layer 160 may be filled between the semiconductor chip 150 and the substrate 200. The protective layer 160 may be formed by curing an epoxy resin solution for underfill. The passivation layer 160 may further include silica. The passivation layer 160 is disposed to overlap the third region C under the semiconductor chip 150. The passivation layer 160 may at least partially overlap the first region A. FIG. The passivation layer 160 may cover at least a portion of the sidewall of the semiconductor chip 150. In the present embodiment, the first region A is formed between the second region B and the third region C on a plan view, and 'U' is formed along a part of an edge of the semiconductor chip 150. It may have a child shape. In FIG. 1, the second region B may be spaced apart from the mounted chip 150 by a first distance D1. An inner end portion of the second region B may be spaced apart from the second connection terminal 105b by a second distance D2. The second distance D2 may be 150 μm or more.

The first insulating layer 110 has a first surface portion 110a in the first region A, a second surface portion 110b in the second region B, and a third region C. Has a third surface portion 110c. Referring to FIG. 2C, surface roughnesses of the surface parts 110a, 110b and 110c are different from each other. Preferably, the surface roughness may not be formed in the third surface portion 110c. Ra (center line average, center line average or roughness average) of the surface roughness of the first surface portion 110a is preferably about 0.01 to 0.5 mu m, and most preferably about 0.086 mu m. Rz (ten point average roughness, ten point height) of the surface roughness of the first surface portion 110a is preferably about 0.5 µm to 3 µm, and most preferably about 1.492 µm. The Rz value of the surface roughness of the second surface portion 110b is preferably about 10 to 100 µm and very preferably about 18 µm. The semiconductor chip 150 is disposed on the substrate 200. Here, Ra means surface roughness in a direction parallel to the surface of the substrate 200 and Rz means surface roughness in a direction perpendicular to the surface of the substrate 200.

Surface roughness of the first insulating layer 110 is different for each region (A, B, C), the wettability and flowability of the epoxy resin liquid for forming the protective film 160 is different for each region (A, B, C) do. That is, the epoxy resin liquid has the best flowability because of its high wettability in the third region (C), and the lowest wettability and poor flowability in the second region (B). Due to such a difference, when the epoxy resin liquid for forming the protective film 160 is supplied, it is possible to prevent the epoxy resin liquid from flowing into an unwanted region (for example, the second region B). Thereby, the insulating epoxy resin liquid can cover the surface of the said 2nd connection terminal 105b, and can prevent that an electrical connection defect arises.

2D is an enlarged view illustrating a portion 'P' of FIG. 2A or 2B according to another example of the present invention. 2E is an enlarged view illustrating a portion 'P' of FIG. 2A or 2B according to another example of the present invention.

The cross-sectional shape of the surface portions 110a, 110b and 110c of the first insulating film 110 may have corners close to a right angle as shown in FIG. 2C or may have a smooth curved shape as shown in FIG. 2D or have a mountain shape as shown in FIG. 2E. May have Alternatively, the cross-sectional shape of the surface parts 110a, 110b, and 110c of the first insulating layer 110 may not be regular and may have a shape in which various sizes and shapes are mixed.

Although not shown, bumps such as solder balls may be attached to the third connection terminals 115.

Next, a method of manufacturing a semiconductor package according to the present embodiment will be described.

Method Example 1

3A, 4A, 5A, and 6A are cross-sectional views sequentially illustrating a process of forming a semiconductor package having a cross section of FIG. 2A according to an example of the present invention. 3B, 4B, 5B, and 6B are enlarged views illustrating portions 'P' of FIGS. 3A, 4A, 5A, and 6A, respectively. FIG. 4C is an enlarged view illustrating a portion 'P1' of FIG. 4A.

3A and 3B, a substrate body 100 having first to third regions A, B, and C and first and second surfaces 100a and 100b is prepared. A copper plate, for example, is attached to the first and second surfaces 100a and 100b of the substrate body 100 by a metal plate (not shown). The metal plate may be attached to the substrate body 100 by thermal compression or a predetermined adhesive. Through holes are formed in the metal plates and the substrate body 100 interposed therebetween by using a laser or a drill. Then, a plating layer is formed on the inner wall of the through hole and the metal plate by using a plating process. The through hole may be filled with a conductive paste material. A first mask pattern (not shown) is formed on the first surface 100a of the substrate body 100, and the first layer and the second connection terminals 105a and 105b are etched by etching the conductive layer and the metal plate using the first mask pattern as an etching mask. ). The first connection terminal 105a is formed in the first area A, and the second connection terminal 105b is formed in the second area B. As shown in FIG. A second mask pattern (not shown) is formed on the second surface 100b of the substrate body 100, and the third connection terminals 115 are formed by etching the plating layer and the metal plate using the second mask pattern (not shown) as an etching mask. The mask patterns are removed. A second insulating layer 120 is formed to cover the second surface 100b of the substrate body 100 and expose the third connection terminals 115. The second insulating layer 120 may be formed of, for example, PSR (Photo Solder Resist), BT (Bismaleimide Triazine) resin, or FR4 (Flame Resistant 4) resin. The first insulating layer 110 is formed on the entire surface of the first surface 100a of the substrate body 100. The first insulating layer 110 may be formed of, for example, a positive photosensitive material. The first insulating layer 110 may be formed by spin coating a positive photosensitive material and performing a soft baking process. 3B, the top surface of the first insulating layer 110 is flat regardless of the region. In this case, the first insulating layer 110 has a flat third surface portion 110c in the third region.

4A, 4B, and 4C, the gray photomask 180 is disposed on the substrate body 100 on which the first insulating layer 110 is formed. The gray photo mask 180 includes first to third portions 180a, 180b, and 180c corresponding to the first to third regions A, B, and C, respectively, and including different light transmittances. do. The third portion 180c has a light transmittance close to '0%' in which light is not transmitted at all. The first portion 180a may include a first sub-transmission part 180sa having a first light transmittance and a first sub-blocking part 180s1 having a light transmittance close to '0%'. The first sub transmission part 180sa and the first sub blocking part 180s1 may be alternately and repeatedly arranged. The first sub transmission part 180sa has a first width W1. The first sub blocking part 180s1 has a second width W2. The second portion 180b may include a second sub-transmission part 180sb having a second light transmittance and a second sub-blocking part 180s2 having a light transmittance close to '0%'. The second sub transmission part 180sb and the second sub blocking part 180s2 may be alternately and repeatedly arranged. The second sub-transmissive part 180sb has a third width W3. The second sub blocking part 180s2 has a fourth width W4. The first and second widths W1 and W2 may be narrower than the third and fourth widths W3 and W4. The first light transmittance may be smaller than the second light transmittance. The gray photo mask 180 may have a fourth portion 180d having a light transmittance close to '100%' for transmitting almost all light. The fourth portion 180d is disposed to overlap the first and second connection terminals 105a and 105b. The first to fourth portions 180a to 180d are attached to the transparent substrate 180e. The light 181 is irradiated using the gray photo mask 180 to perform an exposure process on the first insulating layer 110. Due to the exposure process, portions 110d exposed to light are formed in the first insulating layer 110. The higher the light transmittance, the greater the amount of light 181 reaching the first insulating film 110, thereby deepening the penetration depth of light penetrating into the first insulating film 110. This increases the thickness of the portions 110d exposed to the light. The portions 110d exposed to the light change to a state in which they are easily dissolved in the developer.

5A and 5B, portions 110d exposed to the light are removed with a developer. As a result, the opening 110h exposing the first and second connection terminals 105a and 105b is formed, and the first insulating layer 110 is formed in the first region A and the second region B. It has a first surface portion 110a and a second surface portion 110b. The surface roughness of the surface parts 110a and 110b is formed differently. The surface roughness of the second surface portion 110b is greater than the surface roughness of the first surface portion 110a. Preferably, the surface roughness of the third surface portion 110c may be about 0 μm. Ra (center line average, center line average or roughness average) of the surface roughness of the first surface portion 110a is preferably about 0.01 to 0.5 mu m, and most preferably about 0.086 mu m. Rz (ten point average roughness, ten point height) of the surface roughness of the first surface portion 110a is preferably about 0.5 µm to 3 µm, and most preferably about 1.492 µm. The Rz value of the surface roughness of the second surface portion 110b is preferably about 10 to 100 µm and very preferably about 18 µm. The first surface portion 110a may be formed in a 'U' shape along the edge of the semiconductor chip to be subsequently mounted in a plane as shown in FIG. 1. The second surface portion 110b may be formed in a closed curve shape surrounding a semiconductor chip to be subsequently mounted. However, the first surface portion 110a and the second surface portion 110b may be formed to be spaced apart from each other by a first distance D1 at one end. Thus, the substrate 200 according to the present embodiment can be completed.

6A and 6B, the semiconductor chip 150 is mounted on the substrate 200. The semiconductor chip 150 may be mounted on the substrate 200 by flip chip bonding. That is, the chip external connection terminal 155 and the first connection terminal 105a protruding from the lower portion of the semiconductor chip 150 may be fused together. Alternatively, a bump may be interposed between the chip external connection terminal 155 and the first connection terminal 105a to be electrically connected to each other. After mounting the semiconductor chip 150, the nozzle 190 is disposed on the third surface portion 110c adjacent to one side of the semiconductor chip 150. Then, the underfill resin liquid 160a for forming a protective film is supplied through the nozzle 190. The underfill resin liquid 160a flows between the semiconductor chip 150 and the substrate 200 by capillary force. At this time, since the surface roughness of the third surface portion 110c is close to 0 μm, the flow of the underfill resin liquid 160a is very good, and the space between the third surface portion 110c and the semiconductor chip 150 is rapidly increased. Is filled. In addition, although the first surface portion 110a attracts the underfill resin liquid 160a to some extent, the wettability is lower and flowability is lower than that of the third surface portion 110c, so that the underfill resin liquid 160a has the first surface. It may form on the part 110a and may not flow any more. Even if some of the underfill resin liquid 160a flows beyond the first surface portion 110a, the second surface portion 110b is large enough to prevent the flow of the underfill resin liquid 160a. The roughness of the underfill resin liquid 160a is stopped on the first surface portion 110a without flowing into the second surface portion 110b. This eliminates the need for a dam to prevent the flow of the underfill resin, and thus can eliminate the area occupied by the dam structure. As a result, the horizontal / vertical size of the semiconductor package can be reduced, and an area for rewiring can be secured, and at the same time, the semiconductor package can be protected from external moisture or contamination. Subsequently, the curing process is performed to cure the underfill resin liquid 160a to form the protective film 160 of FIGS. 2A and 2B. In addition, the first surface portion 110a has an appropriate surface roughness, thereby increasing the surface area, thereby improving adhesion between the passivation layer 160 and the first surface portion 110a. As a result, the reliability of the semiconductor package can be improved.

Method Example 2

7A, 8A, and 9A are cross-sectional views sequentially illustrating a process of forming a semiconductor package having a cross section of FIG. 2A according to an example of the present invention. 7B, 8B, and 9B are enlarged views illustrating portions 'P' of FIGS. 7A, 8A, and 9A, respectively.

7A and 7B, the second insulating film 120 is formed on the second surface 100b of the substrate body 100 as in the method embodiment 1. Similarly to the method of forming the second insulating layer 120, the opening 110h may expose the first and second connection terminals 105a and 105b on the first surface 100a of the substrate body 100. The first insulating film 110 is formed. In this step, the first insulating film 110 is formed to have a flat surface as a whole. The first insulating layer 110 is formed to have a third surface portion 110c in the third region (C).

8A and 8B, a first mask pattern 195 is formed on the first insulating layer 110 to expose the first region A and cover the second region B and the third region C. Referring to FIGS. Form. The first blast process 196 is performed using the first mask pattern 195. The first blast process 196 may be performed by, for example, spraying the substrate with a strong pressure on a mixed solution in which hard particles such as fine sand are mixed in an etchant capable of etching the substrate. Alternatively, the first blast process 196 may be performed by spraying only the fine and hard particles onto the substrate at a high pressure without an etchant. At this time, the surface roughness may be controlled by adjusting the type of the etchant and the size of the particles. A first surface portion 110a is formed in the first insulating layer 110 in the first region A by the first blast process 196.

9A and 9B, the first mask pattern 195 is removed. A second mask pattern 197 is formed on the first insulating layer 110 to expose the second region B but cover the first region A and the third region C. The second mask pattern 197 also covers an upper surface of the first connection terminal 105a. A second blast process 198 is performed using the second mask pattern 197. The second blast process 198 may proceed similarly to the first blast process 196 but with a larger particle size or with higher pressure than the first blast process 196. As a result, a second surface portion 110b is formed in the first insulating layer 110 in the second region B. The surface roughness of the second surface portion 110b may be greater than the first surface portion 110a. The second mask pattern 197 is removed. The underfill resin solution 160a may be supplied and cured in the same manner as in Example 1 to form a semiconductor package. The mask patterns 195 and 197 may be a shadow mask or a photoresist pattern.

The order of progress of the first blast process 196 and the second blast process 198 may be reversed. For example, the first blast process 196 and the second blast process 198 may overlap each other. Specifically, a second blast process 198 is first performed by exposing a second region B using the second mask pattern 197, and then the first region A and the second region B are exposed. The first blast process 196 may be performed. In this case, as shown in FIG. 9C, different surface roughnesses may overlap each other in the second region B. FIG.

During the second blast process 198, the mask patterns 195 and 197 have openings that expose the first and second connection terminals 105a and 105b so that the first and second connection terminals 105a are exposed. , 105b) may be formed to have surface roughness.

<Example 2>

10 shows a layout of a semiconductor package according to Embodiment 2 of the present invention.

Referring to FIG. 10, in the substrate 201 included in the semiconductor package 401 according to the second embodiment, a plurality of first regions A may be present. That is, the first area A may include a first sub area A1 and a second sub area A2. The first subregion A1 and the second subregion A2 may not overlap the first connection terminal 105a. Both the first subregion A1 and the second subregion A2 may have a 'U' shape, and the first subregion A1 surrounds the second subregion A2. Can have Other configurations and formation methods may be the same as or similar to those of the first embodiment.

<Example 3>

11A shows a layout of a semiconductor package according to Embodiment 3 of the present invention. FIG. 11B is a cross-sectional view taken along the line II ′ of FIG. 11A.

11A and 11B, in the substrate 202 included in the semiconductor package 402 according to the third exemplary embodiment, the first region A may have a 'U' shape surrounding the semiconductor chip 150. have. The first region A may be formed in an area overlapping the second connection terminal 105b along an edge of the substrate 202, and the semiconductor chip 150 and the second connection terminal 105b may be formed. It can be formed in the area between. The second area B may be disposed in a bar shape at one end of the first area A. FIG. The second region B may be formed in an area overlapping the second connection terminal 105b along an edge of the substrate 202, and the semiconductor chip 150 and the second connection terminal 105b may be formed. It can be formed in the area between. When manufacturing the semiconductor package 402, an underfill resin liquid 160a is supplied between the semiconductor chip 150 and the second region B, and the underfill resin liquid 160a is supplied to the semiconductor chip 150. ) Flows between the substrate 202 and the substrate 202, but the second region B has a roughness such that the underfill resin liquid 160a does not flow and does not flow into the second region B. In addition, the first region A also has a roughness such that the underfill resin liquid 160a does not flow, and thus the underfill resin liquid 160a at the boundary between the first region A and the third region C. ) Flow stops. The first region A and the second region B may be formed to overlap the first and second connection terminals 105a and 105b along the edge of the semiconductor package, or may be formed to overlap the first and second connection terminals. It may be formed between the (105a, 105b) and the semiconductor chip mounting region 150. Other configuration / forming methods may be the same as in the first embodiment.

<Example 4>

12 shows a layout of a semiconductor package according to Embodiment 4 of the present invention.

Referring to FIG. 12, in the substrate 203 included in the semiconductor package 403 according to the fourth exemplary embodiment, the first region A does not exist, and only the second region B is connected to the semiconductor chip 150. It may have a closed curve shape spaced apart to surround the semiconductor chip 150 along the edge of the substrate 203. Other construction / forming methods may be the same as in Example 1.

In the present exemplary embodiment, the closed curve shape of the second area B is described without the first area A. However, the first area A may have a closed curve shape as shown in FIG. 12 without the second area B. Referring to FIG.

Example 5

13A shows a layout of a semiconductor package according to Embodiment 5 of the present invention. FIG. 13B is a cross-sectional view taken along the line II ′ of FIG. 13A.

13A and 13B, the substrate 204 included in the semiconductor package 404 according to the fifth exemplary embodiment includes a second region B having a closed curve shape without the first region A, as disclosed in FIG. 12. ) In addition, the dam 500 may be disposed in the form of a bar between the third region C and the second region B adjacent to a point where the nozzle is disposed to inject the epoxy resin solution. The dam 500 may also be arranged in the structure of the above embodiments 1 to 4. Since the dam 500 is disposed only at one point adjacent to the point where the epoxy resin solution is injected, the area occupied by the dam may be reduced as compared with a package structure having dams located along both sides or the circumference of the semiconductor chip 150.

<Example 6>

14 shows a layout of the semiconductor package according to the sixth embodiment of the present invention. FIG. 15A is a cross-sectional view taken along line II ′ of FIG. 14. FIG. 15B is an enlarged view illustrating a portion 'P' of FIG. 15A.

14, 15A, and 15B, in the substrate 205 included in the semiconductor package 405 according to the fourth embodiment, the first region A has a closed curve shape adjacent to an edge of the semiconductor chip 150. The second region B has a closed curve shape surrounding the first region A. FIG. The third region C is disposed inside the first region A. FIG. Other configurations may be the same as or similar to the first embodiment.

A method of manufacturing the semiconductor package 405 will be described.

16A is a cross-sectional view illustrating a process of manufacturing the semiconductor package having the cross section of FIG. 15A. FIG. 16B is an enlarged view illustrating a portion 'P' of FIG. 16A.

16A and 16B, the substrate 205 is formed as in Method Embodiment 1 or Method Embodiment 2. FIG. Before mounting the semiconductor chip 150, the nozzle 190 is positioned at the center of the substrate 203 and the underfill resin liquid 160a is supplied. The underfill resin liquid 160a flows quickly from the third surface portion 110c to the first surface portion 110a to cover the third surface portion 110c and stop at the first surface portion 110a. If the underfill resin liquid 160a flows over the first surface portion 110a, it does not flow into the second surface portion 110b. Subsequently, with reference to FIGS. 15A and 15B, the semiconductor chip 150 is mounted on the substrate 205 by flip chip bonding. At this time, the underfill resin liquid 160a existing between the chip external connection terminal 155 and the first connection terminal 105a is discharged to the outside by the pressure of the semiconductor chip 150. And a poor contact between the first connection terminal 105a does not occur. Other formation methods may be the same as or similar to Example 1.

<Example 7>

17 shows a layout of the semiconductor package according to the seventh embodiment of the present invention.

Referring to FIG. 17, in the substrate 206 included in the semiconductor package 406 according to the seventh embodiment, the first region A is formed outside the mounting region of the semiconductor chip 150, and the second region ( B) may be formed to surround the first area A, and the first area A may be divided into a plurality of parts. That is, the first area A may include a first sub area A1 and a second sub area A2. The first subregion A1 and the second subregion A2 may not overlap the first connection terminal 105a. Both the first subregion A1 and the second subregion A2 may have a closed curve surrounding the semiconductor chip 150, and the first subregion A1 may be the second subregion A2. ) May have a closed curve shape. Other configurations and formation methods may be the same as or similar to those of the fourth embodiment.

<Example 8>

18 shows a layout of a semiconductor package according to Embodiment 8 of the present invention.

Referring to FIG. 18, the third region C may not exist in the substrate 207 included in the semiconductor package 407 according to the present embodiment. That is, the semiconductor chip 150 may overlap only with the first region A. FIG. The semiconductor package 407 may be formed using a gray photo mask as described in Method Example 1. Alternatively, the semiconductor package 407 may be formed using a blast process as described in Method Example 2. When the semiconductor package 407 is formed using a blast process, after the first blast process is performed on the entire surface of the substrate 207 without forming the first mask pattern 195 shown in FIGS. 8A and 8B, It may be formed by forming a second mask pattern (see 197 of FIGS. 9A and 9B) covering the first region A of FIG. 18 and performing a second blast process. In this case, the photolithography process for forming the first mask pattern 195 of FIG. 8A may be reduced once. Other configurations and formation methods may be the same as or similar to those of the fourth embodiment.

Example 9

19 is a sectional view of a semiconductor package according to Embodiment 9 of the present invention.

Referring to FIG. 19, the semiconductor package 408 according to the ninth embodiment includes a first substrate 208. The first substrate 208 may correspond to the substrate 200 of FIG. 2B. That is, the first substrate 208 includes first to third regions A, B, and C. The first substrate 208 includes a substrate body 100 including a first surface 100a and a second surface 100b, a first insulating film 110, and a second insulating film 120. The first insulating layer 110 has a first surface portion 110a in the first region A and a second surface portion 110b connected to the first surface portion 110a in the second region B. ) In addition, the first insulating layer 110 has a third surface portion 110c in the third region (C). The first connection terminal 105a is disposed in the first region A, and the second connection terminal 105b is disposed in the second region B. Third connection terminals 115 are disposed on the second surface 100b. An external solder ball 312 may be attached to the third connection terminals 115. The first semiconductor chip 150 may be mounted on the first substrate 206. The first semiconductor chip 150 may be mounted in contact with the first connection terminal 105a by a flip chip bonding method. The passivation layer 160 is filled between the first semiconductor chip 150 and the first substrate 208. The second substrate 304 may be disposed on the first substrate 208 to be spaced apart from the first semiconductor chip 150. A second substrate external connection terminal 320 is disposed below the second substrate 304, and an internal solder ball 310 is disposed between the second substrate external connection terminal 320 and the second connection terminal 105b. Disposed to electrically connect the first substrate 208 and the second substrate 304. The plurality of second semiconductor chips 306 may be mounted on the second substrate 304 by, for example, a flip chip bonding method or a wire bonding method. Top surfaces of the second semiconductor chips 306 and the second substrate 304 are covered with a molding layer 308.

The first to third surface parts 110a, 110b and 110c may have a structure disclosed in Examples 1 to 6 or a combination thereof. As a result, the passivation layer 160 may be formed only under the semiconductor chip 150.

<Example 10>

20 is a sectional view of a semiconductor package according to Embodiment 10 of the present invention.

Referring to FIG. 20, the package 409 according to the tenth embodiment includes a substrate 209. The substrate 209 may correspond to the substrate 200 of FIG. 2B. That is, the substrate 209 includes first to third regions A, B, and C. The substrate 209 includes a substrate body 100 including a first surface 100a and a second surface 100b, a first insulating film 110, and a second insulating film 120. The first insulating layer 110 has a first surface portion 110a in the first region A and a second surface portion 110b in the second region B. As shown in FIG. In addition, the first insulating layer 110 has a third surface portion 110c in the third region (C). The first connection terminal 105a is disposed in the first region A, and the second connection terminal 105b is disposed in the second region B. Third connection terminals 115 are disposed on the second surface 100b. The first face 100a faces downward and the second face 100b faces upward. That is, the substrate 200 of FIG. 2B is inverted. The first semiconductor chip 250 is mounted on the first connection terminal 105a. The first semiconductor chip 250 may include a through via 252 penetrating therein. In the first semiconductor chip 250, redistribution pads 258 electrically connected to the through vias 252 are disposed on a surface of the first semiconductor chip 250 facing the first surface 100a. The redistribution pad 258 and the first connection terminal 105a are electrically connected to each other by a bump 244. The space between the first semiconductor chip 250 and the substrate 209 is filled with a protective film 260. A first solder ball 312 is attached to the second connection terminal 105b. Chip borlands 254 electrically connected to the through vias 252 are disposed on a lower surface of the first semiconductor chip 250. A second solder ball 256 is attached to the chip borlands 254. The size of the first solder ball 312 and the second solder ball 256 may be different as shown in FIG. Second semiconductor chips 306 may be stacked on the substrate 209 and mounted in a flip chip bonding method or a wire bonding method. The substrate 209 and the second semiconductor chips 306 may be covered with a molding layer 308.

In the present structure, the first to third surface parts 110a, 110b, and 110c may have the structure disclosed in Embodiments 1 to 6 or a combination thereof. As a result, the passivation layer 260 may be formed only between the first semiconductor chip 250 and the substrate 209 and may not cover the second connection terminal 105B.

<Example 11>

21 is a sectional view of a semiconductor package according to Embodiment 11 of the present invention.

The semiconductor package 410 according to the eleventh exemplary embodiment may have a form in which the structure of the semiconductor package 408 of the ninth embodiment and the structure of the semiconductor package 409 of the tenth embodiment are combined.

That is, specifically, referring to FIG. 21, the semiconductor package 410 according to the eleventh embodiment includes a first substrate 210. The first substrate 210 may correspond to the substrate 200 of FIG. 2B. That is, the first substrate 210 includes first to third regions A, B, and C. The first substrate 210 includes a substrate body 100 including a first surface 100a and a second surface 100b, a first insulating film 110, and a second insulating film 120. The first insulating layer 110 has a first surface portion 110a in the first region A and a second surface portion 110b connected to the first surface portion 110a in the second region B. ) In addition, the first insulating layer 110 has a third surface portion 110c in the third region (C). A first connection terminal 105a is disposed on the first surface 100a in the first region A, and a second connection terminal 105b is disposed on the first surface 100a in the second region B. Is placed. The second insulating layer 120 has a fourth surface portion 120a in the first region A and a fifth surface portion 120b connected to the fourth surface portion 120a in the second region B. ) In addition, the second insulating layer 120 has a sixth surface portion 120c in the third region C. A third connection terminal 115a is disposed on the second surface 100b in the first region A, and a fourth connection terminal 115b is disposed on the second surface 100b in the second region B. Is placed. The surface roughness of the fourth surface portion 120a may be the same as the first surface portion 110a. The surface roughness of the fifth surface portion 120b may be the same as the second surface portion 110b. The surface roughness of the sixth surface portion 120c may be the same as the third surface portion 110c. The first semiconductor chip 150 may be mounted on the first connection terminal 105a in contact with a flip chip bonding method. The space between the first semiconductor chip 150 and the first substrate 210 is filled with the first passivation layer 160. The second semiconductor chip 250 may be mounted on the third connection terminal 115a. The space between the second semiconductor chip 250 and the substrate 208 may be filled with a second passivation layer 260. The second semiconductor chip 250 may include a through via 252 penetrating therein. A redistribution pad 258 electrically connected to the through via 252 is disposed on a surface of the second semiconductor chip 250 that faces the second surface 100b. The redistribution pad 258 and the third connection terminal 115a are electrically connected to each other by a bump 244. Chip borlands 254 electrically connected to the through vias 252 are disposed on a lower surface of the second semiconductor chip 250. A first solder ball 312 is attached to the fourth connection terminal 115b and a second solder ball 256 is attached to the chip ball lands 254. The first solder ball 312 and the second solder ball 256 may have different sizes as shown in FIG. 19. A second substrate 304 electrically connected to the second connection terminal 105b is disposed on the first substrate 210. A plurality of third semiconductor chips 306 may be stacked and mounted on the second substrate 304. Top surfaces of the third semiconductor chips 306 and the second substrate 304 may be covered with a molding layer 308.

The above-described semiconductor package technology may be applied to various kinds of semiconductor devices and package modules having the same.

22 is a perspective view illustrating an electronic device having a semiconductor package according to an embodiment of the present invention. Referring to FIG. 22, a semiconductor package according to an embodiment of the present invention may be applied to an electronic device 1000 such as a mobile phone. Since the semiconductor package of the present exemplary embodiment is excellent in terms of size reduction and performance improvement, it is advantageous in light and short reduction of the electronic device 1000 that simultaneously implements various functions. The electronic device is not limited to the mobile phone illustrated in FIG. 22. For example, a mobile electronic device, a laptop computer, a portable computer, a portable multimedia player (PMP), an MP3 player, a camcorder, a web tablet ), A wireless telephone, navigation, and a personal digital assistant (PDA).

23 is a system block diagram of an electronic device to which a semiconductor package according to an exemplary embodiment of the present invention is applied. Referring to FIG. 23, the above-described semiconductor packages 400-410 may be applied to the electronic system 1100. The electronic system 1100 may include a body 1110, a microprocessor unit 1120, a power unit 1130, a function unit 1140, and a display controller. It may include a unit 1150 (Display Controller Unit). The body 1110 may include a set board formed of a printed circuit board therein, and may include a microprocessor unit 1120, a power unit 1130, a function unit 1140, and a display controller unit 1150. The back may be mounted on the body 1110.

The power unit 1130 receives a predetermined voltage from an external battery (not shown) and branches it to a required voltage level to supply the microprocessor unit 1120, the function unit 1140, the display controller unit 1150, and the like. .

The microprocessor unit 1120 may receive a voltage from the power unit 1130 to control the function unit 1140 and the display unit 1160. The function unit 1140 may perform the functions of the various electronic devices 1000. For example, when the electronic device 1000 is a mobile phone, the function unit 1140 may be a mobile phone function such as dialing, output of an image to the display unit 1160, audio output to a speaker, and the like by communicating with an external device 1170. It may include a number of components that can perform, if the camera is formed together may be a camera image processor (Camera Image Processor). For example, when the electronic device 1000 is connected to a memory card to expand the capacity, the function unit 1140 may be a memory card controller. The functional unit 1140 may exchange signals with the external device 1170 through a wired or wireless communication unit 1180. For example, when the electronic device 1000 requires a universal serial bus (USB) to expand a function, the function unit 1140 may be an interface controller. The semiconductor packages 400-410 according to the embodiment of the present invention may be used in at least one of the microprocessor unit 1120 and the function unit 1140.

The semiconductor package technology described above may be applied to an electronic system. 24 is a block diagram illustrating an example of an electronic device including a semiconductor package to which the technology of the present invention is applied. Referring to FIG. 24, the electronic system 1300 may include a controller 1310, an input / output device 1320, and a memory device 1330. The controller 1310, the input / output device 1320, and the memory device 1330 may be coupled through a bus 1350. The bus 1350 may be a path through which data moves. For example, the controller 1310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing the same function. The controller 1310 and the memory device 1330 may include a semiconductor package according to the present invention. The input / output device 1320 may include at least one selected from a keypad, a keyboard, a display device, and the like. The memory device 1330 is a device for storing data. The memory device 1330 may store data and / or instructions executed by the controller 1310. The memory device 1330 may include a volatile memory device and / or a nonvolatile memory device. Alternatively, the memory device 1330 may be formed of a flash memory. For example, an information processing system such as a mobile device or a desktop computer may be equipped with a flash memory to which the technique of the present invention is applied. Such a flash memory may be composed of a semiconductor disk device (SSD). In this case, the electronic system 1300 may stably store large amounts of data in the flash memory system. The electronic system 1300 may further include an interface 1340 for transmitting data to or receiving data from the communication network. The interface 1340 may be in a wired or wireless form. For example, the interface 1340 may include an antenna or a wired / wireless transceiver. Although not shown, the electronic system 1300 may further include an application chipset, a camera image processor (CIS), an input / output device, and the like. Self-evident to one.

The foregoing detailed description illustrates the present invention. In addition, the foregoing description merely shows and describes preferred embodiments of the present invention, and the present invention can be used in various other combinations, modifications, and environments. That is, changes or modifications may be made within the scope of the concept of the invention disclosed in this specification, the scope equivalent to the disclosed contents, and / or the skill or knowledge in the art. The above-described embodiments are for explaining the best state in carrying out the present invention, the use of other inventions such as the present invention in other state known in the art, and the specific fields of application and uses of the present invention. Various changes are also possible. Accordingly, the detailed description of the invention is not intended to limit the invention to the disclosed embodiments. Also, the appended claims should be construed to include other embodiments.

Claims (18)

A first substrate comprising a first surface portion positioned in a first region, and a second surface portion positioned in a second region adjacent to the first region and connected to the first surface portion,
The surface roughness of the first surface portion is different from the surface roughness of the second surface portion. The method of claim 1,
A first semiconductor chip mounted on the first substrate; And
Further comprising a first passivation layer to fill between the first semiconductor chip and the first substrate,
And the first region is adjacent to an end of the first semiconductor chip. The method of claim 2,
And the second region has at least one closed curve shape surrounding the first semiconductor chip or a bar shape disposed adjacent to one end of the first substrate. The method of claim 2,
The first region may have a 'U' shape or a closed curve shape. The method of claim 2,
The surface roughness of the first surface portion is smaller than the surface roughness of the second surface portion. The method of claim 5, wherein
The first substrate further includes a third surface portion disposed in a third region overlapping the first semiconductor chip and connected to the first surface portion.
The surface roughness of the third surface portion is different from the surface roughnesses of the first and second surface portions. The method according to claim 6,
The surface roughness of the third surface portion is smaller than the surface roughness of the first surface portion. The method of claim 7, wherein
The first substrate,
A substrate body comprising a first side and a second side;
A first connecting terminal disposed on the first surface of the substrate body; And
A first insulating film covering the first surface of the substrate body and exposing the first connection terminal,
And the first insulating layer includes the first to third surface portions in the first to third regions, respectively. The method of claim 8,
The first connecting terminal is disposed on the third surface portion,
The semiconductor chip is mounted on the first connection terminal. The method of claim 8,
Further comprising a second connecting terminal disposed on the second surface portion,
The inner edge of the second region is spaced apart from the second connection terminal by 150㎛ or more. The method of claim 10,
A second substrate disposed on the first substrate and electrically connected to the first substrate through the second connection terminal; And
And a second semiconductor chip mounted on the second substrate. The method of claim 8,
The first substrate may include a third connection terminal disposed on the second surface of the substrate body; And a second insulating film covering the second surface of the substrate body and exposing the third connection terminal.
The second insulating film has a fourth surface portion and a fifth surface portion in the first region and the second region, respectively, wherein the surface roughness of the fourth surface portion is different from the surface roughness of the fifth surface portion. . The method of claim 12,
A second semiconductor chip mounted on the third connection terminal under the first substrate; And
Further comprising a second passivation layer that fills between the second semiconductor chip and the first substrate,
The surface roughness of the fourth surface portion is smaller than the surface roughness of the fifth surface portion. Forming a substrate comprising a first surface portion positioned in a first region and a second surface portion positioned in a second region adjacent to the first region and connected to the first surface portion; And
Mounting a semiconductor chip on the substrate and forming a protective film filling the semiconductor chip and the substrate;
And the second surface portion forms the substrate to have a surface roughness different from that of the first surface portion. The method of claim 14,
Forming the substrate,
Preparing a substrate body;
Forming a photosensitive insulating film on the entire surface of the substrate body;
Performing an exposure process on the photosensitive insulating layer by using a gray photo mask that includes first and second portions respectively corresponding to the first region and the second region and having different light transmittances; And
Removing the exposed portion to form the first and second surface portions having different surface roughnesses on the photosensitive insulating layer. The method of claim 14,
Forming the substrate,
Preparing a substrate body;
Forming an insulating film on the front surface of the substrate body; And
And performing a first blasting process on the insulating film in the first region. 17. The method of claim 16,
The forming of the substrate may further include performing a second blasting process on the insulating layer in the second region. The method of claim 14,
Forming the substrate,
Preparing a substrate body;
Forming an insulating film on the entire surface of the substrate body;
Performing a second blasting process on the insulating film in the second region; And
And performing a first blasting process on the first region and the insulating layer of the first region.

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