KR20110013162A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR20110013162A KR20110013162A KR1020090134733A KR20090134733A KR20110013162A KR 20110013162 A KR20110013162 A KR 20110013162A KR 1020090134733 A KR1020090134733 A KR 1020090134733A KR 20090134733 A KR20090134733 A KR 20090134733A KR 20110013162 A KR20110013162 A KR 20110013162A
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- KR
- South Korea
- Prior art keywords
- film
- forming
- layer
- pattern
- semiconductor device
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
Abstract
The present invention provides a method for forming a metal wiring of a semiconductor device to reduce the coupling capacitance by forming an insulating film having an air gap between the metal wiring, the method of forming a metal wiring of the semiconductor device of the present invention comprises a first insulating film, Forming a multilayer film including an etch stop film and a sacrificial film; Etching a portion of the multilayer to form a plurality of damascene patterns; Forming a metal wiring structure to fill the interior of the damascene pattern; Removing the sacrificial layer; Removing the etch stop layer; And forming a second insulating layer that provides an air gap between the metal wiring structures, and the present invention has the effect of reducing the coupling capacitance by forming an air gap between neighboring metal wirings. have.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for manufacturing a semiconductor device in which an intra coupling capacitance between adjacent metal wirings is reduced.
Recently, as the metal line was changed from aluminum (Al) to copper (Cu), the overall RC delay was reduced.However, as a measure for further improvement, the intra-coupling capacitance A decrease in the number of people also became necessary. Coupling capacitances include inter coupling capacitances and intra coupling capacitances. The intercoupling capacitance is the coupling capacitance between the lower metal wiring and the upper metal wiring (vertical field), and the intra coupling capacitance is the coupling capacitance between the metal wiring of the same level (horizontal field).
1 is a view showing a semiconductor device according to the prior art.
As shown in FIG. 1, a plurality of metal wiring structures having a predetermined interval, a second
In the prior art of FIG. 1, the
In the prior art as described above, the first
However, the process of the dielectric film having a dielectric constant (k) of 2.5 or less is very difficult, and still difficult to evaluate the actual process.
In addition, the conventional technique of FIG. 1 has a limitation in reducing the intra coupling capacitance even when a dielectric film having a low dielectric constant is used by the
SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a semiconductor device and a method of manufacturing the same, which lower an intra coupling capacitance by forming an insulating film having an air gap between neighboring metal wirings. There is this.
The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a plurality of adjacent metal wiring structure at a predetermined interval; And forming an insulating film that provides an air gap between the metallization structures, wherein the forming of the insulating film uses plasma chemical vapor deposition (PECVD). It characterized in that it comprises a silicon oxide film.
In addition, the semiconductor device manufacturing method of the present invention comprises the steps of forming a multilayer film including a first insulating film, an etch stop film and a sacrificial film; Etching a portion of the multilayer to form a plurality of damascene patterns; Forming a metal wiring structure to fill the interior of the damascene pattern; Removing the sacrificial layer; Removing the etch stop layer; And forming a second insulating layer that provides an air gap between the metallization structures. The forming of the second insulating layer is characterized by using plasma chemical vapor deposition (PECVD), the second insulating layer is characterized in that it comprises a silicon oxide film.
In addition, the semiconductor device manufacturing method of the present invention comprises the steps of forming a multilayer film including a first insulating film, an etch stop film and a sacrificial film; Etching a portion of the multilayer to form a plurality of damascene patterns; Forming a protective layer pattern covering a surface of the damascene pattern and a metal wiring structure filling the inside of the damascene pattern on the protective layer pattern; Removing the sacrificial layer; Removing the etch stop layer; And forming a second insulating layer that provides an air gap between the metallization structures. The forming of the second insulating film is characterized by using plasma chemical vapor deposition (PECVD), the second insulating film is characterized in that it comprises a silicon oxide film. The protective layer pattern may include any one of cobalt tungsten phosphide, cobalt tungsten boride, and cobalt tungsten borophosphide.
The present invention described above has the effect of reducing intra coupling capacitance by forming an air gap between metal wiring structures by depositing an insulating film having poor step coverage.
In addition, the present invention has the effect of preventing the sidewall attack of the metallization structure during the subsequent etching process by forming a protective film to protect the sidewalls of the metallization structures.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.
2A to 2I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
As shown in FIG. 2A, the first
As shown in FIG. 2B, the photosensitive film is coated, followed by exposure and development to form a first
Using the first
As shown in FIG. 2C, the
Subsequently, the
Before forming the
As shown in FIG. 2D, the planarization process is performed until the surface of the
By this planarization process, the
As shown in FIG. 2E, a second
Subsequently, a
Subsequently, the second
As illustrated in FIG. 2F, the
The
As shown in FIG. 2G, the
Hereinafter, the
As shown in FIG. 2H, the hard
As such, when the etch
As shown in FIG. 2I, the second insulating
In this case, when the second insulating
On the other hand, the plasma chemical vapor deposition method (PECVD) for forming the second insulating
In addition, an oxygen source for reacting with a silicon source to form a silicon oxide film includes O 2 , N 2 O, O 3 , and the like. The chamber where the plasma chemical vapor deposition (PECVD) is performed supplies the bias power and the source power. Bias power ranges from 0 to 500W, and source power ranges from 1000 to 3000W. In addition, the process pressure is maintained at 10 ~ 50mTorr.
According to the first embodiment described above, by forming the
3 is a view comparing the reduction ratio of the intra coupling capacitance between metal wirings according to the type of insulating film. In FIG. 3, (a) is a first specimen using an oxide film having a dielectric constant of 3.9, (b) is a second specimen using an oxide film having a low dielectric constant of 2.9, and (b) is a third specimen using an oxide film having a dielectric constant of 3.5. (D) is a fourth specimen using an oxide film providing an air gap. The first and second specimens have a nitride film as an etch stop film, and the third and fourth specimens do not have a nitride film as an etch stop film.
Referring to FIG. 3, the second specimen may obtain a reduction ratio of intra coupling capacitance of about 7.9%. In addition, the third specimen was able to obtain a reduction ratio of the intra coupling capacitance of about 21%. The fourth specimen can obtain a reduction rate of intra coupling capacitance of about 35% than the first specimen.
4A to 4I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
As shown in FIG. 4A, the first insulating
As shown in FIG. 4B, after the photoresist film is applied, exposure and development are performed to form the first photoresist pattern 44. The first photoresist pattern 44 is referred to as a damascene mask.
The
As shown in FIG. 4C, the first photoresist pattern 44 is removed.
Subsequently, a
Subsequently, the
Before forming the
As shown in FIG. 4D, the planarization process is performed until the surface of the
By this planarization process, the
As shown in FIG. 4E, a second
Next, a
Subsequently, a second
As shown in FIG. 4F, the
The second
As shown in FIG. 4G, the
Hereinafter, the
The first diffusion
As shown in FIG. 4H, the hard
As such, when the etch
As shown in FIG. 4I, a second insulating
In this case, when the second insulating
Meanwhile, the plasma chemical vapor deposition method (PECVD) for forming the second insulating
In addition, an oxygen source for reacting with a silicon source to form a silicon oxide film includes O 2 , N 2 O, O 3 , and the like. The chamber where the plasma chemical vapor deposition (PECVD) is performed supplies the bias power and the source power. Bias power ranges from 0 to 500W, and source power ranges from 1000 to 3000W. In addition, the process pressure is maintained at 10 ~ 50mTorr.
According to the second embodiment described above, by forming the
Meanwhile, as a modification of the second embodiment, a silicon carbon nitride film SiCN may be applied to prevent the attack of the first
The silicon carbon nitride layer (SiCN) can prevent the attack of the first
Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
1 is a view showing a semiconductor device according to the prior art.
2A to 2I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
3 is a view comparing the reduction ratio of intracoupling capacitance between metal wirings according to the type of insulating film.
4A to 4I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
* Explanation of symbols for the main parts of the drawings
21A: first insulating
27A:
31: second insulating film 32: air gap
Claims (27)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR1020090071012 | 2009-07-31 | ||
KR20090071012 | 2009-07-31 |
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KR20110013162A true KR20110013162A (en) | 2011-02-09 |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101402962B1 (en) * | 2012-04-13 | 2014-06-03 | 한국생산기술연구원 | Method of forming air-gap on the metal interconnect of semiconductor |
US9287198B2 (en) | 2013-09-27 | 2016-03-15 | SK Hynix Inc. | Interconnection structure including air gap, semiconductor device including air gap, and method of manufacturing the same |
US9337150B2 (en) | 2012-09-05 | 2016-05-10 | Samsung Electronics Co., Ltd. | Semiconductor devices including supporting patterns in gap regions between conductive patterns |
US9812450B2 (en) | 2015-04-14 | 2017-11-07 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
KR20180016112A (en) * | 2016-08-05 | 2018-02-14 | 세메스 주식회사 | Substrate treating apparatus and substrate treating apparatus |
KR20190134203A (en) * | 2018-05-25 | 2019-12-04 | 주식회사 디비하이텍 | Rf switch device with an air-gap and method of manufacturing the same |
-
2009
- 2009-12-30 KR KR1020090134733A patent/KR20110013162A/en not_active Application Discontinuation
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101402962B1 (en) * | 2012-04-13 | 2014-06-03 | 한국생산기술연구원 | Method of forming air-gap on the metal interconnect of semiconductor |
US9337150B2 (en) | 2012-09-05 | 2016-05-10 | Samsung Electronics Co., Ltd. | Semiconductor devices including supporting patterns in gap regions between conductive patterns |
US9741608B2 (en) | 2012-09-05 | 2017-08-22 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices including supporting patterns in gap regions between conductive patterns |
US9287198B2 (en) | 2013-09-27 | 2016-03-15 | SK Hynix Inc. | Interconnection structure including air gap, semiconductor device including air gap, and method of manufacturing the same |
US9812450B2 (en) | 2015-04-14 | 2017-11-07 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
KR20180016112A (en) * | 2016-08-05 | 2018-02-14 | 세메스 주식회사 | Substrate treating apparatus and substrate treating apparatus |
KR20190134203A (en) * | 2018-05-25 | 2019-12-04 | 주식회사 디비하이텍 | Rf switch device with an air-gap and method of manufacturing the same |
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