KR20110006946A - Semiconductor chip with low noise through silicon via penetrating guard ring and stack package using the same - Google Patents

Abstract

PURPOSE: A semiconductor chip with a low noise through-silicon-via and a stack package using the same are provided to protect a through-silicon-via from the noise existing on the silicon substrate. CONSTITUTION: A guard ring is formed by ion-injecting the impurity into a silicon substrate(21). The through-silicon-via passes through the guard ring and the silicon substrate. The guard ring is ion-injected with the n-type impurity or the p-type impurity. The guard ring has a bigger diameter than that of the through-silicon-via.

Description

Semiconductor chip having low noise through silicon via passing through guard ring and stacked package using the same {SEMICONDUCTOR CHIP WITH LOW NOISE THROUGH SILICON VIA PENETRATING GUARD RING AND STACK PACKAGE USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor chip having a low noise through silicon via passing through a guard ring and a stacked package using the same.

Packaging technology for semiconductor integrated devices has been continuously developed in accordance with the demand for miniaturization and high capacity. Recently, various technologies for stack packages that can satisfy the miniaturization and high capacity and the mounting efficiency have been developed. .

The stacked package can be manufactured by stacking individual semiconductor chips, and then stacking the stacked semiconductor chips at a time and stacking the packaged individual packages. The individual semiconductor chips of the stacked package are formed of metal wires or through silicon vias. (Through Silicon Via; TSV), etc. are electrically connected.

However, the laminated package using the conventional metal wire is slow because the electrical signal exchange is made through the metal wire, and a large number of wires are used, resulting in deterioration of electrical characteristics. In addition, an additional area is required in the substrate to form a metal wire, thereby increasing the size of the package, and a height of the package is increased because a gap Gap for wire bonding between semiconductor chips is required.

In recent years, a laminated package using through silicon vias (TSVs) has been proposed. Such a laminated package generally forms a via hole penetrating the semiconductor chip in the semiconductor chip, and fills a conductive material in the penetrated via hole to form a through electrode called a through silicon via (TSV). It is implemented by electrically connecting the upper semiconductor chip and the lower semiconductor chip through the through electrode.

Figure 1a is a cross-sectional view showing a laminated package according to the prior art, Figure 1b is a plan view along the line AA 'of Figure 1a.

As shown in FIGS. 1A and 1B, at least two semiconductor chips 110 including a plurality of silicon through vias 102 penetrating through the silicon substrate 101 are stacked. The stacked semiconductor chips 110 form a physical and electrical connection with each other by the through silicon vias 102. The through silicon vias 102 are electrically connected to the pads of the semiconductor chip 110 through rewiring.

A guard ring 103 is provided to surround the through silicon via 102. The guard ring 103 provides electrical insulation between the through silicon via 102 and the inside of the semiconductor chip as well as to relieve stress transmitted to the through silicon via 102, and has a ring shape in plan view. In addition, the through silicon via 102 is provided to be spaced apart.

However, according to the related art, since the guard ring 103 is provided to be spaced apart from the through silicon vias 102, the through silicon vias 102 are adjacent to the silicon substrate 101 so that the high frequency noise may pass. There is a problem that can be.

The present invention has been proposed to solve the above problems of the prior art, to provide a semiconductor chip and a laminated package using the same that can reduce the noise (noise) generated when the guard ring and the through silicon via is spaced apart. There is this.

The semiconductor chip of the present invention for achieving the above object is a silicon substrate; A guard ring formed by ion implantation of impurities into the silicon substrate; And a through silicon via penetrating the guard ring and the silicon substrate.

In addition, the semiconductor chip of the present invention is a silicon substrate; A first conductive guard ring and a second conductive guard ring formed by ion implantation of impurities spaced apart from each other by a predetermined interval in the silicon substrate; A first through silicon via penetrating the first conductive guard ring and the silicon substrate; And a second through silicon via penetrating the second conductive guard ring and the silicon substrate.

In addition, the semiconductor chip of the present invention includes a silicon substrate having a digital circuit and an analog circuit; And a guard ring array provided between the digital circuit and the analog circuit and formed by ion implantation of impurities.

In addition, in the multilayer package of the present invention, a semiconductor chip having a plurality of guard rings formed by ion implantation of impurities and a plurality of through silicon vias penetrating each of the plurality of guard rings is connected to each other through the through silicon vias. It is characterized by two or more laminated.

In the present invention described above, the through silicon via is formed to penetrate the guard ring formed by ion implantation to isolate the noise generated from the through silicon via to the silicon substrate, and to protect the through silicon via from the noise present in the silicon substrate. It can work.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A is a cross-sectional view illustrating a semiconductor chip according to a first embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along the line BB ′ of FIG. 2A.

As shown in FIGS. 2A and 2B, the semiconductor chip 100 according to the first embodiment of the present invention penetrates the silicon substrate 11 and the silicon substrate 11 and is spaced apart from each other through the first through silicon via 12A. ) And the second through silicon via 12B. The silicon substrate 11 includes a silicon substrate ion-implanted with P-type impurities such as boron, and the through silicon vias 12A and 12B are formed of a metal film such as aluminum film Al. The first and second through silicon vias 12A and 12B are connected to ground or a power grid to bias the DC voltage DC. This provides a low impedance path of high frequency noise, allowing the silicon substrate 11 to be separated from the first and second through silicon vias 12A and 12B. The first through silicon via 12A may be connected to a power grid to become a P-TSV (Power TSV), and the second through silicon via 12B may be connected to a ground to become a G-TSV (GND TSV).

A plurality of guard rings 13 and 14 are formed in the silicon substrate 11 so as to surround the first and second through silicon vias 12A and 12B, respectively. The plurality of guard rings 13 and 14 achieve electrical insulation between the first and second through silicon vias 12A and 12B and the semiconductor chip 100 as well as the first and second through silicon vias 12A and 12B. ) To alleviate the stress that is transmitted. The planar guard rings 13 and 14 are larger in size than the first and second through-silicon vias 12A and 12B, and the cross-sectional view of the first and second through-silicon vias 12A and 12B respectively. It passes through the guard rings 13 and 14.

Looking at the guard rings (13, 14) in detail as follows.

The guard ring includes a first guard ring 13 and a second guard ring 14, and both of the first and second guard rings 13 and 14 may be impurity regions doped with impurities. That is, it is formed in the silicon substrate 11 through ion implantation of P-type impurities or N-type impurities.

The first guard ring 13 and the second guard ring 14 are ion-implanted with impurities of different conductivity types. For example, the N-type impurity is ion-implanted in the first guard ring 13, and the P-type impurity is ion-implanted in the second guard ring 14. The N-type impurity may include phosphorus (P) or arsenic (As), and the P-type impurity may include boron (Boron; B).

As described above, since the first guard ring 13 and the second guard ring 14 are spaced apart from each other by being ion-implanted by impurities of different conductivity types, the neighboring first through silicon vias 12A and the first guard ring 13 are formed. The two through silicon vias 12B are separated from each other. That is, the first through silicon via 12A penetrating the first guard ring 13 and the second through silicon via 12B penetrating the second guard ring 14 are separated from each other.

Meanwhile, in the above-described first embodiment, the first guard ring 13 is formed by ion implantation of N-type impurities, and the second guard ring 14 is formed by ion implantation of P-type impurities. In this case, the first guard ring may be formed by ion implantation of P-type impurities, and the second guard ring may be formed by ion implantation of N-type impurities. Preferably, in order to minimize the loss due to noise, the first guard ring 13 is formed by ion implantation of N-type impurities and connected to a power network, and the second guard ring 14 is a P-type impurity. It must be formed by ion implantation of and connected to the ground network.

The first guard ring 13 and the second guard ring 14 are laid out in a rectangular shape filled in the semiconductor chip 100 during the fabrication step of the semiconductor chip 100 before forming the through silicon vias 12A and 12B. In the process step, the through-holes are formed to penetrate the first guard ring 13 and the second guard ring 14, and then the through-silicon vias 12A and 12B embedded in the through-holes are formed.

According to the first embodiment described above, the first and second through-silicon vias 12A and 12B are formed to pass through the first and second guard rings 13 and 14 formed by ion implantation of impurities, respectively. That is, the first and second gaps do not exist between the first through silicon via 12A and the first guard ring 13 and between the second through silicon via 12B and the second guard ring 14. Noise generated by the silicon substrate 11 can be separated from the through silicon vias 12A and 12B, and the first and second through silicon vias 12A and 12B are protected from the noise present in the silicon substrate 11. can do.

3A is a cross-sectional view illustrating a semiconductor chip according to a second embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along the line BB ′ of FIG. 3A.

As shown in FIGS. 3A and 3B, the semiconductor chip 200 according to the second embodiment of the present invention passes through the silicon substrate 21 and the silicon substrate 21 and is spaced apart from each other through the first through silicon vias 22A. ) And a second through silicon via 22B. The silicon substrate 21 includes a silicon substrate ion-implanted with P-type impurities such as boron, and the first and second through silicon vias 22A and 22B are formed of a metal film such as aluminum film Al. do. The first and second through silicon vias 22A and 22B are connected to ground or a power grid to bias the DC voltage DC. This provides a low impedance path of high frequency noise, so that the silicon substrate 21 can be separated from the first and through silicon vias 12A and 12B. The first through silicon vias 22A may be connected to a power grid to become a P-TSV (Power TSV), and the second through silicon vias 22B may be connected to a ground to become a G-TSV (GND TSV).

A plurality of guard rings 23, 24, and 25 are formed in the silicon substrate 21 so as to surround the first and second through silicon vias 22A, 22B. The plurality of guard rings 23, 24, and 25 achieve electrical insulation between the first and second through silicon vias 22A and 22B and the semiconductor chip 200, as well as the first and second through silicon vias 22A. , 22B) to relieve stress. In the plan view, each of the guard rings 23, 24, and 25 is larger than the through silicon vias 22A, 22B, and in the cross-sectional view, the first and second through-silicon vias 22A, 22B are the respective guard rings. It penetrates through (23, 24, 25).

Looking at the guard ring in detail:

The guard ring includes a first guard ring 23, a second guard ring 24, and a third guard ring 25, and all of the first to third guard rings 23, 24, and 25 are doped with impurities. It may be an impurity region. That is, the silicon substrate 21 is formed through ion implantation of P-type impurities or N-type impurities.

The first guard ring 23 and the second guard ring 24 are ion-implanted with impurity having the same conductivity, and the third guard ring 25 has the first and second guard rings ( Contrast with 23 and 24, ion-implanted impurities are implanted. For example, the first guard ring 23 and the second guard ring 24 are ion implanted with N type impurity, and the third guard ring 25 has a P type impurity. This ion implantation is carried out. Here, the first guard ring 23 and the second guard ring 24 are implanted with N-type impurities, but have different concentrations of impurities. The concentration of the impurity implanted into the second guard ring 24 may be higher than the concentration of the impurity implanted into the first guard ring 23. The N-type impurity may include phosphorus (P) or arsenic (As), and the P-type impurity may include boron (Boron; B).

As described above, since the first guard ring 23 and the third guard ring 25 are spaced apart from each other by being ion-implanted by impurities of different conductivity types, the neighboring first through silicon vias 22A. And the second through silicon via 22B are separated from each other. That is, the first through silicon via 22A penetrating the first guard ring 23 and the second guard ring 24 and the second through silicon via 22B penetrating the third guard ring 25 are separated from each other. do.

The first guard ring 23 may be a well type formed deeper than the second guard ring 24, and the second guard ring 24 and the third guard ring 25 have the same depth. Accordingly, separation between the first through silicon via 22A enclosed by the first and second guard rings 23 and 24 and the second through silicon via 22B enclosed by the third guard ring 25. Is easy. The first guard ring 23 may have the form of an N-well in which N-type impurities are ion implanted. As described above, the first and second guard rings 23 and 24 through which the first through silicon vias 22A penetrate have a double guard ring structure.

Meanwhile, in the above-described second embodiment, the first guard ring 23 and the second guard ring 24 are formed by ion implantation of N-type impurities, and the third guard ring 25 is ion implanted of P-type impurities. In another embodiment, the first guard ring and the second guard ring may be formed by ion implantation of P-type impurities, and the third guard ring may be formed by ion implantation of N-type impurities. Preferably, in order to minimize the loss due to noise, the first and second guard rings 23 and 24 should be formed by ion implantation of N-type impurities and connected to a power network, and the third guard ring 25 ) Should be formed by ion implantation of P-type impurities and connected to the ground network.

The first guard ring 23, the second guard ring 24, and the third guard ring 25 may be filled in the semiconductor chip manufacturing step before forming the first and second through-silicon vias 22A and 22B. Lay out in the shape of a rectangle, and in the subsequent packaging process step to form a through-hole to penetrate the first guard ring 23, the second guard ring 24 and the third guard ring 25 is embedded in the through hole First and second through silicon vias 22A and 22B are formed.

According to the second embodiment described above, the first through silicon vias 22A are formed to penetrate through the first and second guard rings 23 and 24 formed by ion implantation of impurities, and the ion implantation of impurities is formed A second through silicon via 22B penetrating through the third guard ring 25 is formed. That is, no space exists between the first through silicon vias 22A and the first and second guard rings 23 and 24, and between the second through silicon vias 22B and the third guard ring 25. The noise generated by the silicon substrate 21 can be separated from the first and second through-silicon vias 22A and 22B by removing the space therebetween, and the first noise can be separated from the noise present in the silicon substrate 21. And the second through silicon vias 22A and 22B. In addition, by forming a double guard ring structure consisting of the first guard ring 23 and the second guard ring 24, separation between the first through silicon vias 22A and the second through silicon vias 22B is easier. In addition, the effect of separating noise is further increased.

4 is a diagram illustrating a semiconductor chip having a guard ring array as a modification of the second embodiment of the present invention.

Referring to FIG. 4, a plurality of through-silicon vias 301A, 301B pass through each of the guard rings 302, 303, and 304 between the digital circuit 310 and the analog circuit 320. When arranged in a row to form a guarding array, it is possible to more effectively achieve noise separation between two circuits in a system in which the digital circuit 310 and the analog circuit 320 are mixed.

In FIG. 4, the guard ring array formed on the digital circuit 310 side is formed of an array of through silicon vias 301A penetrating through the first guard ring 302 and the second guard ring 303. The guard ring array formed on the side of the analog circuit 320 is composed of an array of through-silicon vias 301B passing through the third guard ring 304. The first guard ring 302 and the second guard ring 303 are guard rings ion implanted with N-type impurities, and the third guard ring 304 is guard rings implanted with P-type impurities. The first guard ring 302 and the third guard ring 304 are spaced apart from each other at regular intervals. The cross-sectional structure of the first to third guard rings is referred to Figure 3b.

FIG. 5 illustrates a stack package in which semiconductor chips are stacked in accordance with a second embodiment of the present invention, and illustrates a structure of a through silicon via chip stack package.

Referring to FIG. 5, the stacked semiconductor package 400 includes at least two semiconductor chips. Each semiconductor chip includes a first through silicon via 402A and a second through silicon via 402B spaced apart from each other, and an upper semiconductor chip and a lower semiconductor chip each include a first through silicon via 402A and a second through silicon via. Connection is made through silicon via 402B.

Each semiconductor chip has a first through silicon via 402A and a second through silicon via 402B spaced apart from each other through the silicon substrate 401 and the silicon substrate 401. The silicon substrate 401 includes a silicon substrate ion-implanted with P-type impurities such as boron, and the first and second through-silicon vias 402A and 402B are formed of a metal film such as aluminum film Al. do. A plurality of guard rings 403, 404, 405 are formed in the silicon substrate 401 so as to surround the first and second through silicon vias 402A, 402B. Here, the first and second through-silicon vias 402A and 402B pass through the respective guard rings.

Looking at the guard ring in detail:

The guard ring includes a first guard ring 403, a second guard ring 404, and a third guard ring 405, and all of the first to third guard rings 403, 404, and 405 are doped with impurities. It may be an impurity region. That is, the silicon substrate 401 is formed through ion implantation of P-type impurities or N-type impurities.

The first guard ring 403 and the second guard ring 404 have a double guard ring structure in which impurities of the same conductivity type are ion-implanted, and the third guard ring 405 has a first guard ring and a first guard ring 405. Ions are implanted with impurities of the opposite conductivity type to the second guard rings 403 and 404. For example, the first guard ring 403 and the second guard ring 404 are ion implanted with an N type impurity, and the third guard ring 405 has a P type impurity. This ion implantation is carried out. Here, the first guard ring 403 and the second guard ring 404 are implanted with N-type impurities, but have different concentrations of impurities. The concentration of the impurity implanted into the second guard ring 404 may be higher than the concentration of the impurity implanted into the first guard ring 403. The N-type impurity may include phosphorus (P) or arsenic (As), and the P-type impurity may include boron (Boron; B).

As described above, since the first guard ring 403 and the third guard ring 405 are spaced at a predetermined interval while being ion implanted by impurities of different conductivity types, the first guard ring 403 and the neighboring first through silicon via 402A are separated from each other. The second through silicon vias 402B are separated from each other. The first guard ring 403 may be a well type formed deeper than the second guard ring 404, and the second guard ring 404 and the third guard ring 405 have the same depth. Accordingly, separation between the first through silicon via 402A surrounded by the first and second guard rings 403 and 404 and the second through silicon via 402B surrounded by the third guard ring 405. Is easy. The first guard ring 403 may have the form of an N-well in which N-type impurities are ion implanted. In the above-described embodiment, the first guard ring 403 and the second guard ring 404 are formed by ion implantation of N-type impurities, and the third guard ring 405 is implanted by ion implantation of P-type impurities. In another embodiment, the first guard ring 403 and the second guard ring 404 are formed by ion implantation of P-type impurities, and the third guard ring 405 is formed by ion implantation of N-type impurities. It may be formed. Preferably, in order to minimize the loss caused by noise, the first guard ring 403 and the second guard ring 404 should be formed by ion implantation of N-type impurities to be connected to a power network. The ring 405 should be formed by ion implantation of P-type impurities and connected to the ground network.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A is a cross-sectional view of a laminated package according to the prior art.

1B is a plan view along the line AA ′ of FIG. 1A;

2A is a sectional view showing a semiconductor chip according to the first embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along the line BB ′ of FIG. 2A;

3A is a sectional view of a semiconductor chip according to a second embodiment of the present invention;

3B is a cross-sectional view taken along the line BB ′ of FIG. 3A.

4 shows a semiconductor chip having a guard ring array as a modification of the second embodiment of the present invention.

FIG. 5 illustrates a stack package in which semiconductor chips according to a second embodiment of the present invention are stacked. FIG.

* Explanation of symbols for the main parts of the drawings

21: silicon substrate 22A: first through silicon via

22B: 2nd penetrating silicon via 23: 1st guard ring

24: 2nd guard ring 25: 3rd guard ring

Claims (20)

Silicon substrate; A guard ring formed by ion implantation of impurities into the silicon substrate; Through silicon via penetrating the guard ring and the silicon substrate Semiconductor chip comprising a. The method of claim 1, The guard ring is ion-implanted with N-type impurities or P-type impurities Semiconductor chip. The method of claim 1, The guard ring is larger than the through silicon vias Semiconductor chip. Silicon substrate; A first conductive guard ring and a second conductive guard ring formed by ion implantation of impurities spaced apart from each other in the silicon substrate by a predetermined distance; A first through silicon via penetrating the first conductive guard ring and the silicon substrate; And A second through silicon via penetrating the second conductive guard ring and the silicon substrate; Semiconductor chip comprising a. The method of claim 4, wherein The first conductive guard ring has a double guard ring structure Semiconductor chip. The method of claim 5, The double guard ring structure includes a first impurity region and a second impurity region having a lower impurity concentration and a deeper depth than the first impurity region. Semiconductor chip. The method according to claim 4 or 6, The first conductive guard ring is ion implanted with N-type impurity, and the second conductive guard ring is ion implanted with P-type impurity Semiconductor chip. The method of claim 7, wherein The first through silicon via is connected to a power grid, and the second through silicon via is connected to ground. Semiconductor chip. A silicon substrate having a digital circuit and an analog circuit; And A guard ring array formed between the digital circuit and the analog circuit and formed by ion implantation of impurities. Semiconductor chip comprising a. 10. The method of claim 9, The guard ring array, A first conductive guard ring and a second conductive guard ring formed by ion implantation of impurities spaced apart from each other by a predetermined interval in the silicon substrate; A plurality of first through silicon vias passing through the first conductive guard ring and the silicon substrate; And A plurality of second through silicon vias passing through the second conductive guard ring and the silicon substrate; Semiconductor chip comprising a. The method of claim 10, The first conductive guard ring has a double guard ring structure Semiconductor chip. The method of claim 11, The double guard ring structure includes a first impurity region and a second impurity region having a lower impurity concentration and a deeper depth than the first impurity region. Semiconductor chip. The method of claim 10 or 12, The first conductive guard ring is ion implanted with N-type impurity, and the second conductive guard ring is ion implanted with P-type impurity Semiconductor chip. A semiconductor chip having a plurality of guard rings formed by ion implantation of impurities and a plurality of through silicon vias penetrating each of the plurality of guard rings are connected to each other through the through silicon vias and stacked at least two or more. Laminated package. The method of claim 14, The plurality of guard rings, A stack package including a first conductive guard ring and a second conductive guard ring formed by ion implantation of impurities spaced apart from each other by a predetermined interval in a silicon substrate. The method of claim 15, The first conductive guard ring, Laminated package with double guard ring structure. The method of claim 16, The double guard ring structure, A stack package comprising a first impurity region and a second impurity region having a smaller impurity concentration and a deeper depth than the first impurity region. The method according to claim 15 or 17, The first conductive guard ring is ion-implanted with an N-type impurity, and the second conductive guard ring is ion-implanted with a P-type impurity. The method of claim 14, The semiconductor chip may include a semiconductor chip in which a digital circuit and an analog circuit are mixed. The method of claim 19, The digital circuit and the analog circuit are separated by the guard ring, wherein the guard ring has an array structure formed with a plurality of guide rings in which the plurality of through silicon vias are arranged.

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