KR101515613B1 - Semiconductor package including interposer and method for manufacturing the same - Google Patents

Abstract

A method of manufacturing a semiconductor package according to the present invention includes the steps of: forming through electrodes connecting a first surface and a second surface to a substrate; forming at least one laminated semiconductor chip connected to the penetrating electrodes on the first surface; Forming an interposer by dicing the substrate in a unit of the semiconductor chip, arranging the interposers and the semiconductor chips at regular intervals on a molding sheet, forming a protective material on the molding sheet And removing the molding sheet and then dicing the protective material to form a package of the interposer and the semiconductor chip. According to the present invention, since the diced interposer is molded in a state of being arranged at a suitable interval on the molding sheet in order to provide a space between adjacent interposers, the side surface of the interposer can be effectively molded.

Description

Technical Field [0001] The present invention relates to a semiconductor package including an interposer and a manufacturing method thereof,

In particular, the present invention relates to a semiconductor package including an interposer and a method of manufacturing the same. More particularly, the cavity formed by recessing the lower side edge of the interposer is filled with a molding member to protect the side surface of the interposer, To a semiconductor package and a method of manufacturing the same.

BACKGROUND ART [0002] Recent trends in the electronics industry are moving toward the production of lightweight, miniaturized, high-speed, multi-functional and highly reliable products at low cost. One of the important technologies that make this possible is package technology. Generally, the interposer substrate is one of the package technologies that realizes the three-dimensional structure and miniaturization.

1, the semiconductor package 10 includes an interposer substrate 14 to which external terminals 12 are attached, a semiconductor chip 16 to be mounted on the interposer substrate 14, and an interposer substrate 14 And a molding member 18 for protecting the upper portion. Since the molding member 18 is formed only on the upper surface of the interposer substrate 14, the side, particularly the edge portion of the interposer substrate 14 is very vulnerable to impact. Further, there is a problem that the interposer substrate 14 is disengaged from the semiconductor package 10 arbitrarily.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a semiconductor package including an interposer that can protect a side surface of an interposer, .

Another object of the present invention is to provide a semiconductor package including an interposer that prevents the interposer from being arbitrarily disengaged from the package, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a semiconductor package including an interposer, a semiconductor chip stacked on an interposer, and a molding member for protecting the interposer and the semiconductor chip, , The molding member covers at least a side surface of the interposer.

A method of manufacturing a semiconductor package according to the present invention includes the steps of: forming through electrodes connecting a first surface and a second surface to a substrate; forming at least one laminated semiconductor chip connected to the penetrating electrodes on the first surface; The method comprising the steps of: dicing the substrate in a unit of the laminated semiconductor chip to form interposers; arranging the interposers and the semiconductor chips at regular intervals on the molding sheet; forming a protective material on the molding sheet And removing the molding sheet and then dicing the protective material to form a package of the interposer and the semiconductor chip.

As described above, according to the configuration of the present invention, the following effects can be expected.

First, since the integrated type interposer wafer is diced by the unit interposer, and then the interposer is molded on the molding sheet at a proper interval in order to provide a space between the adjacent interposers, Side moldings can be freely adjusted while effectively molding the side surfaces. In particular, there is no need to cut expensive interposer wafers to make space between unit interposers, which is economical.

Second, since the interposer wafer front face is attached on the thinning sheet to expose the penetrating electrode, the interposer wafer front face is thinned, and the interposer wafer face is continuously half cut or half-etched continuously, so that the cavity can be easily formed have.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a configuration of a semiconductor package according to the prior art;
2 is a cross-sectional view showing a configuration of a semiconductor package including an interposer according to an embodiment of the present invention.
3 is a cross-sectional view showing a configuration of a semiconductor package including an interposer according to another embodiment of the present invention.
4A to 4J are cross-sectional views showing the manufacturing method of Fig.
Figures 5A-5F are cross-sectional views illustrating the method of manufacture of Figure 2;

Hereinafter, preferred embodiments of the semiconductor package including the interposer according to the present invention and the method for fabricating the same will be described in detail with reference to the accompanying drawings.

FIG. 2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor package including a cavity according to another embodiment of the present invention.

Referring to FIG. 2, the semiconductor package 50 of the present invention includes an interposer 100, a semiconductor chip 200, and a molding member 400. The interposer 100 has a first surface 110a corresponding to the upper surface, a second surface 110b opposite to the first surface 110a and a side 110c connecting the first and second surfaces . The first surface 110a may be front-side. The second surface 110b may be a back-side. The semiconductor chip 200 is stacked on the first surface 110a using the solder bumps 122. [ The molding member 400 covers the first surface 110a and the side surface 110c of the interposer 100 excluding the second surface 110b and the semiconductor chip 200. [ Accordingly, the molding member 400 exposes only the second surface 110b. As such, the molding member 400 covers the side surface 110c of the interposer 110 to better protect the interposer 110 from external impact. In addition, the second surface 110b is exposed, and the rewiring pattern (not shown) is formed on the second surface 110b, so that various electrical tests can be easily performed.

3, the semiconductor package 60 of the present invention includes an interposer 100, a semiconductor chip 200 stacked on the interposer 100 through a solder bump 122, and an interposer 100 And a molding member (400) for protecting the semiconductor chip (200). The molding member 400 covers at least the side surface 110c of the interposer 100 so that the sectional area of the first surface 110a embedded in the molding member 100 is larger than that of the second surface 110b Wider than the cross-sectional area. A part of the edge of the second surface 110b of the interposer 100 is recessed to form the cavity C on the side surface 110c so that the cavity C is filled with the molding member 400. [ The molding member 400 filled in the cavity C protects the side surface 100c of the interposer 100 and also performs a locking function to prevent the interposer 100 from being arbitrarily disengaged from the molding member 400. [

Hereinafter, a method of manufacturing a semiconductor package including an interposer according to the present invention will be described in detail.

4A to 4J are cross-sectional views illustrating a method of manufacturing a package according to an embodiment of the present invention, and show a case of a package including a cavity C for preventing deviation of the interposer.

Referring to FIG. 4A, a substrate 110 is prepared. The first surface 110a of the substrate 110 is patterned so that the via holes H are formed in a predetermined region of the substrate 110 to a predetermined depth. The via-holes H may be formed through a photolithography process. Or may be formed through a laser process. The via-holes H may be formed by one process, or may be formed by dividing into a plurality of processes.

Referring to FIG. 4B, an insulating film (not shown) may be formed on the first surface 110a of the substrate 110 including the via-holes H through a CVD or PVD process. The insulating layer may be deposited to a predetermined thickness on the lower holes H including the first surface 110a. A barrier film for preventing diffusion may be further formed on the insulating film. When a penetrating electrode is formed using a plating process, a seed film may be further formed on the insulating film. Through electrodes 120 filling the via holes H may be formed on the insulating layer. At this time, the barrier film and the seed film formed on the first surface 110a of the substrate 110 may be removed by a planarization process (CMP).

Referring to FIG. 4C, the penetrating electrodes 120 may be exposed through a thin film process that removes the second surface 110b of the substrate 110. Referring to FIG. A thinning sheet 170 may be attached to the substrate 110 for a thin film process. That is, the second surface 110b can be processed while the first surface 110a of the substrate 110 is fixed to the thinning sheet 170. [ For example, a thinning process may be performed to expose the penetrating electrode 120 buried in the substrate 110 using a chemical mechanical polishing (CMP) process or an etch back process. The thickness of the substrate 110 is reduced by the thinning process.

Referring to FIG. 4D, half-cutting or half-etching may be performed to form the cavity C on the thinned second surface 110b. The cavity C may be a boundary region for dividing the penetrating electrode 120 in units of a package. A partial cutting process is performed such that the thinned second surface 110b is half-cut by the first width W1 using a laser or a dicing blade. If the substrate 110 is wafer-based, it may be partially cut through a half-etching process. Here, the height of the cavity C, which is recessed by half cutting or half etching, may be less than half the thickness of the thinned substrate 110.

Referring to FIG. 4E, the thinning sheet 170 (FIG. 4D) is removed. A conductive material is deposited on the first surface 110a of the substrate 110 using a metallization process and the rewiring patterns (not shown) electrically connected to the penetrating electrodes 120 using an etching process, Can be formed. A passivation film (not shown) may be formed on the first surface 110a of the substrate 110 to expose a part of the redistribution patterns.

Also, at least one semiconductor chip 200 may be stacked on the first surface 110a of the substrate 110. [ Since the semiconductor chips 200 are formed with through electrodes (not shown) and semiconductor chip pads (not shown), the through electrodes 120 of the substrate 110 are electrically connected to the through holes 120 through the solder bumps 122 . For example, the penetrating electrodes 120 of the substrate 110 may be electrically connected to the penetrating electrodes (not shown) of the semiconductor chips 200 stacked thereon via rewiring patterns (not shown) .

The semiconductor chips 200 may include a memory semiconductor chip, a logic semiconductor chip, or various passive elements such as a resistor, a capacitor, and the like. The semiconductor chips 200 may be composed of the same kind of semiconductor chips or different kinds of semiconductor chips.

Referring to FIG. 4F, full cutting through the substrate 110 may be performed. The dicing sheet 180 may be attached to the second surface 110b. The substrate 110 is fully cut into the second width W2 by using the laser so that the substrate 110 or the integral interposer is diced into the unit interposer 100. [ The second width W2 is narrower than the first width W1. The full cut line L may pass through the center of the cavity C as viewed from the second surface 110b of the substrate 110. [

Referring to FIG. 4G, the semiconductor chip 200 and the interposer 100 are integrally sealed. To this end, the interposer 100 may be attached onto the molding sheet 190 using an adhesive (not shown). At this time, when the interposer 100 and the semiconductor chip 200 are disposed on the molding sheet 190, predetermined intervals are maintained. That is, both sides of the interposer 100 are molded, and a sufficient interval should be maintained such that unit molding members (400 of FIG. 4J) are present on both sides of the interposer 100 after the dicing process.

Referring to FIG. 4H, the semiconductor chip 200 and the interposer 100, which are arranged at regular intervals on the molding sheet 190, are integrally molded. That is, in the state that the second surface 110b of the interposer 100 is fixed to the molding sheet 190, the protective material 330 may be formed on the first surface 110a. At this time, the protective material 330 is molded so as to cover both sides of the interposer 100 and the upper surface of the semiconductor chip 200.

Referring to FIG. 4I, the molding sheet 190 may be removed. A clean process may be performed so that the adhesive (not shown) can be completely removed. At this time, the rewiring process and the bump process may be performed on the backlapped second surface 110b.

Referring to FIG. 4J, a singulation process for separating the molded interposer 100 and the semiconductor chip 200 into a package unit may be performed. A step of cutting the integral protective material 330 into a unit molding member (400 in FIG. 4J) through dicing or the like may be performed. Such a unit package can be subjected to electrical inspection by putting it in a test socket.

5A to 5F, which illustrate a manufacturing process of a package according to another embodiment of the present invention, the contents overlapping with those described above will be omitted or briefly described.

Referring to FIG. 5A, penetrating electrodes 120 connecting the first surface 110a and the second surface 110b of the substrate 100 are formed.

Referring to FIG. 5B, the redistribution patterns (not shown) electrically connected to the penetrating electrodes 120 may be formed on the first surface 110a of the substrate 110. FIG. At least one semiconductor chip 200 may be stacked on the first surface 110a of the substrate 110. [ The semiconductor chips 200 are electrically connected to the penetrating electrodes 120 of the substrate 110 using solder bumps 122.

Referring to FIG. 5C, a dicing sheet 180 may be attached to the second surface 110b to effect full cutting through the substrate (110 of FIG. 5B). As a result, the substrate 110 is diced into the unit interposer 100, and the interposer 100 and the semiconductor chip 200 constitute one package unit.

Referring to FIG. 5D, the semiconductor chip 200 and the interposer 100 are arranged at predetermined intervals using the molding sheet 190.

Referring to FIG. 5E, the semiconductor chip 200 and the interposer 100, which are arranged at regular intervals on the molding sheet 190, are integrally molded using the protective material 330. At this time, the protective material 330 is molded so as to cover the side surface of the interposer 100 and the upper surface of the semiconductor chip 200.

Referring to FIG. 5F, after the molding sheet 190 (FIG. 5E) is removed, a singulation process for separating the molded interposer 100, the semiconductor chip 200, and the molding member 400 into a package unit is performed .

As described above, the present invention forms a molding member for protecting the side surface of the interposer by forming a space between the interposers when rearranging the diced interposer on the molding sheet, It can be seen that the structure for preventing the interposer from being arbitrarily disengaged from the molding member by filling a molding member into the cavity formed by recessing a part is considered as a technical idea. Many other modifications will be possible to those skilled in the art, within the scope of the basic technical idea of the present invention.

50, 60: semiconductor package
100: interposer 110: substrate
110a: first surface 110b: second surface
110c: side surface 120: penetrating electrode
122: solder bump 170: thinning sheet
180: dicing sheet 190: molding sheet
200: semiconductor chip 330: protective material
400: molding member H: via hole
C: cavity L: full cut line

Claims (9)

delete Interposer;
A semiconductor chip stacked on an interposer; And
And a molding member for protecting the interposer and the semiconductor chip,
Wherein the molding member covers at least a side surface of the interposer,
Wherein the interposer includes a first surface that is embedded in the molding member and a second surface that is exposed to the outside, wherein the cross-sectional area of the first surface is wider than the cross-sectional area of the second surface,
Wherein a portion of the second surface edge of the interposer is recessed to form a cavity on a side surface thereof, and the cavity is filled with a molding member. delete delete Forming through electrodes connecting the first surface of the front surface and the second surface of the white surface to the substrate;
Forming one or more laminated semiconductor chips connected to the penetrating electrodes on the first surface;
Dicing the substrate into the semiconductor chips to form interposers;
Arranging the interposers and the semiconductor chips at regular intervals on a molding sheet;
Forming a protective material on the molding sheet; And
Removing the molding sheet, and then dicing the protective material to form a unit package of the interposer, the semiconductor chip, and the molding member. Forming through electrodes connecting the first surface and the second surface to the substrate;
Forming a cavity for partitioning the penetrating electrodes in a package unit on the second surface;
Forming one or more laminated semiconductor chips connected to the penetrating electrodes on the first surface;
Dicing the substrate in the package unit to form interposers;
Arranging the interposers and the semiconductor chips at regular intervals on a molding sheet;
Forming a protective material on the molding sheet; And
Removing the molding sheet, and then dicing the protective material to form a unit package of the interposer, the semiconductor chip, and the molding member. The method according to claim 6,
The forming of the penetrating electrodes may include:
Patterning the first surface of the substrate to form via holes;
Forming an insulating film on the via-holes;
Forming a through electrode on the insulating film; And
Attaching a thinning sheet to the first surface and thinning the second surface to expose penetrating electrodes that are buried in the substrate. 8. The method of claim 7,
Wherein forming the cavity comprises:
Wherein the second surface is half-cut using the thinning sheet attached to the first surface. Forming via holes in the first surface of the substrate;
Filling the via holes with a conductive material to form through electrodes;
Thinning a second surface of the substrate to expose the penetrating electrode;
Half-cutting the thinned second surface to form a cavity for partitioning the penetrating electrodes in a package unit;
Stacking one or more semiconductor chips on a first surface of the substrate and electrically connecting the penetrating electrodes;
Dicing the substrate with the interposer of the package unit;
Disposing the interposer and the semiconductor chip on the molding sheet at regular intervals;
Forming a protective material on at least the side surface of the interposer and the upper surface of the semiconductor chip on the molding sheet;
Removing the molding sheet; And
And dicing the protective material in the package unit so as to include the interposer and the semiconductor chip.

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