KR20110130111A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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Publication number
KR20110130111A
KR20110130111A KR1020100049584A KR20100049584A KR20110130111A KR 20110130111 A KR20110130111 A KR 20110130111A KR 1020100049584 A KR1020100049584 A KR 1020100049584A KR 20100049584 A KR20100049584 A KR 20100049584A KR 20110130111 A KR20110130111 A KR 20110130111A
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KR
South Korea
Prior art keywords
vias
chip
axis direction
semiconductor
silicon vias
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Application number
KR1020100049584A
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Korean (ko)
Inventor
유종호
이창현
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주식회사 하이닉스반도체
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Priority to KR1020100049584A priority Critical patent/KR20110130111A/en
Publication of KR20110130111A publication Critical patent/KR20110130111A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures

Abstract

PURPOSE: A semiconductor integration circuit is provided to minimize the whole area of the device by removing the unnecessary space of a semiconductor chip through optimizing the arrangement structure of a plurality of penetration silicon vias. CONSTITUTION: In a semiconductor integration circuit, a plurality of penetration silicon vias(240) passes through a semiconductor chip(210). The penetration silicon via passes a signal and power between stacked semiconductor chips. The penetration silicon vias are arranged as a plurality of rows by a certain interval between them. An adjacent two penetration silicon vias are arranged in the different axes while facing to an Y axis. The penetration silicon via arranged in the same axle as an X-axis is separated by a first interval.

Description

[0001] SEMICONDUCTOR INTEGRATED CIRCUIT [0002]

The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor integrated circuit.

In general, packaging technology for semiconductor integrated circuits has been continuously developed to meet the demand for miniaturization and mounting reliability. Recently, as the miniaturization of electric / electronic products and high performance are required, various technologies for stack packages have been developed.

The term "stack" in the semiconductor industry refers to stacking at least two or more semiconductor chips or packages vertically. According to such a stack package, for example, in the case of a semiconductor memory device, a memory capacity of twice as much as a memory capacity that can be realized in a semiconductor integration process It can implement a product having. In addition, since stack packages have advantages in terms of increasing memory capacity and efficiency of mounting density and footprint area, research and development on stack packages are being accelerated.

A stack package can be manufactured by stacking individual semiconductor chips, and then stacking stacked semiconductor chips at once, and stacking individual packaged semiconductor chips. The individual semiconductor chips of the stack package are formed of metal wires or through silicon vias. It is electrically connected through (TSV: Through Silicon Via). In particular, a stack package using through silicon vias is a structure in which through silicon vias are formed in a semiconductor chip so that physical and electrical connections between the semiconductor chips are made vertically by the through silicon vias.

1 illustrates a perspective view of a stack packaged semiconductor integrated circuit.

Referring to FIG. 1, a semiconductor integrated circuit 100 includes a plurality of semiconductor chips 110 to 130 stacked vertically, and a plurality of semiconductor chips 110 to 130 passing through each of the plurality of semiconductor chips 110 to 130. A plurality of through silicon vias 140 to 160 are provided to interface signals, power, and the like. At this time, the plurality of through-silicon vias 140 is provided in a few hundred to thousands. Although not shown in detail in the drawings, the plurality of through silicon vias 140 to 160 provided through the plurality of semiconductor chips 110 to 130 are connected to each other, and the plurality of through silicon vias 140 to 160 are actually connected to each other. ) Bump pads (not shown in the drawing) are provided for electrically connecting the two electrodes.

2 is a plan view of the semiconductor integrated circuit of FIG. 1.

2, a plan view of a semiconductor chip provided at the top of the semiconductor integrated circuit of FIG. 1 will be described. In addition, 24 through silicon vias penetrating the semiconductor chip are provided as an example.

Referring to FIG. 2, a plurality of through silicon vias 140 vertically penetrating the semiconductor chip 110 are disposed in a lattice shape on the semiconductor chip 110. That is, the through silicon vias 140 are disposed to penetrate the semiconductor chip 110 and are arranged at regular intervals.

On the other hand, the plurality of through-silicon vias 140 are spaced apart at regular intervals A to prevent interference between them. The constant distance A refers to a minimum separation distance within a range in which interference phenomenon between neighboring through silicon vias 140 does not occur.

Here, the horizontal length of the semiconductor chip 110 is referred to as 'Z1', and the vertical length is referred to as 'W1', and the space between the through silicon vias 140 adjacent to each other in the oh-and-row direction is referred to as 'A'. When the diameter of the silicon via 140 is 'B', the area SAREA1 of the semiconductor chip 110 is represented by Equation 1 below.

[Equation 1]

Figure pat00001

As such, the grid-like arrangement may minimize the separation distance A of the through-silicon vias 140 adjacent to each other in the oh-and-row directions, but the separation distance C of the adjacent through-silicon vias 140 in the diagonal direction. ) Cannot be the minimum separation distance A (C ≠ A). Therefore, the lattice-shaped arrangement structure is a layout structure having a low space efficiency according to the distance C of the through-silicon vias 140 adjacent to each other in a diagonal direction, and there is a problem in that area loss occurs.

It is an object of the present invention to provide a semiconductor integrated circuit having an optimized area through an efficient arrangement of through silicon vias.

According to an aspect of the invention, the present invention includes a semiconductor chip and a plurality of chip through vias penetrating the semiconductor chip, the plurality of chip through vias are arranged in a plurality of rows at regular intervals in the first axis direction, Two adjacent rows of chip through vias are arranged on different axes in the second axis direction.

According to another aspect of the invention, the present invention comprises a semiconductor chip and a plurality of chip through vias penetrating the semiconductor chip, the plurality of chip through vias are arranged in a plurality of rows at regular intervals in the first axis direction, The chip through vias in the odd row are arranged on the same axis in the second axis direction, and the chip through vias in the even row are arranged on the same axis in the second axis direction, and the chip through vias in the odd row and the even chip through vias The axes formed in the second axis direction are configured differently.

According to another aspect of the present invention, the present invention includes a semiconductor chip and a plurality of chip through vias penetrating the semiconductor chip, wherein the chip through vias adjacent to any first chip through via are selected from the first chip through via. It is configured to form a regular hexagon spaced apart by a predetermined interval about the.

According to the present invention, since a plurality of through-silicon vias penetrating the semiconductor chip are disposed in consideration of space efficiency, unnecessary space of the semiconductor chip is saved, and thus, the overall area of the semiconductor integrated circuit can be expected to be minimized.

1 is a perspective view of a stack packaged semiconductor integrated circuit.
2 is a plan view of the semiconductor integrated circuit of FIG.
3 is a plan view of a semiconductor integrated circuit according to an embodiment of the present invention.
4 is a plan view of a semiconductor integrated circuit for explaining the arrangement of the through-silicon vias of FIG. 3.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

In the embodiment of the present invention, for convenience of description, one semiconductor chip through which a plurality of through silicon vias (TSVs) penetrates is described as an example. However, as shown in FIG. Naturally, it is applied to the circuit.

3 is a planar view of a semiconductor integrated circuit according to an embodiment of the present invention.

Referring to FIG. 3, the semiconductor integrated circuit 200 includes a semiconductor chip 210 and a plurality of through silicon vias 240 penetrating through the semiconductor chip 210.

The semiconductor chip 210 is a conventional silicon substrate provided with various devices (eg, MOS transistors).

The plurality of through-silicon vias 240 serve to interface signals or power supplies between stacked semiconductor chips (not shown). Therefore, the plurality of through silicon vias 240 may be made of a metal having excellent conductivity, such as copper (Cu). The plurality of through silicon vias 240 penetrates the semiconductor chip 210 at least hundreds to as many as thousands. However, in the exemplary embodiment of the present invention, 24 through silicon vias 240 pass through the semiconductor chip 210 for convenience of description.

Such a plurality of through-silicon vias 240 are arranged in a plurality of rows at regular intervals in a first axis direction (hereinafter referred to as the "X-axis direction"), and two adjacent through-vias vias 240 in any two rows are formed in the second row. Arranged on different axes in the axial direction (hereinafter referred to as "Y-axis direction"). In this case, the through-silicon vias 240 disposed on the same axis in the X-axis direction are spaced apart at the first interval D, and the through-silicon vias 240 disposed on the same axis in the Y-axis direction are second. It is arranged spaced apart from the interval (A).

In other words, the plurality of through-silicon vias 240 are arranged in a plurality of rows at regular intervals in the X-axis direction, and the through-silicon vias 240 in the odd-numbered rows are disposed on the same axis in the Y-axis direction, and the even-numbered rows The chip through vias are arranged on the same axis in the Y-axis direction. In this case, the through-silicon vias 240 in the odd-numbered rows and the even-numbered chip light-vias 240 are arranged differently in the Y-axis direction. In addition, the axes formed by the through-silicon vias 240 in the odd-numbered rows and the even-numbered chip light-vias 240 in the Y-axis direction are equally spaced. Accordingly, the through-silicon vias 240 in any odd-numbered rows and the through-silicon vias 240 in even-numbered rows adjacent to the odd-numbered rows are arranged in a zigzag form at equal intervals A. In this case, the equal interval A refers to a minimum separation distance from which interference is prevented between neighboring through silicon vias 240.

Here, the horizontal length of the semiconductor chip 210 is referred to as 'Z2', the vertical length is referred to as 'W2', and the interval between adjacent through silicon vias 240 is referred to as 'A', and each through silicon via 240 is formed. If the diameter of 'B', the area (SAREA2) of the semiconductor chip 210 is as shown in Equation 2 below.

[Equation 2]

Figure pat00002

If the distance A between the adjacent through silicon vias 240 is 50 μm and the diameter B of each through silicon via 240 is 20 μm, the area of the semiconductor chip 210 is determined. (SAREA2) is approximately '81340 µm 2 '. On the other hand, the area SAREA1 of the semiconductor chip 110 according to the related art is approximately '85100 μm 2 ' by Equation 1. Accordingly, it can be seen that the semiconductor chip 210 according to the embodiment of the present invention sees an area gain of approximately 5% compared to the related art. However, the semiconductor chip 210 according to the embodiment of the present invention takes a part of the actual area as an example, and if the total area of the actual semiconductor chip is compared, the area gain will be further improved.

4 is a plan view of a semiconductor integrated circuit for describing the arrangement of the through silicon vias of FIG. 3. In other words, FIG. 4 illustrates the number of through-silicon vias penetrating through one semiconductor chip in a practical manner.

Referring to FIG. 4, the through silicon vias 240 adjacent to any of the through silicon vias 240 are spaced at regular intervals about the through silicon vias 240 to form a regular hexagon. Of course, the through silicon vias 240 disposed adjacent to the edge of the semiconductor chip 210 are not disposed at the center of the through silicon vias 240 forming a regular hexagon, but any other through silicon vias 240 except for the It is disposed at the center of the through-silicon vias 240 forming a regular hexagon.

According to the embodiment of the present invention, by optimizing the arrangement structure of the plurality of through silicon vias to save unnecessary space of the semiconductor chip, there is an advantage that the total area of the semiconductor integrated circuit is minimized.

Although the technical spirit of the present invention has been described in detail with reference to the above embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

200: semiconductor integrated circuit 210: semiconductor chip
240: multiple through silicon vias

Claims (16)

Semiconductor chips; And
A plurality of chip through vias penetrating the semiconductor chip;
The plurality of chip through vias are arranged in a plurality of rows at regular intervals in a first axis direction, and two adjacent rows of chip through vias are disposed on different axes in a second axis direction.
The method of claim 1,
And the first axis direction and the second axis direction are perpendicular to each other.
The method of claim 2,
The chip through vias disposed on the same axis in the first axis direction are spaced apart from each other at a first interval.
The method of claim 2,
The chip through vias disposed on the same axis in the second axis direction are spaced apart from each other by a second interval.
The method according to claim 3 or 4,
The adjacent two chip through vias are arranged in a zigzag form at the second intervals.
The method of claim 5,
And wherein the second gap is a minimum separation distance from which interference is prevented between neighboring chip through vias.
The method according to claim 1 or 2,
The plurality of chip through vias are through silicon vias (TSVs).
Semiconductor chips;
A plurality of chip through vias penetrating the semiconductor chip;
The plurality of chip through vias are arranged in a plurality of rows at predetermined intervals in a first axis direction, chip through vias in odd-numbered rows are disposed on the same axis in a second axis direction, and chip through vias in even-numbered rows are formed in the first axis. A semiconductor integrated circuit disposed on the same axis in two axis directions, wherein the axes formed by the chip through vias in the odd-numbered rows and the chip through light vias in the even-numbered rows are different from each other in the second axis direction.
The method of claim 8,
And the first axis direction and the second axis direction are perpendicular to each other.
The method according to claim 8 or 9,
And an axis formed between the chip through vias in the odd-numbered rows and the chip through light vias in the even-numbered rows in the second axis direction.
The method of claim 8,
And the chip through vias of any odd-numbered rows and the chip through vias of even-numbered columns adjacent to the odd-numbered columns are arranged in a zigzag form at equal intervals. The method of claim 11,
The equidistance is a minimum separation distance from which interference is prevented between neighboring chip through vias.
The method according to claim 8 or 9,
The plurality of chip through vias are through silicon vias (TSVs).
Semiconductor chips;
A plurality of chip through vias penetrating the semiconductor chip;
The chip integrated vias adjacent to any of the first chip through vias are spaced at regular intervals about the first chip through via to form a regular hexagon.
The method of claim 14,
Wherein the predetermined interval is a minimum separation distance from which interference is prevented between neighboring chip through vias. The method according to claim 14 or 15,
The plurality of chip through vias are through silicon vias (TSVs).
KR1020100049584A 2010-05-27 2010-05-27 Semiconductor integrated circuit KR20110130111A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10566370B2 (en) 2017-10-31 2020-02-18 Samsung Electronics Co., Ltd. Image sensing apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10566370B2 (en) 2017-10-31 2020-02-18 Samsung Electronics Co., Ltd. Image sensing apparatus
US10998366B2 (en) 2017-10-31 2021-05-04 Samsung Electronics Co., Ltd. Image sensor and image sensing appartatus

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