KR20080088094A - Stack package - Google Patents

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KR20080088094A
KR20080088094A KR1020070030514A KR20070030514A KR20080088094A KR 20080088094 A KR20080088094 A KR 20080088094A KR 1020070030514 A KR1020070030514 A KR 1020070030514A KR 20070030514 A KR20070030514 A KR 20070030514A KR 20080088094 A KR20080088094 A KR 20080088094A
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South Korea
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package
connection pad
bumps
pads
connection
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KR1020070030514A
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Korean (ko)
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KR100866137B1 (en
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강태민
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주식회사 하이닉스반도체
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Priority to KR1020070030514A priority Critical patent/KR100866137B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A stack package is provided to implement a rapid signal transmission and to reduce the size of a package by using an FPC(Flexible Printed Circuit) board and a dummy silicon wafer. A semiconductor chip is provided with a plurality of bonding pads. A first bump(208) is formed on the respective bonding pads. An FPC board(216) includes a first connection pad, a second connection pad, and a dummy pad. The first connection pad is formed on a position corresponding to the first bump. The second connection pad is formed on a position spaced away from and corresponding to the first connection pad. The dummy pad is formed on a position on the other side of the second connection pad. A dummy silicon wafer(210) is provided with a groove on which the FPC board is received. A plurality of through-electrodes connected to the second connection pads are formed on the dummy silicon wafer. A plurality of second bumps(220a) are interposed between stacked unit packages so as to connect the through-electrodes of an upper unit package to the second connection pads of a lower unit package. A third bump(220b) is interposed between the stacked unit packages at which the second bumps are not interposed so as to support the upper unit package.

Description

스택 패키지{Stack package}Stack package

도 1a 및 도 1b는 종래 스택 패키지를 설명하기 위해 도시한 단면도.1A and 1B are cross-sectional views illustrating a conventional stack package.

도 2는 본 발명의 실시예에 따른 스택패키지를 도시한 단면도.2 is a cross-sectional view showing a stack package according to an embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 스택 패키지를 구현하기 위한 단위 패키지를 설명하기 위하여 도시한 도면. 3 is a view illustrating a unit package for implementing a stack package according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명** Explanation of symbols for the main parts of the drawings *

200 : 반도체 칩 202 : 본딩 패드200: semiconductor chip 202: bonding pad

208 : 제1범프 209 : 접착 부재208: first bump 209: adhesive member

210 : 더미 실리콘 웨이퍼 216 : FPC210: dummy silicon wafer 216: FPC

218 : 관통전극 220a : 제2범프218: through electrode 220a: second bump

220b : 제3범프 222a : 상측 단위 패키지220b: third bump 222a: upper unit package

222a : 하측 단위 패키지 226a : 제1접속 패드222a: lower unit package 226a: first connection pad

226b : 제2접속 패드 226c : 더미 패드226b: second connection pad 226c: dummy pad

H : 홈H: home

본 발명은 스택패키지에 관한 것으로서, 보다 상세하게는, FPC(Flexible Printed Circuit board) 및 더미 실리콘 웨이퍼를 사용하여 빠른 신호 전달의 구현 및 크기를 줄일 수 스택 패키지에 관한 것이다. The present invention relates to a stack package, and more particularly, to a stack package that can reduce the size and implementation of fast signal transfer using a flexible printed circuit board (FPC) and a dummy silicon wafer.

전기·전자 제품이 고성능화되고 전자기기들이 경박단소화됨에 따라 핵심 소자인 패키지의 고밀도, 고실장화가 중요한 문제로 대두되고 있다. 또한, 컴퓨터의 경우 기억 용량의 증가에 따라 대용량의 램(Random Access Memory) 및 플래쉬 메모리(Flash Memory)와 같이 반도체 소자의 용량은 증대되지만, 패키지는 소형화되는 경향으로 연구되고 있어 한정된 크기의 기판에 더 많은 수의 반도체 칩 또는 패키지를 실장하기 위한 여러 가지 기술들이 제안·연구되고 있다. As electrical and electronic products are getting higher performance and electronic devices are lighter and shorter, the high density and high mounting of the package, which is a key element, is becoming an important problem. In addition, in the case of a computer, as the storage capacity increases, the capacity of semiconductor devices, such as a large amount of random access memory (RAM) and flash memory (Flash memory), increases, but the package is being tended to be smaller, so that a limited sized substrate is used. Various techniques for mounting a larger number of semiconductor chips or packages have been proposed and studied.

이러한 고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 용량 증대, 즉, 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다.A method for providing such a high-capacity semiconductor module may include increasing the capacity of the memory chip, that is, high integration of the memory chip, and this high integration may be realized by integrating a larger number of cells in a limited space of the semiconductor chip. Can be.

그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선폭을 요구하는 등의 고난도의 기술과 많은 개발 시간을 필요로 함으로써 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 스택(Stack) 기술이 제안되었다.However, stacking has been proposed as another method for providing a high-capacity semiconductor module because of the high integration of the memory chip, which requires a high level of technology and a lot of development time.

반도체 산업에서 말하는 "스택"이란 적어도 2개 이상의 반도체 칩, 또는 반도체 패키지를 수직으로 적층한 것으로서, 스택 패키지는 메모리 용량 증대와 실장 밀도 및 실장 면적 사용의 효율성 측면 및 단순화된 공정으로 패키지의 제조 단가를 낮출 수 있고 대량 생산이 가능하다는 잇점이 있기 때문에, 이러한 스택 패키지에 대한 연구 및 개발이 가속화되고 있다.The term "stack" in the semiconductor industry refers to a vertical stack of two or more semiconductor chips, or semiconductor packages. The stack package is a manufacturing cost of a package in a simplified process and an increase in memory capacity, mounting density and use of a mounting area. Research and development on these stack packages is accelerating due to the low cost and high volume production advantages.

도 1a 및 도 1b는 종래 스택 패키지를 설명하기 위해 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a conventional stack package.

도시된 바와 같이, 종래 스택 패키지는 2개 이상의 반도체 칩 또는 반도체 패키지가 기판 상에 수직적으로 적층되어 있고, 각 적층된 반도체 칩 또는 반도체 패키지들과 기판은 금속 와이어 또는 연결 부재에 의해 상호 전기적으로 연결되어 있다. As shown, a conventional stack package has two or more semiconductor chips or semiconductor packages stacked vertically on a substrate, and each stacked semiconductor chip or semiconductor packages and the substrate are electrically connected to each other by metal wires or connecting members. It is.

이러한 스택 패키지는 단순화된 공정으로 패키지의 제조 단가를 낮출 수 있고 대량 생산이 가능하다는 등의 잇점이 있는 반면, 적층되는 반도체 칩 또는 반도체 패키지의 수 및 크기 증가에 따라 패키지 내부의 전기적 연결을 위한 배선 공간이 부족하다는 단점이 있다.Such a stack package has advantages such as lower manufacturing cost of the package and mass production in a simplified process, while wiring for electrical connection inside the package according to the increase in the number and size of semiconductor chips or semiconductor packages being stacked. The disadvantage is the lack of space.

도 1a를 참조하면, 다수의 반도체 칩(100a, 100b, 100c)이 기판(104)에 접착제(107)를 매개로 적층된 스택 패키지의 경우, 적층되는 반도체 칩의 수가 증가할수록 상기 반도체 칩들(100a, 100b, 100c)의 본딩 패드(102)들과 기판(104)의 접속 패드(106)들 간의 전기적인 연결을 위한 금속 와이어(108)의 수가 증가하고, 증가된 금속 와이어(108)들 간의 간섭을 피하기 위해 기판(104)에 연결되는 금속 와이어(108)를 수평적으로 또는 수직적으로 형성하기 때문에 금속 와이어(108)들 간의 공간이 증가하여 스택 패키지의 크기가 증가한다.Referring to FIG. 1A, in the case of a stack package in which a plurality of semiconductor chips 100a, 100b and 100c are stacked on a substrate 104 via an adhesive 107, the semiconductor chips 100a are increased as the number of stacked semiconductor chips increases. , The number of metal wires 108 for electrical connection between the bonding pads 102 of 100b, 100c and the connection pads 106 of the substrate 104 increases, and the interference between the increased metal wires 108 increases. Since the metal wires 108 connected to the substrate 104 are formed horizontally or vertically, the space between the metal wires 108 increases, thereby increasing the size of the stack package.

그리고, 본딩 와이어의 스윕(Sweep) 현상 등에 의하여 전기적인 쇼트가 발생할 수 있으며, 긴 본딩 와이어의 길이로 인하여 신호의 전달이 느려지고, 소요 전력이 증가되어 전기적 특성이 나빠진다.In addition, electrical short may occur due to the sweep phenomenon of the bonding wire, and the transmission of the signal is slowed due to the length of the long bonding wire, and the required power is increased, thereby deteriorating the electrical characteristics.

도 1b를 참조하면, 다수의 본딩 패드(102)들에 범프(108)들이 형성된 반도체 칩들(100a, 100b, 100c, 100d)이 전도성 막(112)이 형성된 더미 실리콘 웨이퍼(110)에 부착되어 있고, 상기 전도성 막(112)이 형성된 더미 실리콘 웨이퍼(110)들은 상기 적층된 반도체 칩들(100a, 100b, 100c, 100d)의 공간을 확보하기 위하여 전기적 연결 부재(114)를 매개로 기판(104)에 부착되어 있다.Referring to FIG. 1B, semiconductor chips 100a, 100b, 100c, and 100d having bumps 108 formed on a plurality of bonding pads 102 are attached to the dummy silicon wafer 110 having the conductive film 112 formed thereon. In addition, the dummy silicon wafers 110 having the conductive layer 112 formed thereon are connected to the substrate 104 via an electrical connection member 114 to secure a space of the stacked semiconductor chips 100a, 100b, 100c, and 100d. Attached.

그러나, 반도체 칩들 간을 연결 및 적층을 더미 실리콘 웨이퍼를 이용하여 형성한 스택 패키지의 경우, 추가적인 전기적 연결 수단과 복잡한 패턴 형성 및 재배열이 요구되고, 핸들링(Handling) 및 충격에 취약하다.However, in the case of a stack package formed by connecting and stacking semiconductor chips using dummy silicon wafers, additional electrical connection means, complicated pattern formation and rearrangement are required, and are vulnerable to handling and impact.

본 발명은 FPC(Flexible Printed Circuit board) 및 더미 실리콘 웨이퍼를 사용하여 빠른 신호 전달의 구현 및 크기를 줄일 수 스택 패키지를 제공한다.The present invention provides a stack package that can reduce the size and implementation of fast signal transfer using a flexible printed circuit board (FPC) and a dummy silicon wafer.

본 발명에 따른 스택 패키지는, 다수의 본딩 패드를 구비하고 각 본딩 패드 상에 제1범프가 형성된 반도체 칩과, 상기 각 제1범프와 대응하는 위치에 각각 제1접속 패드가 형성되고 상기 제1접속 패드와 이격된 위치에 대응하는 제1접속 패드와 각각 연결되게 형성된 제2접속 패드 및 상기 제2접속 패드의 타측 이격된 위치에 더미 패드가 형성된 FPC(Flexible Printed Circuits Board)와, 상기 FPC가 안착되는 홈을 구비하고 상기 FPC의 각 제2접속 패드와 각각 연결되는 다수의 관통전극이 형성된 더미 실리콘 웨이퍼를 포함하는 적어도 둘 이상의 단위 패키지가 수적으로 이격해서 스택되고, 상기 스택된 단위 패키지들 사이에서 상측 단위 패키지의 관통전극들과 하측 단위 패키지의 제2접속 패드들을 개별적으로 각각 연결시키도록 다수의 제2범프가 개제되며, 상기 제2범프들이 개재되지 않은 부분의 스택된 단위 패키지들 사이에 상측 단위 패키지를 지지하기 위한 제3범프가 개재된 것을 특징으로 한다.The stack package according to the present invention includes a semiconductor chip having a plurality of bonding pads and having a first bump formed on each bonding pad, and a first connection pad formed at a position corresponding to each of the first bumps, respectively. A second connection pad formed to be connected to a first connection pad corresponding to a position spaced apart from the connection pad, and a flexible printed circuit board (FPC) having a dummy pad formed at a position spaced from the other side of the second connection pad; At least two or more unit packages including a dummy silicon wafer having a groove to be seated and having a plurality of through electrodes connected to each of the second connection pads of the FPC, respectively, are stacked spaced apart from each other, and between the stacked unit packages. A plurality of second bumps are disposed to individually connect the through electrodes of the upper unit package and the second connection pads of the lower unit package to each other. Characterized in that the second bumps are interposed the third bumps for supporting the upper package unit among the units of the stack is not interposed any package.

상기 본딩 패드는 재배선된 것을 특징으로 한다.The bonding pads may be rewired.

상기 재배선은 구리(Cu) 또는 금(Au)으로 이루어진 것을 특징으로 한다.The redistribution is characterized in that consisting of copper (Cu) or gold (Au).

상기 제1접속 패드는 상기 제2접속 패드와 회로 패턴으로 연결된 것을 특징으로 한다.The first connection pad may be connected to the second connection pad in a circuit pattern.

상기 FPC는 상기 더미 실리콘 웨이퍼의 상면에 접착 부재를 매개로 부착된 것을 특징으로 한다.The FPC may be attached to an upper surface of the dummy silicon wafer through an adhesive member.

상기 관통전극은 구리(Cu) 또는 금(Au)으로 이루어진 것을 특징으로 한다.The through electrode is made of copper (Cu) or gold (Au).

상기 제2 및 제3범프는 동일한 크기를 가지고, 상기 반도체 칩의 두께보다 두꺼운 수직 두께를 갖는 것을 특징으로 한다.The second and third bumps have the same size and have a vertical thickness thicker than that of the semiconductor chip.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예에 대해 첨부된 도면을 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 다수의 접속 패드를 구비한 FPC(Flexible Printed Circuits Board)와 더미 실리콘 웨이퍼를 사용하여 경박단소하고 빠른 신호 전달의 구현이 가능한 스택 패키지를 제공한다.SUMMARY OF THE INVENTION The present invention provides a stack package capable of implementing a light and simple signal transmission using a flexible printed circuit board (FPC) having a plurality of connection pads and a dummy silicon wafer.

자세하게, 본 발명은 공지된 방법으로 재배선되고 상기 재배선된 본딩 패드 상에 제1범프를 구비한 반도체 칩과, 상기 반도체 칩이 부착되고 일측에 TSV(Through Silicon Via) 형성 기술을 이용하여 내부를 관통하는 관통전극이 형성된 더미 실리콘 웨이퍼 및 상기 반도체 칩의 제1범프와 더미 실리콘 웨이퍼의 관통전극을 전기적으로 연결하는 다수의 접속 패드를 구비한 FPC로 구성된 적어도 2개 이상의 단위 패키지를 형성한다.In detail, the present invention uses a semiconductor chip that is redistributed by a known method and provided with a first bump on the redistributed bonding pad, and the semiconductor chip is attached to one side of the substrate using a through silicon via (TSV) forming technique. At least two unit packages including a dummy silicon wafer having through electrodes formed therethrough and a plurality of connection pads electrically connecting the first bumps of the semiconductor chip and the through electrodes of the dummy silicon wafer are formed.

그리고, 상기 단위 패키지들 중 상부에 위치하는 단위 패키지의 관통전극과 하부에 위치하는 단위 패키지에 구비된 FPC의 접속 패드를 제2범프를 이용하여 전기적으로 연결하고, 상기 범프의 타측에 상기 상부에 위치하는 단위패키지를 지지하기 위한 제3범프를 형성하여 스택 패키지를 구현한다.The connection pads of the FPC provided in the unit package disposed below and the through electrode of the unit package positioned above the unit package are electrically connected to each other using a second bump, and the other side of the bump is connected to the upper side. The stack package is implemented by forming a third bump to support the unit package located therein.

따라서, 종래 금속 와이어를 사용하는 스택 패키지에 비해 전기적인 연결 길이를 짧게 하여 패키지의 크기를 줄일 수 있고, 빠른 신호 전달을 구현할 수 있다. Therefore, compared with the stack package using the conventional metal wire, the electrical connection length can be shortened, thereby reducing the size of the package and implementing fast signal transmission.

그리고, 더미 실리콘 웨이퍼를 사용함으로써, 그리고, 반도체 칩과 실리콘의 열팽창 계수 차이가 크기 않아 패키지의 휨(Warpage)를 최소화할 수 있음으로써 스택 패키지의 구조적 신뢰성을 향상시킬 수 있다.In addition, by using the dummy silicon wafer and by minimizing the thermal expansion coefficient difference between the semiconductor chip and the silicon, the warpage of the package can be minimized, thereby improving the structural reliability of the stack package.

여기서, 상기 FPC(Flexible Printed Circuits Board)는 연성 회로 기판이라고 불리며, 동박의 정밀 에칭으로 형성된 회로를 절연특성이나 내열성이 뛰어난 폴리이미드 필름을 사용하여 샌드위치 구조로 형성한 기판으로서, 전자제품이 소형화 및 경량화가 되면서 개발된 전자부품으로 유연성, 굴곡성, 내약품성 및 내열성이 우수하고 작업성이 뛰어나 대부분의 전자제품에 핵심부품으로 사용된다. Here, the FPC (Flexible Printed Circuits Board) is a flexible circuit board, a substrate formed by sandwiching the circuit formed by precise etching of copper foil using a polyimide film having excellent insulation properties or heat resistance, and the electronics are miniaturized and It is an electronic component developed while being light in weight, and it is used as a core part in most electronic products due to its excellent flexibility, flexibility, chemical resistance, heat resistance, and excellent workability.

도 2는 본 발명의 실시예에 따른 스택패키지를 도시한 단면도이고, 도 3은 본 발명의 실시예에 따른 스택 패키지를 구현하기 위한 단위 패키지를 설명하기 위 하여 도시한 도면이다. 2 is a cross-sectional view showing a stack package according to an embodiment of the present invention, Figure 3 is a view showing a unit package for implementing a stack package according to an embodiment of the present invention.

도 2 및 도 3을 참조하면, 본 발명에 따른 스택 패키지는 적어도 2개 이상의 단위 패키지가 범프를 매개로 적층되어 형성된다. 2 and 3, a stack package according to the present invention is formed by stacking at least two or more unit packages through bumps.

여기서, 상기 단위 패키지(222a, 222b)는 공지된 방법으로 재배선된 다수의 본딩 패드(202) 및 상기 본딩 패드들(202)에 형성된 제1범프(208)를 구비한 반도체 칩(200)이 TSV(Through Silicon Via) 형성 기술로 일측에 내부를 관통하는 다수의 관통전극(218)을 구비한 더미 실리콘 웨이퍼(210)의 상면에 다수의 접속 패드 (226a, 226b)를 구비한 FPC(Flexible Printed Circuits Board : 216)를 매개로 전기적으로 연결되어 구성된다. Here, the unit packages 222a and 222b may include a semiconductor chip 200 having a plurality of bonding pads 202 rearranged by a known method and a first bump 208 formed on the bonding pads 202. Flexible printed via having a plurality of connection pads 226a and 226b on the top surface of the dummy silicon wafer 210 having a plurality of through electrodes 218 penetrating therein through TSV (Through Silicon Via) forming technology. Circuits Board: 216) is electrically connected.

이때, 상기 반도체 칩(200)의 재배선 및 상기 더미 실리콘 웨이퍼(210)의 관통전극(218)는 구리(Cu) 또는 금(Au)을 사용한 도금 공정으로 형성되고, 상기 더미 실리콘 웨이퍼(210)의 상면에는 상기 FPC(216)의 면적보다 넓은 면적의 홈(H)이 형성되어 있으며, 상기 홈(H) 내에는 상기 FPC(216)가 접착 부재(209)를 매개로 부착된다.At this time, the redistribution of the semiconductor chip 200 and the through electrode 218 of the dummy silicon wafer 210 are formed by a plating process using copper (Cu) or gold (Au), and the dummy silicon wafer 210 A groove H having an area larger than that of the FPC 216 is formed on an upper surface of the FPC 216, and the FPC 216 is attached to the groove H via the adhesive member 209.

그리고, 상기 FPC(216)에는 상면에 상기 반도체 칩(200)의 본딩 패드(202)에 형성된 제1범프(208)와 대응하는 위치에 상기 반도체 칩(200)과의 전기적인 연결을 위한 제1접속 패드(226a)가 구비되어 있고, 상기 본딩 패드(202)에 형성된 제1범프(208)가 상기 FPC(216)에 구비된 제1접속 패드(226a)에 부착됨으로써 전기적으로 연결된다. The FPC 216 has a first surface for electrically connecting to the semiconductor chip 200 at a position corresponding to the first bump 208 formed on the bonding pad 202 of the semiconductor chip 200. The connection pad 226a is provided, and the first bump 208 formed on the bonding pad 202 is electrically connected to the first connection pad 226a provided on the FPC 216.

또한, 상기 FPC(216)에는 상기 제1접속 패드(226a)와 이격된 위치, 즉, 상기 더미 실리콘 웨이퍼(210)의 관통전극(218)과 대응하는 위치에 상기 제1접속 패드(226a) 및 회로 패턴(228)으로 개별 연결되고 상기 관통전극(218)들과 전기적으로 연결되는 제2접속 패드(226b)가 구비되어 있으며, 상기 제2접속 패드(226b)의 타측 이격된 위치에 더미 패드(226c)가 형성되어 있다. 따라서, 상기 반도체 칩(200)과 상기 더미 실리콘 웨이퍼(210)의 관통전극(218)과 전기적으로 연결된다. In addition, the FPC 216 has the first connection pad 226a at a position spaced apart from the first connection pad 226a, that is, at a position corresponding to the through electrode 218 of the dummy silicon wafer 210. The second connection pads 226b are individually connected to the circuit patterns 228 and electrically connected to the through electrodes 218, and the dummy pads are disposed at positions spaced apart from each other of the second connection pads 226b. 226c) is formed. Therefore, the semiconductor chip 200 and the through electrode 218 of the dummy silicon wafer 210 are electrically connected to each other.

한편, 상술한 상기 2개 이상의 단위 패키지(222a, 222b)를 적층하여 형성된 스택 패키지는 상부에 위치하는 상측 단위 패키지(222a)의 관통전극(218)과 상기 상측 단위 패키지의 하부에 위치하는 하측 단위 패키지(222b)의 제2접속 패드(222b) 간을 제2범프(220a)를 사용해 전기적으로 연결하고, 상기 제2범프(220a)의 타측에 상기 제2범프(220a)와 동일한 크기를 가지는 제3범프(220b)를 상기 더미 패드(2Z26c)에 상에 형성하여 상기 상측 단위 패키지(222a)를 물리적으로 지지하여 형성된다.Meanwhile, the stack package formed by stacking the two or more unit packages 222a and 222b described above includes a through electrode 218 of the upper unit package 222a disposed above and a lower unit positioned below the upper unit package. Electrically connecting the second connection pads 222b of the package 222b using the second bumps 220a and having the same size as the second bumps 220a on the other side of the second bumps 220a. Three bumps 220b are formed on the dummy pad 2Z26c to physically support the upper unit package 222a.

그리고, 상술한 바와 동일한 구조의 단위 패키지를 제2 및 제3범프를 매개로 다수 적층하여 스택 패키지가 구현된다. In addition, a stack package is implemented by stacking a plurality of unit packages having the same structure as described above via the second and third bumps.

여기서, 상기 제2 및 제3범프(220a)는 상기 제1범프(208)보다 수직적으로 두께운 두께를 가지며, 상기 제2 및 제3범프(220a)는 상기 반도체 칩(200)의 두께보다 수직적으로 두께운 두께를 가진다. Here, the second and third bumps 220a have a thickness that is vertically thicker than that of the first bumps 208, and the second and third bumps 220a are perpendicular to the thickness of the semiconductor chip 200. It has a thick thickness.

따라서, 본 발명에 따른 스택 패키지는 금속 와이어가 아닌 범프를 사용하여 전기적으로 연결함으로써 전기적인 연결 길이를 짧게 하여 패키지의 크기를 줄일 수 있고, 빠른 신호 전달을 구현할 수 있다. Therefore, the stack package according to the present invention can reduce the size of the package by shortening the electrical connection length by the electrical connection using a bump rather than a metal wire, it is possible to implement a fast signal transmission.

그리고, 반도체 칩과 열팽창 계수 차이가 크기 않은 더미 실리콘 웨이퍼를 사용하여 스택 패키지를 형성함으로써, 스택 패키지의 휨(Warpage)을 를 최소화할 수 있다. In addition, by forming a stack package using a semiconductor chip and a dummy silicon wafer having a large difference in thermal expansion coefficient, warpage of the stack package may be minimized.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 반도체 칩과, 반도체 칩이 실장되고 내부를 관통하는 관통전극이 형성된 더미 실리콘 웨이퍼와 반도체 칩 및 더미 실리콘 웨이퍼를 전기적으로 연결하는 FPC로 구성된 적어도 2개 이상의 단위 패키지와 상기 단위 패키지들 간을 전기적 및 물리적으로 연결하는 범프로 스택 패키지를 구현한다. As described above, the present invention provides at least two unit packages including a semiconductor chip, a dummy silicon wafer on which the semiconductor chip is mounted and a through electrode penetrating therein, and an FPC electrically connecting the semiconductor chip and the dummy silicon wafer; A stack package is implemented as a bump that electrically and physically connects the unit packages.

따라서, 종래 금속 와이어를 사용하는 스택 패키지에 비해 전기적인 연결 길이를 짧게 하여 패키지의 크기를 줄일 수 있고, 빠른 신호 전달을 구현할 수 있다. Therefore, compared with the stack package using the conventional metal wire, the electrical connection length can be shortened, thereby reducing the size of the package and implementing fast signal transmission.

그리고, 더미 실리콘 웨이퍼를 사용함으로써, 그리고, 반도체 칩과 실리콘의 열팽창 계수 차이가 크기 않아 패키지의 휨(Warpage)를 최소화할 수 있음으로써 스택 패키지의 구조적 신뢰성을 향상시킬 수 있다.In addition, by using the dummy silicon wafer and by minimizing the thermal expansion coefficient difference between the semiconductor chip and the silicon, the warpage of the package can be minimized, thereby improving the structural reliability of the stack package.

Claims (7)

다수의 본딩 패드를 구비하고 각 본딩 패드 상에 제1범프가 형성된 반도체 칩과, 상기 각 제1범프와 대응하는 위치에 각각 제1접속 패드가 형성되고 상기 제1접속 패드와 이격된 위치에 대응하는 제1접속 패드와 각각 연결되게 형성된 제2접속 패드 및 상기 제2접속 패드의 타측 이격된 위치에 더미 패드가 형성된 FPC(Flexible Printed Circuits Board)와, 상기 FPC가 안착되는 홈을 구비하고 상기 FPC의 각 제2접속 패드와 각각 연결되는 다수의 관통전극이 형성된 더미 실리콘 웨이퍼를 포함하는 적어도 둘 이상의 단위 패키지가 수적으로 이격해서 스택되고,A semiconductor chip having a plurality of bonding pads and having a first bump formed on each bonding pad, and a first connection pad formed at a position corresponding to each of the first bumps, respectively, and corresponding to a position spaced apart from the first connection pad. A second connection pad formed to be connected to each of the first connection pads, a flexible printed circuits board (FPC) having dummy pads formed at positions spaced from the other side of the second connection pads, and a groove in which the FPC is seated; At least two or more unit packages including a dummy silicon wafer having a plurality of through electrodes connected to respective second connection pads of the plurality of through electrodes, 상기 스택된 단위 패키지들 사이에서 상측 단위 패키지의 관통전극들과 하측 단위 패키지의 제2접속 패드들을 개별적으로 각각 연결시키도록 다수의 제2범프가 개제되며, A plurality of second bumps are disposed between the stacked unit packages to individually connect the through electrodes of the upper unit package and the second connection pads of the lower unit package, respectively. 상기 제2범프들이 개재되지 않은 부분의 스택된 단위 패키지들 사이에 상측 단위 패키지를 지지하기 위한 제3범프가 개재된 것을 특징으로 하는 스택 패키지. And a third bump interposed between the stacked unit packages of the portion where the second bumps are not interposed to support the upper unit package. 제 1 항에 있어서,The method of claim 1, 상기 본딩 패드는 재배선된 것을 특징으로 하는 스택 패키지. And the bonding pads are rearranged. 제 2 항에 있어서,The method of claim 2, 상기 재배선은 구리(Cu) 또는 금(Au)으로 이루어진 것을 특징으로 하는 스택 패키지. The redistribution is a stack package, characterized in that consisting of copper (Cu) or gold (Au). 제 1 항에 있어서,The method of claim 1, 상기 제1접속 패드는 상기 제2접속 패드와 회로 패턴으로 연결된 것을 특징으로 하는 스택 패키지. The first connection pad is a stack package, characterized in that connected to the second connection pad in a circuit pattern. 제 1 항에 있어서,The method of claim 1, 상기 FPC는 상기 더미 실리콘 웨이퍼의 상면에 접착 부재를 매개로 부착된 것을 특징으로 하는 스택 패키지. The FPC stack package, characterized in that attached to the upper surface of the dummy silicon wafer via an adhesive member. 제 1 항에 있어서,The method of claim 1, 상기 관통전극은 구리(Cu) 또는 금(Au)으로 이루어진 것을 특징으로 하는 스택 패키지. The through electrode is a stack package, characterized in that made of copper (Cu) or gold (Au). 제 1 항에 있어서,The method of claim 1, 상기 제2 및 제3범프는 동일한 크기를 가지고, 상기 반도체 칩의 두께보다 두꺼운 수직 두께를 갖는 것을 특징으로 하는 스택 패키지. And the second and third bumps have the same size and have a vertical thickness thicker than the thickness of the semiconductor chip.
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Cited By (3)

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US8680667B2 (en) 2011-08-17 2014-03-25 Samsung Electronics Co., Ltd. Semiconductor devices, package substrates, semiconductor packages, package stack structures, and electronic systems having functionally asymmetric conductive elements
US8698301B2 (en) 2011-10-25 2014-04-15 Samsung Electronics Co., Ltd. Semiconductor packages including a plurality of upper semiconductor devices on a lower semiconductor device
CN113314472A (en) * 2021-04-20 2021-08-27 中国科学院声学研究所 System-on-chip based on FPC substrate

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US9196549B2 (en) * 2013-12-04 2015-11-24 United Microelectronics Corp. Method for generating die identification by measuring whether circuit is established in a package structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8680667B2 (en) 2011-08-17 2014-03-25 Samsung Electronics Co., Ltd. Semiconductor devices, package substrates, semiconductor packages, package stack structures, and electronic systems having functionally asymmetric conductive elements
US8981581B2 (en) 2011-08-17 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor devices, package substrates, semiconductor packages, package stack structures, and electronic systems having functionally asymmetric conductive elements
US8698301B2 (en) 2011-10-25 2014-04-15 Samsung Electronics Co., Ltd. Semiconductor packages including a plurality of upper semiconductor devices on a lower semiconductor device
US8963308B2 (en) 2011-10-25 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages including a plurality of upper semiconductor devices on a lower semiconductor device
CN113314472A (en) * 2021-04-20 2021-08-27 中国科学院声学研究所 System-on-chip based on FPC substrate

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