KR20110004166A - Interconnection structure, cell structure and semiconductor device comprising the interconnection structure and the cell structure - Google Patents

Abstract

PURPOSE: A wiring structure, a cell structure, and a semiconductor device including the same are provided to space first landing pads, connection films, and second patterns from plugs by including outer spacers between the first landing pads, the connection films, the second patterns, and the plugs. CONSTITUTION: A semiconductor substrate(5) comprises an inactive region(14) and an active region(18). A first landing pad(46) and a second landing pad(48) are arranged on the active region. A lower insulating film(42) is arranged between the first landing pad and the landing pad. The lower insulating film surrounds the first landing pad and the sidewall of a connection film(55). An outer spacer(78) is arranged at the sidewall of the second pattern(76).

Description

Wiring structure and cell structure, and a semiconductor device including the same {Interconnection Structure, Cell Structure And Semiconductor Device Comprising The Interconnection Structure And The Cell Structure}

Embodiments relate to a semiconductor device, and more particularly, to a wiring structure and a cell structure, and a semiconductor device including the same.

Generally, a semiconductor device, for example DRAM, has bit line patterns, gate patterns and information storage elements on a semiconductor substrate. The semiconductor substrate has inactive regions and active regions. The inactive area defines active areas. The bit line patterns and the gate patterns are disposed on the inactive region and the active regions. The bit line patterns and the gate patterns are arranged to cross each other to increase the degree of integration of the semiconductor device.

The bit line patterns and gate patterns input data to or output data from information storage elements. The information storage elements are disposed on the bit line patterns and the gate patterns. In this case, the information storage elements are electrically connected to the semiconductor substrate through plugs located between the bit line patterns and the gate patterns. As the degree of integration of the semiconductor device increases, the plugs have a smaller and smaller space occupancy on the semiconductor substrate.

The plugs may contact the bitline patterns and / or the peripheral structure of the bitline patterns. In this way, the information storage elements can be electrically shorted to the bit line patterns and / or the peripheral structure of the bit line patterns via plugs.

SUMMARY An object to be solved according to embodiments is to provide a semiconductor device suitable for preventing electrical shorts between plugs and bitline patterns under information storage elements or between peripheral structures of plugs and bitline patterns. have.

As a means for solving the above problems, embodiments provide a semiconductor device including outer spacers that contact the sidewalls of the bitline patterns and extend below the bottom surface of the bitline patterns from the sidewalls of the bitline patterns.

The wiring structure according to the embodiments may include a pattern and first outer spacers. The patterns may be disposed on the semiconductor substrate and have a large size of the width of the upper side and the width of the lower side. The first outer spacers may be disposed on one sidewall of the upper side of the pattern. The first outer spacer may pass through a bottom surface of the lower side of the pattern to be spaced apart from the lower side of the pattern.

According to selected embodiments, the wiring structure may further include a landing pad and a connection layer that are sequentially disposed below the pattern. The landing pad and the connection layer may have conductivity. The landing pad may be in contact with the semiconductor substrate. The first outer spacer may surround the landing pad through the connection layer. The pattern may be electrically connected to the semiconductor substrate through the landing pad and the connection layer.

According to selected embodiments, the wiring structure may further include a second outer spacer and an inner spacer. The second outer spacers may be disposed on the other sidewall of the upper side of the pattern. The second outer spacers may have the same structure as the first outer spacers. The inner spacer may surround the lower side of the pattern. The first and second outer spacers may surround the one side wall and the other side wall of the upper side of the pattern, and a portion of the bottom surface of the upper side.

In example embodiments, the wiring structure may further include an isolation pattern and an insulating layer. The isolation pattern may be positioned on the connection layer to define the pattern, the first and second outer spacers, and the inner spacer. The insulating layer may be disposed under the isolation pattern to surround sidewalls of the connection layer and the landing pad. The pattern may have a conductive pattern and an insulating pattern through the lower side and the upper side.

The cell structure according to embodiments may include a first pattern, outer spacers, and an isolation pattern. The first pattern is disposed on the active region and may have a large size of the width of the upper side and the width of the lower side. The outer spacers may be disposed on sidewalls of the upper side of the first pattern. The outer spacers may surround the lower side of the first pattern to be spaced apart from the lower side of the first pattern. The isolation pattern may be disposed below the upper side of the first pattern and disposed between the first pattern and the outer spacers.

According to selected embodiments, the cell structure may further include a connection layer, a first landing pad, a second landing pad, a second pattern, and a plug. The connection layer may contact the lower side of the first pattern under the isolation pattern. The first landing pad may be disposed under the connection layer. The second landing pad may be disposed around the first landing pad. The second pattern may be disposed between the first and second landing pads. The plug may be positioned on the second landing pad and in contact with the second landing pad. The first and second landing pads may be electrically connected to the active region. The first and second landing pads may be conductive together with the connection layer and the plug. The upper surface of the second pattern may be located at a level lower than the upper surface of the connection layer.

In example embodiments, the cell structure may further include an inner spacer and an insulating layer. The inner spacer may be disposed between the isolation pattern and the first pattern to surround the lower side of the first pattern. The insulating layer may surround the first and second landing pads, the connection layer, and the second pattern. Each of the first and second patterns may be a conductive pattern and an insulating pattern that are sequentially stacked. The inner and outer spacers may define the isolation pattern. The selected one of the outer spacers may contact the upper surface of the second pattern.

The semiconductor device according to embodiments may include active regions, inactive regions, first patterns, outer spacers, and isolation patterns. The active region may be disposed on a semiconductor substrate. The inactive region may define the active regions in the semiconductor substrate. The first patterns may have a larger width than the width of the lower side and a width of the upper side in the central region of the active regions. The first patterns may have a width different from that of the upper side on the inactive region. The outer spacers may be located on sidewalls of the upper side of the first patterns. The outer spacers may extend from the sidewalls on the upper side of the first patterns toward the active regions and the inactive region. The isolation patterns may be disposed between the outer spacers and the first patterns in the central region of the active regions. The isolation patterns may be disposed between the outer spacers in the edge regions of the active regions.

In example embodiments, the semiconductor device may further include second patterns, first landing pads, and second landing pads. The second patterns may be located below the first patterns. The second patterns may cross the first patterns while passing through the active regions and the inactive region. The first landing pads may be disposed under the first patterns while being positioned in the central area of the active areas. The second landing pads may be disposed between the first and second patterns and disposed in the edge regions of the active regions. The outer spacers may contact upper surfaces of the second patterns on the second patterns. The first landing pads may be surrounded by the central area of the active areas between the second patterns. The upper surface of the second landing pads may contact the edge regions of the active regions between the second patterns.

In example embodiments, the semiconductor device may further include connection layers, lower insulating layers, inner spacers, plugs, and an upper insulating layer. The connection layers may be disposed between the first patterns and the first landing pads. The lower insulating layer may expose sidewalls of the first landing pads and the connection layers to expose the second patterns and the second landing pads. The inner spacers may be disposed between the first patterns and the isolation patterns to surround the lower side of the first patterns. The plugs may be positioned between the first and second patterns to contact the second landing pads. The upper insulating layer may be disposed between the plugs. The plugs may contact the outer spacers.

According to the remaining selected embodiments, each of the first and second patterns may be a conductive pattern and an insulating pattern stacked in sequence. The first and second landing pads may contact the active regions. The first and second landing pads may be conductive together with the connection layers and the plugs.

As described above, the embodiments provide a semiconductor device having no electrical short circuit between the plugs and the first landing pads, the plugs and the connecting films, or the plugs and the second patterns. To this end, the semiconductor device includes outer spacers disposed between the first landing pads, the connection layers, the second patterns, and the plugs. The outer spacers may space the first landing pads, the connection layers, and the second patterns from the plugs.

Embodiments may be applied to semiconductor devices other than DRAM. For example, a semiconductor device other than the DRAM may have an outer spacer according to embodiments between a landing pad, a pattern located on the landing pad, a landing pad, and a conductor located around the pattern. The semiconductor device may include a volatile memory device or a nonvolatile memory device.

Aspects of the above embodiments will now be described with reference to the accompanying drawings. However, the above embodiments may be embodied in many different forms and should not be construed as limited to the aspects set forth herein. Rather, the above aspects make the embodiments more thorough and complete, and fully convey the scope of the embodiments to those skilled in the art. Although terms referring to first, second, etc. may be used herein to describe various components, it will be understood that the components are not limited to these terms. These terms are only used to distinguish one component from another.

As used herein, the term 'pattern' may be used to describe the results that can be obtained during the performance of a semiconductor manufacturing process selected on a desired film in a semiconductor manufacturing line. And, particularly relative terms such as "bottom, top, optional, part, below, on" and the like simply describe the relative relationship between the selected component, another component with a shape, or the shape shown in the figures. The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the embodiments.

Now, a semiconductor device according to embodiments will be described with reference to FIGS. 1 and 2.

1 is a plan view illustrating a semiconductor device according to example embodiments.

Referring to FIG. 1, first patterns 36 may be prepared according to embodiments. The first patterns 36 may be disposed parallel to each other. Each of the first patterns 36 may have the same width along the length direction. The first patterns 36 may be arranged at the same pitch. Each of the first patterns 36 may be a gate pattern. Second patterns 76 that cross the first patterns 36 may be prepared. The second patterns 76 are orthogonal to the first patterns 36. The second patterns 76 may be disposed parallel to each other.

Each of the second patterns 76 may have first and second widths W1 and W2 along the length direction. The first width W1 has a smaller size than the second width W2. The second patterns 76 may be arranged at the same pitch. Each of the second patterns 76 may be a bit line pattern. Active regions 18 overlapping the second patterns 76 may be prepared. Each of the active regions 18 may have the same width along the length direction. The central region of the active regions 18 intersects with the second patterns 76.

The edge region of the active regions 18 is disposed between the first and second patterns 36, 76. First landing pads 46 may be prepared at intersections of the active regions 18 and the second pattern 76. The first landing pads 46 are disposed in the central region of the active regions 18. Second landing pads 48 are disposed between the first and second patterns 36 and 76. The second landing pads 48 are disposed in the edge region of the active regions 18. Connection holes 66 may be prepared at intersections of the second patterns 76 and the active regions 18.

Plugs 98 overlapping the second landing pads 48 may be prepared. The plugs 98 are disposed between the first and second patterns 36, 76. Each of the plugs 98 may extend from the edge region of the selected active region 18 to the central region of the peripheral active region 18. The plugs 98 together with the active regions 18, the first patterns 36, the first and second landing pads 46 and 48, the connection holes 66 and the second pattern 76. The semiconductor device 100 according to the embodiments may be configured.

As a variation of the embodiments, the active regions 18 may have different widths along the length direction. Each of the first patterns 36 may have different widths in the length direction. The first patterns 36 may have shapes that are repeated in limited regions. In this case, the first patterns 36 may be arranged at different pitches between the defined regions. Each of the second patterns 76 may have the same widths along the length direction.

FIG. 2 is a cross-sectional view showing a semiconductor device taken along the cutting line II ′ in FIG. 1.

Referring to FIG. 2, the semiconductor device 100 according to the embodiments may include inactive regions 14 and active regions 18 in the semiconductor substrate 5. The active regions 18 may be defined as the inactive regions 14 to have a shape as shown in FIG. 1. First and second landing pads 46 and 48 of FIG. 1 may be disposed on the active regions 18. The first and second landing pads 46 and 48 are in contact with the active regions 18. Each of the first landing pads 46 may have a connection layer on an upper surface thereof. The first and second landing pads 46 and 48 may be conductive together with the connection layer.

A lower insulating layer 42 may be disposed between the first and second landing pads 46 and 48. The lower insulating layer 42 may expose sidewalls of the first landing pad 46 and the connection layer 55 to expose the second landing pads 48. In detail, the lower insulating layer 42 may have step differences between the first and second landing pads 46 and 48. Each of the steps of the lower insulating layer 42 may include a lower step difference (LSD) on the inactive region 14 and an upper step difference (USD) on the active region 18.

The upper step may be substantially the same level as the top surface of the connection layer 55. The lower insulating layer 42 corresponding to the upper step may completely surround sidewalls of the first landing pad 46 and the connection layer 55. The lower insulating layer 42 corresponding to the upper step may expose the top surface of the connection layer 55. The lower insulating layer 42 corresponding to the lower step may expose upper surfaces and sidewalls of the second landing pads 48. The second patterns 76 of FIG. 1 may be disposed on the adhesive layer 55.

The second patterns 76 may have a larger size than the width of the lower side and the width of the upper side in the central region of the active regions 18. The width of the upper side of the second patterns 76 may have substantially the same size as the second width W2 of the second patterns of FIG. 1. The second patterns 76 may have substantially the same size as the first width W1 of the second patterns 76 of FIG. 1 on the inactive region 14. The second pattern 76 includes a conductive pattern 72 and an insulating pattern 74 that are sequentially stacked. The conductive pattern 72 may constitute a portion of the upper side of the second patterns 76.

The conductive pattern 72 may contact the connection layer 55. Outer spacers 78 may be disposed on sidewalls of the second patterns 76. The outer spacers 78 may extend from the sidewalls on the upper side of the second patterns 76 toward the inactive region 14 and the active regions 18. The outer spacers 78 may overlap the upper stepped portion of the lower insulating layer 42 in the central region of the active regions 18. The outer spacers 78 may surround the lower side of the second patterns 76 to be spaced apart from the lower side of the second patterns 76.

In this case, the outer spacers 78 may completely surround the connecting film 55 in the central region of the active regions 18 and partially surround the first landing pad 46. The outer spacers 78 may contact upper surfaces of the second landing pads 48 in the edge region of the active regions 18. Isolation patterns 63 may be disposed on the outer spacers 78. The isolation patterns 63 may be disposed between the outer spacers 78 and the second patterns 76 in the central region of the active regions 18.

The isolation patterns 63 may surround the lower side of the second patterns 76 in the central region of the active regions 18. The isolation patterns 63 may include a second pattern in the edge region of the active regions 18. It may be disposed between the outer spacers 78 because it does not surround the lower side of the 76. Inner spacers 69 may be disposed on the isolation patterns 63. The inner spacers 69 may surround lower sides of the second patterns 76. The inner spacers 69 may be spaced apart from the outer spacers 78 and disposed on an upper step of the lower insulating layer 42.

The plugs 98 of FIG. 1 are disposed between the second patterns 76. The plugs 98 may be conductive. The plugs 98 may be in contact with the outer spacers 78. The plugs 98 may be positioned on lower steps of the lower insulating layer 42 to contact the second landing pads 48. An upper insulating layer 84 may be disposed between the plugs 98.

Next, a method of forming a semiconductor device according to embodiments will be described with reference to FIGS. 3 to 10.

3, 5, 7, and 9 are cross-sectional views illustrating a method of forming a semiconductor device, taken along the cutting line I-I 'of FIG. 4, 6, 8, and 10 are cross-sectional views illustrating a method of forming a semiconductor device, taken along cut lines II-II 'and III-III' of FIG.

3 and 4, inactive regions 14 and active regions 18 may be formed on the semiconductor substrate 5 as shown in FIGS. 3 and 4, according to embodiments. The inactive region 14 may be formed to surround the active regions 18. The inactive region 14 may be formed to be filled with an insulating material. Each of the active regions 18 may have the shape of FIG. 1 when viewed in plan view. First patterns 36 passing through the inactive region 14 and the active region 18 may be formed as shown in FIG. 4.

The first patterns 36 may include gate patterns. The first patterns 36 may be formed on the inactive region 14 and the active regions 18. A portion of the first patterns 36 may be formed to have a shape 25 embedded in the inactive region 14 and the active regions 18. Each of the first patterns 36 may include a conductive pattern 32 and an insulating pattern 34 that are sequentially stacked. Lower spacers 38 may be formed on sidewalls of the first patterns 36 as illustrated in FIG. 3. The lower spacers 38 may include an insulating material.

3 and 4, the lower insulating layer 42 may be formed on the inactive region 14 and the active regions 28 to cover the first patterns 36 and the lower spacers 38. The lower insulating layer 42 may include an insulating material. Landing holes 44 may be formed on the lower insulating layer 42 as shown in FIGS. 3 and 4. The landing holes 44 may be formed as shown in FIGS. 3 and 4 to expose the active regions 18 and the lower spacers 38. The landing holes 44 may be formed to expose the active regions 18, the first patterns 36, and the lower spacers 38.

First and second landing pads 46 and 48 may be formed in the landing holes 44 as shown in FIGS. 3 and 4. The first and second landing pads 46 and 48 may be formed to sufficiently fill the landing holes 44. The first and second landing pads 46 and 48 may include a conductive material. 3 and 4, a middle insulating layer 61 may be formed on the lower insulating layer 42 to cover the first and second landing pads 46 and 48. The middle insulating layer 61 may include an insulating material.

5 and 6, connection holes 66 may be formed in the middle insulating layer 61 of FIGS. 3 and 4, as shown in FIGS. 5 and 6, according to embodiments. The connection hole 66 may be formed to expose the first landing pad 46. An inner spacer 69 may be formed on the sidewall of the connection hole 66 as shown in FIGS. 5 and 6. The inner spacers 69 may include an insulating material. 5 and 6, the connection film 55 may be formed on the first landing pad 46 through the connection hole 66.

The connection layer 55 may include a conductive material, for example, metal silicide. Second patterns 76 may be formed on the central insulating layer 61 to fill the connection hole 66 as shown in FIGS. 5 and 6. The second patterns 76 include bit line patterns. The second patterns 76 may have different widths of the upper side in the inactive region 14 and the active regions 18 as shown in FIGS. 1 and 5. The second patterns 76 may have a larger width W2 on the upper side than a width W1 on the lower side in the central region of the active regions 18.

Each of the second patterns 76 includes a conductive pattern 72 and an insulating pattern 74 that are sequentially stacked. The conductive pattern 72 may be formed to contact the connection layer 55. The conductive pattern 72 may be formed on the middle insulating layer 61 while filling the connection hole 66. The conductive pattern 72 may be formed to sufficiently fill the connection hole 66 or partially fill the connection hole 66. The width of the upper side of each of the second patterns 76 may be larger than the width of the first landing pad 46 in the central region of the active region 18.

The lower insulating layer 42 and the middle insulating layer 61 may be etched using the second patterns 76 as an etch mask and the second landing pads 48 as etch buffer layers. In this case, the lower insulating layer 42 and the middle insulating layer 61 may have grooves G as shown in FIGS. 5 and 6 between the second patterns 76. The grooves G may be formed to expose top surfaces and sidewalls of the second landing pads 48. The grooves G may fully expose or partially expose the top surfaces of the second landing pads 48.

Bottom surfaces of the grooves G may be recessed below a top surface of the second landing pads 48 by a predetermined depth D1. The grooves G may not expose the first patterns 36 or expose the first patterns 36. The grooves G may form isolation patterns 63 under the second patterns 76 using the middle insulating layer 61 as shown in FIGS. 5 and 6. Each of the isolation patterns 63 may be formed as shown in FIGS. 5 and 6 to surround the inner spacer 69 in the middle region of the active region 18.

Each of the isolation patterns 63 may cover the top surface of the connection layer in the middle region of the active region 18 together with the inner spacers 69. The isolation patterns 63 may be formed as shown in FIG. 5 to expose the second landing pads 48 in the edge regions of the active regions 18.

7 and 8, the lower insulating layer 42 and the isolation pattern 63 may be isotropically etched through the grooves G of FIGS. 5 and 6, according to embodiments. The bottom surfaces of the grooves G may be further recessed by a predetermined depth D2 below the top surfaces of the second landing pads 48 than the bottom surfaces of the grooves G of FIGS. 5 and 6. The grooves G may expose the first patterns 36 and / or the second landing pads 48. In this case, the sidewalls of the isolation patterns 63 may be moved downward toward the upper side of the second patterns 76 relative to the sidewalls of the isolation patterns 63 of FIGS. 5 and 6.

After the lower insulating layer 42 and the isolation pattern 63 are etched isotropically, each space of the grooves G may be enlarged relative to each of the grooves G of FIGS. 5 and 6. . Outer spacers 78 may be formed on sidewalls of the grooves G as shown in FIGS. 7 and 8. The outer spacers 78 may include an insulating material. The outer spacers 78 may extend toward the inactive regions 14 and / or the active regions 18 past the sidewalls of the upper side of the second patterns 76 and the sidewalls of the isolation patterns 63.

The outer spacers 78 may surround the first landing pad 46 and / or the connection layer 55 on the central region of the active regions 18. The outer spacers 78 may contact the top surfaces of the second landing pads 48 around the inactive region 14 or on the edge region of the active region 18. 7 and 8, an upper insulating layer 84 may be formed to fill the grooves G and cover the second patterns 76. The upper insulating layer 84 may include an insulating material. 7 and 8, the node holes 88 may be formed in the lower insulating layer 42 after passing through the upper insulating layer 84.

The node holes 88 may be formed between the second patterns 76 to overlap with the grooves G, respectively. The node holes 88 may expose the first patterns 36, the second landing pads 48, and the second patterns 76. The node holes 88 may be formed to expose the first patterns 36, the second landing pads 48, the second patterns 76, and the outer spacers 78. Lower and upper insulating layers 42 and 84 may be isotropically etched through the node holes 88.

After the lower and upper insulating layers 42 and 84 are isotropically etched, the bottom surfaces of the node holes 88 are below the top surfaces of the second landing pads 48 compared to the bottom surfaces of the enlarged grooves G. FIG. 7 may be further recessed as shown in FIG. 7 by a predetermined depth D3. In detail, the bottom surfaces of the node holes 88 may be positioned as shown in FIGS. 7 and 8 at a predetermined depth D4 below the top surfaces of the second landing pads 48. The depth D4 of the bottom surfaces of the node holes 88 is a sum of the depths D2 and D3 positioned below the top surfaces of the second landing pads 48.

In this case, the bottom surfaces of the outer spacers 78 may be exposed in the node holes 88 as shown in FIG. 7. The upper insulating layer 84 between the node holes 88 may have an insulation thickness T that does not cause electrical breakdown, as shown in FIG. 8. Through this, the space of each of the node holes 88 may be further enlarged by isotropically etching the lower and upper insulating layers 42 and 84.

9 and 10, the plugs 98 filling the node holes 88 may be formed as shown in FIGS. 9 and 10, according to embodiments. The plugs 98 may include a conductive material. The plugs 98 may be in contact with the second landing pads 48. Each of the plugs 98 may extend from the second landing pad 48 toward the first landing pad 46, as shown in FIG. 1, between the first and second patterns 36, 76. In this case, each of the plugs 98 is spaced apart from the first landing pad 46 and the connection film 55 by the thickness of the lower insulating film 42 and / or the outer spacer 78, as shown in FIGS. 9 and 10. Can be formed.

Meanwhile, as a variation of the embodiments, before the plugs 98 are formed in the node holes 88, upper spacers 94 may be formed on sidewalls of the node holes 88 as shown in FIGS. 9 and 10. It may be. The upper spacers 94 may include an insulating material. The upper spacers 94 may expose top surfaces of the second landing pads 48. The upper spacers 94 may cover the exposed outer spacers 78 in the node holes 88. In this case, the upper spacers 94 may further reinforce the insulating thickness of the upper insulating layer 84 between the node holes 88 physically and / or electrically.

In some embodiments, information storage elements may be further formed on the plugs. The information storage elements may comprise a bottom electrode of a capacitor, for example a storage node. The plugs 98 together with the first patterns 36, the first and second landing pads 46 and 48, the second patterns 76 and the outer spacers 78 are according to embodiments. 100 can be configured.

1 is a plan view illustrating a semiconductor device according to example embodiments.

FIG. 2 is a cross-sectional view of a semiconductor device taken along a cutting line II ′ in FIG. 1.

3, 5, 7, and 9 are cross-sectional views illustrating a method of forming a semiconductor device, taken along the cutting line I-I 'of FIG.

4, 6, 8, and 10 are cross-sectional views illustrating a method of forming a semiconductor device, taken along cut lines II-II 'and III-III' of FIG.

Claims (11)

A pattern disposed on the semiconductor substrate and having a large size of the width of the upper side and the width of the lower side; And A first outer spacer disposed on one sidewall of the upper side of the pattern and spaced apart from the lower side of the pattern and passing through a bottom surface of the lower side of the pattern. The method of claim 1, Further comprising a landing pad and a connection film which are positioned below the pattern and sequentially stacked, The landing pad and the connection film are conductive, the landing pad contacts the semiconductor substrate, the first outer spacer surrounds the landing pad past the connection film, and the pattern is through the landing pad and the connection film. A wiring structure electrically connected to the semiconductor substrate. The method of claim 2, A second outer spacer disposed on the other sidewall of the upper side of the pattern and having the same structure as the first outer spacer; And Further comprising an inner spacer surrounding the lower side of the pattern, And the first and second outer spacers enclose a portion of the one side wall and the other side wall of the upper side of the pattern and a bottom surface of the upper side. The method of claim 3, wherein An isolation pattern positioned on the connection film and defined by the pattern, the first and second outer spacers, and the inner spacer; And An insulating layer disposed under the isolation pattern and surrounding sidewalls of the connection layer and the landing pad, And the pattern has a conductive pattern and an insulating pattern through the lower side and the upper side. A first pattern disposed on the active area and having a large size of the width of the upper side and the width of the lower side; Outer spacers disposed on sidewalls of the upper side of the first pattern and spaced apart from the lower side of the first pattern to surround the lower side of the first pattern; And And an isolation pattern positioned below the upper side of the first pattern and disposed between the first pattern and the outer spacers. The method of claim 5, A connection film contacting the lower side of the first pattern below the isolation pattern; A first landing pad disposed under the connection layer; A second landing pad disposed around the first landing pad; A second pattern disposed between the first and second landing pads; And Further comprising a plug located on the second landing pad and in contact with the second landing pad, The first and second landing pads are electrically connected to the active region, the first and second landing pads are conductive together with the connection film and the plug, and the top surface of the second pattern is compared with the top surface of the connection film. Cell structures located at low levels. The method of claim 6, An inner spacer disposed between the isolation pattern and the first pattern to surround the lower side of the first pattern; And Further comprising an insulating film surrounding the first and second landing pads, the connection film and the second pattern, Each of the first and second patterns is a conductive pattern and an insulating pattern stacked in turn, the inner and outer spacers define the isolation pattern, and a selected one of the outer spacers is in contact with the top surface of the second pattern. Cell structures. Active regions disposed in the semiconductor substrate; An inactive region defining the active regions; First patterns having a larger width than a width of a lower side and a width of an upper side in a central region of the active regions, and having different widths from the upper side on the inactive region; Outer spacers positioned on the sidewalls of the upper side of the first patterns and extending from the sidewalls of the upper side of the first patterns toward the active regions and the inactive region; And And isolation patterns disposed between the outer spacers and the first patterns in the central region of the active regions and between the outer spacers in an edge region of the active regions. The method of claim 8, Second patterns positioned below the first patterns and crossing the first patterns while passing through the active regions and the inactive region; First landing pads positioned in the central area of the active areas and disposed below the first patterns; And Further comprising second landing pads positioned between the first and second patterns and disposed in the edge regions of the active regions, The outer spacers contact the top surfaces of the second patterns on the second patterns, surround the first landing pads in the central region of the active regions between the second patterns, and the second patterns And contact upper surfaces of the second landing pads in the edge region of the active regions therebetween. The method of claim 9, Connection layers disposed between the first patterns and the first landing pads; A lower insulating layer surrounding sidewalls of the first landing pads and the connection layers to expose the second patterns and the second landing pads; Inner spacers disposed between the first patterns and the isolation patterns to surround the lower sides of the first patterns; Plugs positioned between the first and second patterns to contact the second landing pads; And Further comprising an upper insulating film disposed between the plug, And the plugs contact the outer spacers. The method of claim 10, Each of the first and second patterns is a conductive pattern and an insulating pattern stacked in turn, the first and second landing pads contact the active regions, and the first and second landing pads are connected to the connection films and the A semiconductor device conductive with the plugs.

Images