KR20110002978A - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

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Publication number
KR20110002978A
KR20110002978A KR1020090060543A KR20090060543A KR20110002978A KR 20110002978 A KR20110002978 A KR 20110002978A KR 1020090060543 A KR1020090060543 A KR 1020090060543A KR 20090060543 A KR20090060543 A KR 20090060543A KR 20110002978 A KR20110002978 A KR 20110002978A
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South Korea
Prior art keywords
transistor
region
gate electrode
substrate
transistor region
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KR1020090060543A
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Korean (ko)
Inventor
윤경일
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090060543A priority Critical patent/KR20110002978A/en
Publication of KR20110002978A publication Critical patent/KR20110002978A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The present invention has been proposed to solve the above problems of the prior art, to provide a semiconductor device and a method of manufacturing the same that can differentially adjust the transistor (transistor) threshold voltage using a body effect (Body Effect), A semiconductor device according to the present invention includes a substrate on which an isolation layer for separating a plurality of transistor regions is formed; A well region separated by the device isolation film and formed in the surface of the substrate of each transistor region; A gate electrode formed in each transistor region via a gate insulating film; Source / drain regions formed in the substrate surfaces on both sides of the gate electrode; An interlayer insulating film covering an entire surface of the substrate including the gate electrode; A first plug electrically connected to the gate electrode and the source / drain region through the interlayer insulating layer; And a second plug penetrating the interlayer insulating film and connected to the well region of each transistor region, wherein the body effect of the well region is caused by a bias provided to the transistor region from the outside through the second plug. By adjusting the threshold voltage of each transistor region.

Threshold Voltage, Body Effect, Transistor

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, capable of differentially controlling transistor characteristics using a body effect.

In recent years, as the application fields of semiconductor devices are diversified, semiconductor devices, for example, transistors used in chips for improving device performance, have to be formed to have individual characteristics, for example, different threshold voltages. Typically, the threshold voltage of the transistor is adjusted using a method of implanting impurity ions for controlling the threshold voltage on the substrate.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a silicon substrate 11 having three transistor regions A, B, and C is selectively etched to form a trench having a predetermined depth, and an insulating film is formed inside the trench. The device isolation film 12 is formed by being embedded.

As shown in FIG. 1B, after the first photoresist 13 is coated on the silicon substrate 11 on which the device isolation film 12 is formed, the first transistor region A is opened by performing an exposure and development process. The first photoresist 13 is patterned as much as possible. Subsequently, an ion implantation impurity for threshold voltage is implanted into the silicon substrate 11 of the first transistor region A using the patterned first photoresist 13 as a mask.

As shown in FIG. 1C, the first photoresist 13 is removed, the second photoresist 14 is applied onto the silicon substrate 11, and then exposed and developed to perform a second transistor region ( The second photoresist 14 is patterned such that B) is open. Subsequently, using the patterned second photoresist 14 as a mask, the impurities for adjusting the threshold voltage are ionized on the silicon substrate 11 of the second transistor region B so as to have a threshold voltage characteristic different from that of the first transistor region A. FIG. Inject.

As shown in FIG. 1D, the second photoresist 14 is removed, the third photoresist 15 is applied onto the silicon substrate 11, and then exposed and developed to perform a third transistor region ( The third photoresist 15 is patterned to open C). Subsequently, a threshold voltage different from the first transistor region A and the second transistor region B is formed on the silicon substrate 11 of the third transistor region C by using the patterned third photoresist 15 as a mask. Ion implantation of the threshold voltage control impurities to have the characteristics.

As shown in FIG. 1E, the third photoresist 15 is removed, and impurity ions are selectively implanted into the first to third transistor regions A, B, and C to form wells in the surface of the silicon substrate 11. Area 16 is formed. Subsequently, the gate insulating layer 17 and the polysilicon layer are sequentially formed on the silicon substrate 11, and the polysilicon layer and the gate insulating layer 17 are selectively etched through a photo and etching process to form the gate electrode 18. . Then, using the gate electrode 18 as a mask, low concentration impurity ions are implanted into the entire surface of the silicon substrate 11 to form the LDD region 19 in the surface of the silicon substrate 11 on both sides of the gate electrode 18.

As shown in FIG. 1F, an insulating film is deposited on the entire surface of the silicon substrate 11 including the gate electrode 18 and then etched back to form spacers 20 on both sides of the gate electrode 18. Subsequently, a high concentration of source / drain impurity ions are implanted using the spacer 20 and the gate electrode 18 as a mask to form source / drain regions 21 connected to the LDD regions 19 on the surface of the silicon substrate 11. do.

However, in the method of manufacturing a semiconductor device according to the related art, a masking process using a separate mask and a plurality of ion implantation processes are repeatedly performed in order to differentially form characteristics of a plurality of transistors, that is, threshold voltages, in one chip. Since the process staff has to be increased, there is a problem of reducing the price competitiveness of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device capable of differentially controlling a transistor threshold voltage using a body effect and a method of manufacturing the same. .

In accordance with an aspect of the present invention, a semiconductor device includes: a substrate on which an isolation layer for separating a plurality of transistor regions is formed; A well region separated by the device isolation film and formed in the surface of the substrate of each transistor region; A gate electrode formed in each transistor region via a gate insulating film; Source / drain regions formed in the substrate surfaces on both sides of the gate electrode; An interlayer insulating film covering an entire surface of the substrate including the gate electrode; A first plug electrically connected to the gate electrode and the source / drain region through the interlayer insulating layer; And a second plug penetrating the interlayer insulating film and connected to the well region of each transistor region, wherein the body effect of the well region is caused by a bias provided to the transistor region from the outside through the second plug. By adjusting the threshold voltage of each transistor region.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming an isolation layer for separating each transistor region on a substrate in which a plurality of transistor regions are defined; Ion implanting a threshold voltage control impurity on a front surface of a substrate in which each transistor region is defined; Forming a plurality of well regions such that each transistor region is separated by the device isolation film in a surface of a defined substrate; Forming a gate electrode on the substrate on which the transistor region is defined through a gate insulating film; Forming a source / drain region in the substrate surface on both sides of the gate electrode; Forming an interlayer insulating film on the entire surface of the substrate including the gate electrode; And forming a first plug connected to the gate electrode and the source / drain region through the interlayer insulating layer and forming a second plug connected to a well region of each transistor region. The threshold voltage of each transistor region may be adjusted by a body effect of the well region due to a bias provided to each transistor region from the outside through two plugs.

The present invention controls the threshold voltage of each transistor through the electrical control method through the power supply, thereby preventing the increase of the process step by adjusting the threshold voltage through the implant method to reduce the process uncertainty factor due to the process simplification process completion Subsequently, by controlling the characteristics of each transistor by modulating the bias provided to the well region through fuse trimming, the performance of the device may be optimized.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

The present invention described below is a technique for differentially controlling the threshold voltage of each transistor using a body effect of a substrate in a semiconductor device having a plurality of transistors having different threshold voltages, and the conventional impurity ions for adjusting the threshold voltage. Unlike the method of controlling the threshold voltage of a transistor by injection, the technical principle is to control the threshold voltage of each transistor through an electrical signal.

2A to 2C are diagrams illustrating a semiconductor device according to an exemplary embodiment of the present invention, FIG. 2A is a layout diagram, FIG. 2B is a cross-sectional view taken along line AA ′ of FIG. 2A, and FIG. 2C is B of FIG. 2A. It is sectional drawing along the line 'B'. Here, a plurality of N-type transistors capable of adjusting a threshold voltage through an electrical signal are illustrated.

As shown in FIGS. 2A to 2C, the p-type silicon substrate 101 defined by the first to third transistor regions A, B, and C is separated from each transistor region defined by the silicon substrate 101. A gate electrode 105 and a gate electrode 105 formed on the silicon isolation film 102 and the gate insulating film 104 on the silicon substrate 101 of each transistor region separated by the device isolation film 102. LDD region 106 formed on the surface of silicon substrate 101 on both sides, and source / drain region 108 connected to LDD region 106, and formed on the front surface of silicon substrate 101 including gate electrode 105. The first plug 110a electrically connected to the gate electrode 105 and the source / drain region 108 through the interlayer insulating layer 109, the interlayer insulating layer 109, and the interlayer insulating layer 109. Each transistor region is electrically connected to a defined silicon substrate 101 to receive external electricity. It is configured to include a second plug (110b) for adjusting the threshold voltage of the transistor region. In addition, a well region 103 in which impurity ions of the same conductivity type as that of the silicon substrate 101 is implanted is formed in the surface of the silicon substrate 101 of each transistor region by the device isolation film 102, and the second plug ( 110b is connected to the well region 103. In addition, spacers 107 made of an insulating film are formed on both sides of the gate electrode 105. Here, the first plug 110a and the second plug 110b are made of the same conductive film.

The semiconductor device configured as described above forms a well region 103 separated according to the threshold voltage characteristics of each transistor, and sets the well bias to a desired value according to the threshold voltage type and voltage level of the transistor. )do. That is, when the well bias of each transistor region is well picked up through the second plug 110b according to the threshold voltage of each transistor, the well region 103 of each transistor region may have a different voltage level due to a body effect. Can have Through this, it is possible to adjust to have different threshold voltage characteristics for each transistor region.

As such, the present invention controls the threshold voltage of each transistor through an electrical control method through a power supply, thereby preventing an increase in the process step by controlling the threshold voltage through the conventional implant method, thereby reducing the process uncertainty factor due to the process simplification. Can be beaten. In addition, even after the process is completed, the performance of the device may be optimized by controlling the characteristics of each transistor by modulating the bias provided to the well region 103 through a fuse trimming method.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention along the line AA ′ shown in FIG. 2A. Here, a plurality of N-type transistors that can adjust a threshold voltage through an electrical signal are illustrated.

As shown in FIG. 3A, the silicon substrate 101 defined by the three transistor regions A, B, and C is selectively removed to form a trench having a predetermined depth, and an insulating film is embedded in the trench. An isolation layer 102 is formed. Here, three transistors are separated by the device isolation film 102.

As shown in FIG. 3B, impurities for adjusting the threshold voltage are implanted into the entire surface of the silicon substrate 101 on which the device isolation film 102 is formed. In this case, unlike the prior art, the same threshold voltage control impurities are implanted into all three transistor regions.

As illustrated in FIG. 3C, the impurity ions are selectively implanted into the first to third transistor regions A, B, and C to form well regions 103 having a predetermined interval in the surface of the silicon substrate 101. . The well region 103 is implanted with impurity ions having the same conductivity type as the silicon substrate 101. Meanwhile, in the embodiment of the present invention, the p-type silicon substrate 101 is used to implant the p-type impurity ions to form the well region 103.

Subsequently, the gate insulating film 104 and the polysilicon film are sequentially formed on the silicon substrate 101, and the polysilicon film and the gate insulating film 104 are selectively etched through the photolithography and etching processes to form the gate electrode 105. do.

Using the gate electrode 105 as a mask, low concentration n-type impurity ions are implanted into the entire surface of the silicon substrate 101 to form the LDD region 106 in the surface of the silicon substrate 101 on both sides of the gate electrode 105.

As shown in FIG. 3D, an insulating film is deposited on the entire surface of the silicon substrate 1011 including the gate electrode 105 and then etched back to form spacers 107 on both sides of the gate electrode 105.

Subsequently, high concentration n-type impurity ions are implanted using the spacer 107 and the gate electrode 105 as a mask to form a source / drain region 108 connected to the LDD region 106 in the surface of the silicon substrate 101.

As shown in FIG. 3E, an interlayer insulating film 109 is formed on the entire surface of the silicon substrate 101, the surfaces of the gate electrode 105 and the source / drain regions 108, and the first to third transistor regions A are formed. The interlayer insulating layer 109 is selectively etched through a photo and etching process so as to expose the surface of the silicon substrate 101 of B, C), thereby forming contact holes.

Subsequently, a conductive film is deposited on the entire surface of the silicon substrate 101 including the contact hole, and then the metal film is selectively removed through a photo and etching process to the gate electrode 105 and the source / drain region 109 through the contact hole. A second plug electrically connected to the first plug 110a and each well region 103 electrically connected through a contact hole to selectively adjust the threshold voltage of each transistor by electricity applied from the outside (FIGS. 2A and 2B). Reference numeral '110b' of FIG. 2C) is formed simultaneously.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2C illustrate a semiconductor device according to an embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

* Explanation of symbols for the main parts of the drawings

101: silicon substrate 102: device isolation film

103: well region 104: gate insulating film

105: gate electrode 106: LDD region

107: spacer 108: source / drain region

109: interlayer insulating film 110a: first plug

110b: second plug

Claims (4)

A substrate on which an isolation layer for separating a plurality of transistor regions is formed; A well region separated by the device isolation film and formed in the surface of the substrate of each transistor region; A gate electrode formed in each transistor region via a gate insulating film; Source / drain regions formed in the substrate surfaces on both sides of the gate electrode; An interlayer insulating film covering an entire surface of the substrate including the gate electrode; A first plug electrically connected to the gate electrode and the source / drain region through the interlayer insulating layer; And A second plug connected to the well region of each transistor region through the interlayer insulating layer; And controlling the threshold voltage of each transistor region by the body effect of the well region due to a bias provided to the respective transistor regions from outside through the second plug. The method of claim 1, And a plurality of the second plugs connected to a well region of one transistor region. Forming an isolation layer that separates each transistor region on a substrate in which a plurality of transistor regions are defined; Ion implanting a threshold voltage control impurity on a front surface of a substrate in which each transistor region is defined; Forming a plurality of well regions such that each transistor region is separated by the device isolation film in a surface of a defined substrate; Forming a gate electrode on the substrate on which the transistor region is defined through a gate insulating film; Forming a source / drain region in the substrate surface on both sides of the gate electrode; Forming an interlayer insulating film on the entire surface of the substrate including the gate electrode; And Forming a first plug connected to the gate electrode and the source / drain region through the interlayer insulating layer and forming a second plug connected to the well region of each transistor region; And controlling the threshold voltage of each transistor region by the body effect of the well region due to a bias provided to the respective transistor regions from outside through the second plug. The method of claim 3, Forming the second plug, And a plurality of second plugs are connected to a well region of one transistor region.
KR1020090060543A 2009-07-03 2009-07-03 Semiconductor device and method for fabricating the same KR20110002978A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9240408B2 (en) 2012-06-11 2016-01-19 Samsung Electronics Co., Ltd. Integrated circuit device with transistors having different threshold voltages

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9240408B2 (en) 2012-06-11 2016-01-19 Samsung Electronics Co., Ltd. Integrated circuit device with transistors having different threshold voltages

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