KR20090054725A - Method for fabricating semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to improve yield and a characteristic of the device by preventing a leakage current in an SAC(Self Align Contact) fail by not forming a cell channel in a dummy region. A gate line(210) is formed in an upper part of a semiconductor substrate(200) with a device isolation layer(207) defining an active region(205). A spacer(213) is formed in both sides of a gate line. A photosensitive pattern opening the cell region is formed. A cell channel implant process is performed in the cell region by using the photosensitive pattern as a mask. The photosensitive pattern is removed. An interlayer insulating layer is formed in the whole upper part including the gate line. A landing plug contact hole to expose the semiconductor substrate by etching the interlayer insulating layer is formed. The landing plug contact is formed by filling a polysilicon layer in the landing plug contact hole.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device. In particular, it is related with the manufacturing method of the semiconductor element of a dummy area.

Recently, as semiconductor devices are highly integrated, the line width of the gate line is reduced, and the gate line height is increased in consideration of the resistance of the gate line. As a result, the interlayer insulating film cannot be completely buried between the gate line and the gate line due to its high height compared to the gate line width, and the etching area is not fully opened due to the narrow area during the landing plug contact open etching. SAC fail occurs between the landing plug contact and the gate line.

1A and 1B are a layout and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer 107 defining an active region 105 is formed in a semiconductor substrate 100.

Next, the semiconductor substrate 100 of the active region 105 is etched to form a recess (not shown), and the gate conductive layer 110a and the gate hard are formed over the entire region including the recess (not shown). After the mask layer 110b is formed, the gate 110 is formed by patterning the mask layer 110b.

Next, spacers 113 are formed on both sides of the gate line 110.

In this case, the gate line 110 may be formed in a line shape perpendicular to the long axis direction of the active region 105.

Referring to FIG. 1B, a first interlayer insulating layer (not shown) is formed on the entire surface including the gate line 110, and then the landing plug contact hole (not shown) is etched by etching the first interlayer insulating layer (not shown). Form.

Next, a polysilicon layer filling the landing plug contact hole (not shown) is formed and then planarized to form a landing plug contact 115.

Next, the second interlayer insulating layer 120 is formed on the entire surface including the gate line 110 and the landing plug contact 115, and the second interlayer insulating layer 120 is etched to form a bit line contact hole (not shown). To form.

Next, the bit line contact hole (not shown) is buried to form a bit line contact 125.

Next, a bit line 130 is formed to connect with the bit line contact 125.

The bit line 130 may be formed in a line shape perpendicular to the gate line 110.

In this case, the process margin is weak in the dummy region, such that a SAC fail occurs between the landing plug contact and the gate line.

For example, a fail may occur between a landing plug contact connected to a bit line contact and a gate line, such as 'A', and a landing plug contact scheduled to be connected to a storage electrode contact, such as 'B' or 'C'. Fail may occur between the gate and the gate line.

In this case, a fail such as 'B' has a problem in that the dummy bit line voltage VBLP is transferred to the gate line through the channel, causing the turn on voltage of the gate line to drop, thereby degrading the tWR characteristic. there is a problem.

In addition, when a fail such as 'C' is passed through the channel, the dummy bit line voltage VBLP is transferred to the passing gate, thereby increasing the voltage of the passing gate which should be the ground VSS to generate a leakage current. there is a problem.

In the above-described method of manufacturing a semiconductor device according to the related art, a SAC fail occurs between a landing plug contact and a gate line, and the fail does not easily occur, and a margin test is performed with a margin test. There is a problem in that it is difficult to screen through the test because a defect occurs in the package test.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent a cell channel is formed in the dummy region to prevent leakage current during SAC fail, thereby improving the yield and characteristics of the device.

In the manufacturing method of the semiconductor device according to the first embodiment of the present invention,

Forming a gate line on the semiconductor substrate having an isolation layer defining an active region;

Forming spacers on both sides of the gate line;

Forming a photoresist pattern for opening the cell region;

Performing a cell channel implant process on the cell region using the photoresist pattern as a mask;

It characterized in that it comprises a step of removing the photosensitive film pattern,

Forming an interlayer insulating film on the whole including the gate line;

Etching the interlayer insulating film to form a landing plug contact hole exposing the semiconductor substrate;

And filling the landing plug contact hole with a polysilicon layer to form a landing plug contact.

In the manufacturing method of the semiconductor device according to the second embodiment of the present invention,

Forming a gate line on the semiconductor substrate on which the N well region and the P well region are formed;

Forming spacers on both sides of the gate line;

Forming a photoresist pattern for opening the dummy region;

Performing an ion implantation process on the dummy region using the photoresist pattern as a mask;

The method may include removing the photoresist pattern, wherein the ion implantation process includes implanting N-type impurities and P-type impurities into the N well region and the P well region, respectively.

The N-type impurity is any one selected from P, As, and a combination thereof;

The p-type impurity is any one selected from B, BF4, and a combination thereof;

Forming an interlayer insulating film on the whole including the gate line;

Etching the interlayer insulating film to form a landing plug contact hole exposing the semiconductor substrate;

And filling the landing plug contact hole with a polysilicon layer to form a landing plug contact.

The present invention has the effect of preventing the leakage current when the SAC fail between the landing plug contact and the gate line by blocking the passage of the leakage current so that the cell channel is not formed in the dummy region, thereby improving the yield of the device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A and 2B illustrate a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which FIGS. 2A and 2B (iii) show a layout, and (ii) shows X in (iii) above. -The cutting plane according to X '.

Referring to FIG. 2A, an isolation layer 207 defining an active region 205 is formed in a semiconductor substrate 200 having a cell region I and a dummy region II.

Next, the semiconductor substrate 200 of the active region 205 is etched to form a recess (not shown).

Thereafter, the gate conductive layer 210a and the gate hard mask layer 210b are formed on the entire surface including the recess (not shown), and then patterned to form the gate line 210.

The gate conductive layer 210a may be formed of a laminated structure of a gate polysilicon layer and a gate metal layer, and the gate hard mask layer 210b may be formed of a nitride film.

Next, spacers 213 are formed on both sides of the gate line 210.

In this case, the gate line 210 may be formed in a line shape perpendicular to the long axis direction of the active region 205.

Referring to FIG. 2B, a photosensitive film pattern 220 is formed on the dummy region II. Therefore, only the cell region I is opened by the photoresist pattern 220.

Next, a channel implant process is performed on the entire surface including the cell region I and the dummy region II.

Here, the implant process is a process for forming a cell channel. Since the dummy region II is not exposed by the photoresist pattern 220, the cell channel is not formed.

Accordingly, since a cell channel is not formed on the dummy region II and a passage of the leakage current is blocked, a SAC fail can be prevented from occurring.

In this case, in addition to the channel implant process, only a cell region may be opened when the well implant, the landing plug contact, and the C-halo process are performed.

3A and 3B illustrate a method of manufacturing a semiconductor device according to a second embodiment of the present invention, in which FIGS. 3A and 3B (iii) show a layout, and (ii) X in (iii) above. -The cutting plane according to X '.

Referring to FIG. 3A, an isolation layer 307 defining an active region 305 is formed in a semiconductor substrate 300 having a cell region I and a dummy region II.

Next, the semiconductor substrate 300 of the active region 305 is etched to form a recess (not shown).

Thereafter, the gate conductive layer 310a and the gate hard mask layer 310b are formed on the entire surface including the recess (not shown), and then patterned to form the gate line 310.

Here, the gate conductive layer 310a may be formed of a laminated structure of a gate polysilicon layer and a gate metal layer, and the gate hard mask layer 310b may be formed of a nitride film.

Next, spacers 313 are formed on both sides of the gate line 310.

In this case, the gate line 310 may be formed in a line shape perpendicular to the long axis direction of the active region 305.

Referring to FIG. 3B, the photoresist pattern 320 is formed on the cell region I so that only the dummy region II is opened.

Next, an impurity ion implantation process is performed on the semiconductor substrate 300 of the dummy region II to form the impurity region 330.

In this case, in the impurity ion implantation process, it is preferable to implant N-type impurity ions into a substrate on which N-wells are formed and to implant P-type impurity ions into a substrate on which P-wells are formed.

In addition, since the cell region I is not exposed by the photoresist pattern 320, impurity ions are not implanted, which is not a problem in a subsequent cell channel formation process.

Herein, the N-type impurity is preferably any one selected from P, As, and a combination thereof, and the P-type impurity is preferably any one selected from BF2, B, and a combination thereof.

When implanting impurity ions of the same type as the substrate as described above, the cell channel is not formed. Therefore, since the passage of the leakage current on the dummy region II is blocked, it is possible to prevent the occurrence of the SAC fail (Self Aligned Contact Fail).

1 is a layout and a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.

2A and 2B are a layout and a sectional view showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

3A and 3B are a layout and a sectional view showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

<Explanation of Signs of Major Parts of Drawings>

200, 300: semiconductor substrate 205, 305: active region

207 and 307: device isolation layers 210a and 310a: gate conductive layer

210b, 310b: gate hard mask layer 210, 310: gate line

220, 320: photosensitive film pattern

Ⅰ: cell area Ⅱ: dummy area

Claims (6)

Forming a gate line on the semiconductor substrate having an isolation layer defining an active region; Forming spacers on both sides of the gate line; Forming a photoresist pattern for opening the cell region; Performing a cell channel implant process on the cell region using the photoresist pattern as a mask; And Removing the photoresist pattern Method of manufacturing a semiconductor device comprising a. The method of claim 1, Forming an interlayer insulating film over the entire area including the gate line; Etching the interlayer insulating film to form a landing plug contact hole exposing the semiconductor substrate; And Filling the landing plug contact hole with a polysilicon layer to form a landing plug contact Method of manufacturing a semiconductor device further comprising. Forming a gate line on the semiconductor substrate having the N well region and the P well region formed thereon; Forming spacers on both sides of the gate line; Forming a photoresist pattern for opening the dummy region; Performing an ion implantation process on the dummy region using the photoresist pattern; And And removing the photoresist pattern, wherein the ion implantation process implants N-type impurities and P-type impurities into the N well region and the P well region, respectively. The method of claim 3, wherein The N-type impurity is a manufacturing method of a semiconductor device, characterized in that any one selected from P, As and combinations thereof. The method of claim 3, wherein The P-type impurity is a manufacturing method of a semiconductor device, characterized in that any one selected from B, BF4 and combinations thereof. The method of claim 3, wherein Forming an interlayer insulating film over the entire area including the gate line; Etching the interlayer insulating film to form a landing plug contact hole exposing the semiconductor substrate; And Filling the landing plug contact hole with a polysilicon layer to form a landing plug contact Method of manufacturing a semiconductor device further comprising.

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