KR20040058990A - Method of manufacturing a flash memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a flash memory device is provided to restrain the leakage current by compensating etch damage on a junction region without using additional ion-implantation. CONSTITUTION: A semiconductor substrate defined by a cell region having a memory cell array and a peripheral region having a transistor is prepared. A mask is formed on the cell region to selectively expose a junction region of the cell region. By implanting heavily doped impurities into the resultant structure, a heavily doping region is formed in the peripheral region and the etch damage on the exposed junction region of the cell region is simultaneously compensated.

Description

Method of manufacturing a flash memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device capable of suppressing leakage current from occurring at a drain junction for supplying a voltage to a bit line of a selected string in a NAND type flash memory device. It is about.

Unlike NOR flash memory devices, a cell array is connected and operated in the form of a string in a NAND flash memory device.

1 is a layout diagram illustrating a cell array of a general NAND flash memory device. 2 is a cross sectional photograph taken along line II ′ of FIG. 1.

Referring to FIG. 1, device isolation layers 101a defining a plurality of active regions 101 parallel to each other are formed in a predetermined region of the semiconductor substrate 100. The string select line pattern 102s across the device isolation layers 101a and the active regions 101 therebetween, the first to nth word line patterns WP1,..., WPn and the ground select line. The pattern 102g is formed. Impurity regions 107 and 107d in the active region 101 between the string select line pattern 102s, the first to nth word line patterns WP1 to WPn, and the ground select line pattern 102g. 107 s). Here, the impurity region 107d formed on one side of the string select line pattern 102s serves as a drain region of the string select transistor, and the impurity region 107s formed on one side of the ground select line pattern 102g. Serves as the source region of the ground select transistor.

Therefore, a string select transistor is formed at a portion where the string select line pattern 102s and the active region 101 intersect, and a ground select transistor is formed at a portion where the ground select line pattern 102g and the active region 101 intersect. do. Similarly, a cell transistor is formed at a portion where each word line pattern WP1, ..., or WPn and the active region 101 cross each other. As a result, a string consisting of a string select transistor, a plurality of cell transistors, and a ground select transistor connected in series to each active region 101 is formed.

A first interlayer insulating film 104 is formed on the resultant product formed with the string select transistors, the cell transistors, and the ground select transistors. The first interlayer insulating layer 104 is patterned to form common source line contact holes 103 exposing respective source regions (not shown). A conductive film, such as a doped polysilicon film, is formed on the first interlayer insulating film 104 to fill the common source line contact holes 103. The conductive film is patterned to form a common source line 105 covering the common source line contact holes 103. The common source line 105 is electrically connected to the source regions through the common source line contact holes 103.

A planarized second interlayer insulating film is formed on the common source line 105 and the first interlayer insulating film. The second interlayer insulating film and the first interlayer insulating film are successively patterned to form bit line contact holes 108 exposing respective drain regions. Bit line contact plugs are formed in each bit line contact hole 108. A metal film is formed on the entire surface of the resultant bit line contact plugs. The metal film is patterned to form a plurality of bit lines 109 covering the respective bit line contact plugs. The plurality of bit lines 109 cross the first to nth word line patterns WP1,..., WPn.

In the above, in general, as the substrate is lost during the etching process for forming the contact hole 108, the contact hole 108 is formed to the lower end of the previously formed junction (100a in FIG. 2).

Considering that the effective channel length and junction depth of the cell array continue to decrease due to the performance characteristics of the NAND flash memory device, the contact resistance and the junction leakage current due to the etching loss (Junction) The effect of increasing leakage current is a significant problem.

In order to solve this process problem, the plug implant process scheme is applied. The plug ion implantation process is a technology that compensates the concentration and depth of the junction by forming a contact plug in the contact hole and injecting ions into the contact plug bottom using an ion implantation process. have. However, if an ion implantation process is additionally performed for each contact hole forming step, the process step becomes complicated and a process time and cost increase.

Accordingly, in order to solve the above problem, the present invention forms a flash memory cell array in the cell region, forms a contact hole on the junction of the cell region, and then opens the junction of the cell region during the ion implantation process in the peripheral device region. By performing the ion implantation process of the peripheral device region in order to make the ion implantation to compensate for the etching damage generated in the junction of the cell region at the same time, the junction due to the etching damage in the cell region without additional ion implantation process It is an object of the present invention to provide a method of manufacturing a flash memory device capable of compensating for the depth and the impurity concentration, thereby suppressing leakage current and improving process reliability and device electrical characteristics.

1 is a layout diagram illustrating a cell array of a general NAND flash memory device.

FIG. 2 is a cross sectional photograph taken along line II ′ of FIG. 1.

3 is a layout view of a device for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

4A and 4B are characteristic graphs showing depth and concentration characteristics of junctions according to ion implantation energy.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 100a junction

101, 301: active area 102s, 302s: string selection line pattern

102g, 302g: Ground Select Line Pattern 103: Common Source Line Contact Hole

105: common source line 108, 308: bit line contact hole

109: bit lines 307, 307s, 307d: impurity regions

In the method of manufacturing a flash memory device according to an embodiment of the present invention, a flash memory cell array is formed in a cell region, and a semiconductor substrate having various elements including transistors is provided in a peripheral circuit region. Forming a mask in which the junction is exposed and simultaneously compensating for the etching damage generated in the cell region while forming a high concentration impurity region in the peripheral circuit region by high concentration ion implantation.

In the above, the drain region of the string select transistor or the source region of the ground select transistor is exposed to the junction of the cell region. High concentration ion implantation process can inject arsenic or phosphorus

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.

3 is a layout view of a device for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 3, as shown in FIG. 1, device isolation layers (not shown) defining a plurality of active regions 301 parallel to each other are formed in a predetermined region of a semiconductor substrate. Subsequently, the string selection line pattern 302s crossing the active regions 301, the first to nth word line patterns WP1,..., WPn and the ground selection line pattern 302g are formed. Impurity regions 307 and 307d in the active region 301 between the string select line pattern 302s, the first to nth word line patterns WP1 to WPn, and the ground select line pattern 302g. , 307s). Here, the impurity region 307d formed on one side of the string select line pattern 302s serves as a drain region of the string select transistor, and the impurity region 307s formed on one side of the ground select line pattern 302g. Serves as the source region of the ground select transistor.

Accordingly, a string select transistor is formed at a portion where the string select line pattern 302s and the active region 301 intersect, and a ground select transistor is formed at a portion where the ground select line pattern 302g and the active region 301 intersect. do. Similarly, a cell transistor is formed at a portion where each word line pattern WP1, ..., or WPn and the active region 301 intersect. As a result, a string consisting of a string select transistor, a plurality of cell transistors, and a ground select transistor connected in series to each active region 301 is formed.

In the meantime, while the above process is performed in the cell region, a process of manufacturing a transistor for implementing a circuit is also performed in the peripheral device region (not shown). That is, the process applied to both regions is performed with both regions opened, and the process applied only to one region forms a mask in the other region so that the process is applied only to the corresponding region.

In this case, an N + ion implantation process is performed to form a source / drain junction of the transistor in the peripheral device region. In the conventional N + ion implantation process, a mask is formed in the cell region so that the cell region is not completely exposed. An N + ion implantation process was performed.

However, in the present invention, when the N + ion implantation process is performed to form a source / drain junction of the transistor in the peripheral device region, the drain region 307d of the string select transistor of the cell region and the source region of the ground select transistor ( The N + ion implantation process is performed in the state which formed the mask which opens 307s). As a result, a high concentration source / drain junction is formed in the peripheral device region, and the etching damage generated in the drain region 307d of the string select transistor and the source region 307s of the ground select transistor in the cell region is N + ion implantation process. Is compensated for by increasing the impurity concentration and the junction depth. In this manner, the etching damage generated in the drain region 307d and the source region 307s can be suppressed without additionally performing an ion implantation process to compensate for the etching damage, thereby suppressing the leakage current.

5A and 5B are characteristic graphs showing depth and concentration characteristics of junctions according to ion implantation energy.

Referring to FIG. 5A, in order to compensate that the junction depth of the NAND cell array is about 500 to 600 μs, drain in the case of phosphorus (similar characteristics in the case of arsenic implantation) is injected by an N + ion implantation process. The depth and concentration characteristics of the junction, which is composed of impurity regions such as regions or source regions, are shown. As a result of performing ion implantation with each energy, the junction depth can compensate for the junction loss caused by the contact hole forming etching process when the ion implantation energy is 20 keV.

Referring to FIG. 4B, it can be seen that the increase in the junction lateral depth due to the plug ion implantation is insignificant, so that the decrease in the effective channel length of the select transistor does not occur. That is, when the size of the region (308 in FIG. 3) where impurities are implanted during the N + ion implantation process in the drain contact and the source contact of the cell array is less than the overlay margin of each mask process, It is possible to compensate for the junction loss caused by the contact hole forming etching process without degrading the characteristics of the select transistor.

As described above, in the present invention, the ion implantation process of the peripheral device region is performed in the state of opening the junction of the cell region during the ion implantation process in the peripheral device region. The implantation is performed simultaneously, thereby compensating for the depth and impurity concentration of the junction part due to etching damage in the cell region without additional ion implantation process, thereby suppressing leakage current and improving process reliability and device electrical characteristics. You can.

Claims (3)

Providing a semiconductor substrate on which a flash memory cell array is formed in a cell region, and a plurality of elements including transistors are formed in a peripheral circuit region; Forming a mask in the cell region, in which a junction of the cell region is exposed; And And simultaneously compensating for the etching damage generated in the cell region while forming a high concentration impurity region in the peripheral circuit region by the high concentration of ion implantation. According to claim 1, And exposing a drain region of a string select transistor or a source region of a ground select transistor to a junction portion of the cell region. The method of claim 1, The high concentration ion implantation process is a method of manufacturing a flash memory device, characterized in that for implanting arsenic or phosphorus.