KR20110001531A - Semiconductor device in anti fuse, method for repair and method for fabircating the same - Google Patents
Semiconductor device in anti fuse, method for repair and method for fabircating the same Download PDFInfo
- Publication number
- KR20110001531A KR20110001531A KR1020090059097A KR20090059097A KR20110001531A KR 20110001531 A KR20110001531 A KR 20110001531A KR 1020090059097 A KR1020090059097 A KR 1020090059097A KR 20090059097 A KR20090059097 A KR 20090059097A KR 20110001531 A KR20110001531 A KR 20110001531A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive patterns
- fuse
- insulating layer
- semiconductor device
- film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000008439 repair process Effects 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims description 40
- 230000005012 migration Effects 0.000 claims abstract description 52
- 238000013508 migration Methods 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 239000010949 copper Substances 0.000 claims description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 28
- 229910052802 copper Inorganic materials 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 11
- 230000001678 irradiating effect Effects 0.000 claims description 5
- 230000005684 electric field Effects 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 63
- 239000000463 material Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000007664 blowing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Optics & Photonics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor device, and more particularly, to an anti-fuse, a repair method, and a manufacturing method of a semiconductor device using a migration characteristic of a metal.
If any one of a number of cells in a semiconductor memory device fails, it cannot be functioned as a memory and thus is treated as a defective product. However, in spite of a defect occurring only in some cells in the semiconductor memory device, the disposal of the entire semiconductor memory device as a defective product is an inefficient processing method in terms of yield. Therefore, at present, the yield is improved by reviving the entire semiconductor memory device through a repair process in which a defective cell is replaced by using a redundancy cell provided in the semiconductor memory device.
Typically, the fuse is formed by extending a portion of the metal wiring to the fuse unit in the process of forming the metal wiring without forming through a separate process. Recently, fuses are also formed of copper wires as metal wires are formed by using copper (Cu), which has a lower specific resistance than conventional aluminum (Al) or tungsten (W), which can increase signal transmission speed.
1A and 1B show a copper fuse according to the prior art, FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line XX ′ of FIG. 1A.
1A and 1B, a plurality of
Conventionally, after forming a fuse having the above-described structure, a fuse blowing method of cutting the
However, in the prior art, after the repair process, the
The present invention has been proposed to solve the above problems of the prior art, the anti-fuse of the semiconductor device that can prevent the fuse repair failure due to migration in the semiconductor device using a metal having a migration characteristic such as copper as a fuse, An object of the present invention is to provide a repair method and a method of manufacturing the same.
Antifuse of the present invention according to an aspect for achieving the above object, the first and second conductive patterns which are located on the same line on the substrate, spaced apart by a predetermined interval; A first insulating layer covering the first and second conductive patterns and having a fuse box exposing both ends of the first and second conductive patterns facing each other; And a second insulating layer covering the first and second conductive patterns exposed by the fuse box.
The first and second conductive patterns may include metal layers having migration characteristics. Specifically, the first and second conductive patterns may include a copper film.
The thickness of the second insulating layer may be smaller than the thickness of the first insulating layer, and the second insulating layer may include an oxide layer.
According to another aspect of the present invention, a repair method of the present invention includes: covering the first and second conductive patterns and the first and second conductive patterns spaced apart by a predetermined distance from each other on a same line on a substrate, and facing each other; In the anti-fuse comprising a first insulating film having a fuse box for exposing both ends of the first and second conductive patterns and a second insulating film covering the first and second conductive patterns exposed by the fuse box Irradiating a laser on the first and second conductive patterns exposed by the fuse box to remove the second insulating layer on the exposed first and second conductive patterns; And causing migration of the first and second conductive patterns from which the second insulating layer has been removed to electrically connect the first and second conductive patterns.
The electrically connecting the first and second conductive patterns may be performed by forming an electric field between the first and second conductive patterns. Specifically, a positive voltage may be applied to any one of the first and second conductive patterns, and ground or a negative voltage may be applied to any one of the first and second conductive patterns. In this case, the migration may be EM (Electro Migration).
The first and second conductive patterns may include metal layers having migration characteristics. Specifically, the first and second conductive patterns may include a copper film.
The thickness of the second insulating layer may be smaller than the thickness of the first insulating layer, and the second insulating layer may include an oxide layer.
According to another aspect of the present invention, there is provided a method for manufacturing an anti-fuse, including: forming first and second conductive patterns on the same line and spaced apart from each other by a predetermined interval; Forming an insulating layer on the substrate to cover the first and second conductive patterns; And selectively etching the insulating layer to expose both ends of the first and second conductive patterns facing each other, and to form a fuse box such that the insulating layer remains on the exposed surface of the first and second conductive patterns by a predetermined thickness. Steps.
The forming of the fuse box may include forming a first open region such that the insulating film having a predetermined thickness remains on sidewalls of the first and second conductive patterns facing each other by selectively primary etching the insulating film; And selectively etching the insulating layer to expose both ends of the first and second conductive patterns facing each other, so that the insulating layer having a predetermined thickness remains on the exposed upper surfaces of the first and second conductive patterns. And forming a second open region.
The first and second conductive patterns may include metal layers having migration characteristics. Specifically, the first and second conductive patterns may include a copper film.
The insulating film may include an oxide film.
According to another aspect of the present invention, there is provided a method for manufacturing an anti-fuse, including: forming first and second conductive patterns on the same line and spaced apart from each other by a predetermined interval; Forming a first insulating layer on the substrate to cover the first and second conductive patterns; Selectively etching the first insulating layer to form a fuse box exposing both ends of the first and second conductive patterns facing each other; And forming a second insulating layer on the entire surface of the structure including the fuse box.
The first and second conductive patterns may include metal layers having migration characteristics. Specifically, the first and second conductive patterns may include a copper film.
The thickness of the second insulating layer may be smaller than the thickness of the first insulating layer, and the second insulating layer may include an oxide layer.
The present invention based on the above-described problem solving means, by providing a method of repairing anti-fuse and anti-fuse using the metal migration characteristics, thereby essentially the fuse repair failure caused by the metal migration occurring after the repair process of the metal fuse There is an effect that can be prevented.
In addition, by having an insulating film (or a second insulating film) covering the surfaces of the first and second conductive patterns exposed by the fuse box, it is possible to prevent the short between the first and second conductive patterns due to metal migration. It has an effect.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.
The present invention, which will be described later, uses reverse migration characteristics of a metal to prevent a fuse repair failure due to migration in a semiconductor device having a fuse made of a metal having migration characteristics such as copper (Cu). An anti-fuse, a repair method, and a manufacturing method of a semiconductor device are provided.
FIG. 2A is a plan view illustrating an antifuse of a semiconductor device according to a first embodiment of the present invention, and FIG. 2B is a plan view illustrating an antifuse of a semiconductor device according to a second embodiment of the present invention, and FIG. A cross-sectional view taken along the line X-X 'shown in FIG.
As shown in FIGS. 2A to 2C, the antifuse of the present invention may be disposed on the same line on the
The first and second
In addition, the first and second
The
The first insulating
Here, the second insulating
In addition, the second insulating
Antifuse of the present invention having the above-described structure by using the migration characteristics during the repair process, it is possible to prevent the fuse repair failure due to migration that occurs after the repair process in the case of using the metal wiring as a fuse. This will be described in more detail with reference to FIGS. 3A and 3B, which illustrate a repair method using an antifuse of a semiconductor device according to a first embodiment of the present invention.
3A and 3B are cross-sectional views illustrating a repair method using an antifuse of a semiconductor device according to a first embodiment of the present invention.
As shown in FIG. 3A, the first and second
The second insulating
As shown in FIG. 3B, the first and second
For example, as a method of inducing migration of the first and second
As described above, the present invention provides an antifuse and repair method of a semiconductor device capable of performing a repair process using migration characteristics, thereby preventing the occurrence of a fuse repair failure due to migration after the repair process.
In addition, since the second insulating
4A to 4B are cross-sectional views illustrating a method of manufacturing an antifuse of a semiconductor device according to a third embodiment of the present invention. At this time, the process cross-sectional view is shown along the line X-X 'shown in Figure 2a.
As shown in FIG. 4A, first and second
The first and second
Next, an insulating
Next, a first photosensitive film pattern 34 having an
Here, the first
As shown in FIG. 4B, after the first photoresist layer pattern 34 is removed, the line width W5 larger than the interval W1 in which the first and second
Here, the first and second
5A through 5B are cross-sectional views illustrating a method of manufacturing an antifuse of a semiconductor device according to a fourth embodiment of the present invention. At this time, the process cross-sectional view is shown along the line X-X 'cut line shown in Figure 2a.
As shown in FIG. 5A, first and second
The first and second
Next, a first insulating
Next, after the photoresist pattern (not shown) is formed on the first insulating
As shown in FIG. 5B, a second insulating layer 45 is formed on the entire surface of the structure including the
Meanwhile, even when the second insulating layer 45 remains on the
Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.
1a and 1b show a copper fuse according to the prior art;
Fig. 2A is a plan view showing an antifuse of a semiconductor device according to the first embodiment of the present invention.
2B is a plan view illustrating an antifuse of a semiconductor device according to a second exemplary embodiment of the present invention.
FIG. 2C is a cross-sectional view taken along the line X-X 'of FIG. 2A. FIG.
3A and 3B are cross-sectional views illustrating a repair method using antifuse of a semiconductor device according to a first embodiment of the present invention.
4A and 4B are cross-sectional views illustrating a method of manufacturing an antifuse of a semiconductor device according to a third exemplary embodiment of the present invention.
5A and 5B are cross-sectional views illustrating a method of manufacturing an antifuse of a semiconductor device in accordance with a fourth embodiment of the present invention.
* Description of symbols on the main parts of the drawings *
21:
22B: second conductive pattern 23: first insulating film
24: second insulating film 25: fuse box
Claims (23)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20090059097A KR101043741B1 (en) | 2009-06-30 | 2009-06-30 | Semiconductor device in anti fuse, method for repair and method for fabircating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20090059097A KR101043741B1 (en) | 2009-06-30 | 2009-06-30 | Semiconductor device in anti fuse, method for repair and method for fabircating the same |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20110001531A true KR20110001531A (en) | 2011-01-06 |
KR101043741B1 KR101043741B1 (en) | 2011-06-27 |
Family
ID=43610087
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR20090059097A KR101043741B1 (en) | 2009-06-30 | 2009-06-30 | Semiconductor device in anti fuse, method for repair and method for fabircating the same |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR101043741B1 (en) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020066572A (en) * | 2001-02-12 | 2002-08-19 | 삼성전자 주식회사 | Semiconductor device with anti-fuze and method of fabricating the same |
-
2009
- 2009-06-30 KR KR20090059097A patent/KR101043741B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR101043741B1 (en) | 2011-06-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110085564B (en) | Wafer level die size package structure and method of manufacturing the same | |
KR20060134240A (en) | Fuse of semiconductor device and method of forming the same | |
US20110001212A1 (en) | Fuse of semiconductor device and method for fabricating the same | |
US6787878B1 (en) | Semiconductor device having a potential fuse, and method of manufacturing the same | |
KR101043741B1 (en) | Semiconductor device in anti fuse, method for repair and method for fabircating the same | |
KR20110002980A (en) | Fuse in semiconductor device and method for manufacturing the same | |
KR20100044571A (en) | Fuse in the semiconductor device and method for fabricating the same | |
US7888770B2 (en) | Fuse box for semiconductor device and method of forming same | |
KR20070081640A (en) | Semiconductor device and method for fabricating the same | |
KR20120103982A (en) | Fuse pattern and method for manufacturing the same | |
KR100871389B1 (en) | Fuse of semiconductor device and method for forming the same | |
US20060226508A1 (en) | Semiconductor device having patterns for protecting fuses and method of fabricating the semiconductor device | |
KR100702303B1 (en) | Fuse box of semiconductor devices and method for forming the same | |
KR20090070826A (en) | Semiconductor device with fuse and method for manufacturing the same | |
KR20080010995A (en) | Fuse box of semiconductor device and method for forming the same | |
KR100578224B1 (en) | Mtehod for fabricating semiconductor memory device | |
KR20070048404A (en) | Fuse of semiconductor device | |
KR100433845B1 (en) | Method of forming repair redundancy fuse of semiconductor device without damage of semiconductor device | |
KR100998950B1 (en) | Semiconductor device with fuse and method for manufacturing the same | |
KR101110479B1 (en) | Fuse of semiconductor device and method for forming the same | |
KR20070058833A (en) | Semiconductor memory device and method for fabricating the same | |
KR100833588B1 (en) | Method of manufacturing semiconductor device | |
KR101102048B1 (en) | The fuse of semicondutor device and method for fabricating the same | |
KR101033987B1 (en) | Method of repairing semiconductor device | |
KR20110088675A (en) | Fuse in semiconductor device and method for fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
LAPS | Lapse due to unpaid annual fee |