KR20070058833A - Semiconductor memory device and method for fabricating the same - Google Patents

Abstract

A semiconductor memory device is provided to isolate a fuse to be cut its adjacent fuses by forming a fuse window exposing a part of each fuse. A plurality of fuses(222) are formed on a first interlayer dielectric. Second and third interlayer dielectrics are stacked on the plurality of fuses. A plurality of fuse windows(262) are formed on the second and third interlayer dielectrics, exposing a part of each fuse and protecting adjacent fuses in a fuse cutting process. The second interlayer dielectric can be an oxide layer, and the third interlayer dielectric(240) can be a nitride layer. The plurality of fuses can be a straight line type.

Description

Semiconductor memory device and method for manufacturing the same {Semiconductor memory device and method for fabricating the same}

1 is a layout diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

3 is a cross-sectional view of a semiconductor memory device according to another exemplary embodiment of the present invention.

4 is a cross-sectional view taken along the line IV-IV 'of FIG. 3.

5 through 7 are diagrams sequentially illustrating a method of manufacturing a semiconductor memory device according to example embodiments.

<Explanation of symbols on main parts of the drawings>

110, 210: first interlayer insulating film 122, 222: fuse

130, 230: second interlayer insulating film 120, 220: first oxide film

125 and 225: second interlayer insulating film 140, 240: third interlayer insulating film

150, 250: Guard ring 160: 260: Photosensitive film pattern

162, 262: fuse window

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of filtering an external power supply more effectively.

In general, a semiconductor memory device is a fabrication (FAB) process of repeatedly forming a circuit pattern set on a substrate to form cells having integrated circuits, and packaging the substrate on which the cells are formed in chips. It is manufactured by carrying out an assembly process of packaging.

In addition, an electrical die sorting (EDS) process is performed between the fabrication process and the assembly process to examine electrical characteristics of the cells formed on the substrate.

Defective cells may be selected through a process of inspecting electrical characteristics of each cell. Here, the selected defective cells are replaced with a redundancy cell prepared in advance by performing a repair process, so that the defective cells can be normally operated during actual chip operation to improve the yield of the semiconductor memory device.

This repair process is performed by irradiating the laser beam to the wiring part connected to the defective cell and disconnecting it. At this time, the wiring broken by the laser beam is called a fuse, and the dense parts of the fuses are called a fuse area.

Such a fuse region may be formed together when forming a word line or a bit line formed in a cell region of a semiconductor memory device. However, when the fuse is formed on a word line or a bit line that is located relatively lower in the semiconductor memory device as the degree of integration of the semiconductor memory device increases, the etching depth increases during the fuse open process. The conductive layer for the electrode of the metal wiring or the capacitor which is located at is used as the fuse.

However, when cutting a fuse formed of metal by irradiating a laser beam, it may damage adjacent fuses. Such a phenomenon may be intensified as the degree of integration of the semiconductor memory device is increased, thereby reducing the reliability of the repair fail and the semiconductor memory device.

An object of the present invention is to provide a semiconductor memory device that can prevent the by-products scattered during the fuse cutting.

Another object of the present invention is to provide a method of manufacturing such a semiconductor memory device.

The technical problem to be achieved by the present invention is not limited to the above-mentioned problem, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a semiconductor memory device includes a plurality of fuses formed on a first interlayer insulating layer, second and third interlayer insulating layers stacked on a plurality of fuses, And a plurality of fuse windows formed in the second and third interlayer insulating films to expose portions of each fuse and to protect adjacent fuses during fuse cutting.

In accordance with another aspect of the present invention, a method of manufacturing a semiconductor memory device includes forming a plurality of fuses on a first interlayer insulating layer, stacking second and third interlayer insulating layers covering the fuses, Exposing a portion of each fuse to the second and third interlayer insulating films and forming a plurality of fuse windows that protect adjacent fuses when the fuse is cut.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, a semiconductor memory device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout diagram of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

1 and 2, a plurality of fuses 122 are formed on the first interlayer insulating layer 110, and the plurality of fuses 122 are linearly arranged at regular intervals. The fuses 122 are positioned on the same layer as the wiring (not shown) in the cell region and are formed of a metal material.

Second and third interlayer insulating layers 130 and 140 are stacked on the first interlayer insulating layer 110 on which the fuses 122 are formed. In this case, the second interlayer insulating film 130 is an oxide film, and a plurality of oxide films may be stacked according to the structure of the cell region. In an embodiment of the present invention, the first and second oxide films 120 and 125 are stacked. Explain. The third interlayer insulating film 140 is formed of nitride as a passivation film for preventing moisture absorption into the semiconductor memory device.

In the second and third interlayer insulating layers 130 and 140, a plurality of fuse windows 162 exposing portions of the fuses 122 in a straight line form are formed. In more detail, the plurality of fuse windows 162 respectively expose portions of different fuses 122, and the second and third insulating layers 130 and 140 are positioned between the fuse windows 162. .

Therefore, when irradiating a laser beam into the fuse window 162 to cut the fuse 122a, the second and third interlayer insulating films 130 and 140 positioned between the fuse windows 162 serve as a barrier. do. Therefore, by-products generated while the fuse 122a is cut are prevented from being dispersed into the adjacent fuses 122 by the insulating films 130 and 140 made of the oxide film and the nitride film.

In addition, the fuse windows 162 may be arranged in a zigzag form to more secure an area to which the laser beam is irradiated.

In addition, the guard ring 150 is formed around the area where the straight fuses 122 are concentrated. The guard ring 150 is formed in the second interlayer insulating layer 130 formed of a plurality of oxide films, and the semiconductor is formed through the fuse window 162 by forming the fuse window 162 exposing the upper portions of the fuses 122. It is possible to prevent moisture from penetrating into the memory device. The guard ring 150 is composed of contacts 126 connecting the guard ring patterns 124 and 128 and the guard ring patterns 124 and 128 located above and below.

Hereinafter, a semiconductor memory device according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a cross-sectional view of a semiconductor memory device according to another exemplary embodiment of the present invention. 4 is a cross-sectional view taken along the line IV-IV 'of FIG. 3.

3 and 4, a plurality of fuses 222 are formed on the first interlayer insulating layer 210, and the plurality of fuses 222 are formed in a curved shape. In more detail, the plurality of curved fuses 222 may be divided into a wide area A and a dense area B between the fuses 222. That is, the region A having a large pitch between the fuses 222 is a cutting region A in which the laser beam is irradiated to cut the fuse 222. In addition, the area between the fuses is a dense uncut region in which the laser beam is not irradiated. The fuses 222 may be formed on the same layer as the metal wires (not shown) in the cell region.

Second and third interlayer insulating layers 230 and 240 are stacked on the first interlayer insulating layer 210 on which the curved fuses 222 are formed. In the second interlayer insulating film 230, a plurality of oxide films are stacked as in the exemplary embodiment of the present invention, and the third interlayer insulating film 240 is formed of a nitride film as a passivation film.

Fuse windows 262 for exposing a portion of each fuse 222 are formed in the second and third interlayer insulating layers 230 and 240. In more detail, the fuse windows 262 are formed on the cutting area A having a wide pitch between the fuses 222, and each of the fuse windows 262 exposes a portion of the fuse 222, respectively. Accordingly, second and third interlayer insulating layers 230 and 240 are formed between the fuses 222 disposed on the cutting region A having a wide pitch to isolate adjacent fuses 222. Therefore, by-products generated when the laser beam is irradiated for cutting the fuse 222a may be prevented from being distributed to the adjacent fuses 222 by the second and third interlayer insulating layers 230 and 240.

In addition, a guard ring 150 formed of contacts 226 connecting the guard ring patterns 224 and 228 and the upper and lower guard ring patterns 224 and 228 are formed in the second interlayer insulating layer 230. . The guard ring 150 is formed around an area where the fuses 222 are dense, thereby preventing moisture from penetrating into the semiconductor memory device through the fuse window 262.

Hereinafter, a method of manufacturing a semiconductor memory device according to embodiments of the present invention will be described in detail with reference to FIGS. 5 to 7, 3, and 4.

5 through 7 are diagrams sequentially illustrating a method of manufacturing a semiconductor memory device according to example embodiments.

First, as shown in FIG. 5, a metal material is deposited on the first interlayer insulating layer 210 and then patterned to form fuses 222. In this case, the fuses 222 are formed together with metal wires (not shown) in the cell region, and a guard ring pattern 224 is formed around the fuses 222. Specifically, the fuses may be a single layer formed of any one selected from titanium (Ti), tantalum (Ta), titanium nitride (TiN), tartalum nitride (TaN), aluminum (Al), tungsten (W), or copper (Cu). It may be a multilayer film formed by a combination of these.

The fuses 222 may be formed of a curved fuse 222 divided into a cutting area A having a wide pitch between the fuses 222a and an uncut area B having a tight pitch between the fuses 222b. Can be. Also, as illustrated in FIG. 1, the fuses 122 may be formed of a straight line fuse 122 having a constant pitch between the fuses 122.

Next, as shown in FIG. 6, the second interlayer insulating layer 230 is formed on the first interlayer insulating layer 210 on which the fuses 222 and the guard ring pattern 224 are formed, and the guard ring 250 is formed. To complete.

In more detail, the contact 226 is formed on the first interlayer insulating layer 210 on which the fuses 222 and the guard ring pattern 224 are formed, and is connected to the guard ring pattern 224. ). Then, a guard ring pattern 228 connected to the contact 226 is formed on the first oxide film 220, and a second oxide film 225 is formed. By repeating the above process, the guard ring 250 is formed around the area where the fuses 222 are concentrated, and the second interlayer insulating film 230 in which a plurality of oxide films are stacked is completed.

Next, as shown in FIG. 7, the third interlayer insulating film 240 is formed as a passivation film on the second interlayer insulating film 230. In this case, the third interlayer insulating film 240 is formed of nitride to prevent moisture absorption into the semiconductor memory device.

Then, a photosensitive film pattern 260 for forming a fuse window 262 is formed in the third interlayer insulating film 240. In this case, the photoresist pattern 260 is formed differently according to the shape of the fuses 222 disposed below. That is, as shown in FIG. 3, when the lower fuses 222 are curved, the fuse windows 262 are formed to expose the respective fuses 222a in the cutting region A having a wide pitch. 1, when the lower fuses 222 are straight, the fuses 222 are formed to expose a portion of the fuses 222 on the respective fuses 222.

Next, using the photoresist pattern 260 as an etching mask, the upper portion of each of the fuses 222 is etched. The fuse windows 262 thus formed expose portions of the fuses 222a, respectively. Second and third interlayer insulating layers 230 and 240 formed of an oxide film and a nitride film remain on both sides of the fuse 222a exposed by the fuse window 262. Thus, the fuse 222a to be cut and the adjacent fuse 222a are isolated. Therefore, by-products generated during cutting of the fuse 222a may be prevented from being distributed to the adjacent fuse 222a.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the semiconductor memory device of the present invention and a method of manufacturing the same, it is possible to isolate the fuse to be adjacent to the fuse to be cut by forming fuse windows that expose a portion of each fuse.

In addition, since a fuse window may be formed in an insulating film formed of an oxide film and a nitride film, and the fuses may be isolated by the remaining insulating film, another structure for isolating adjacent fuses may not be formed, thereby simplifying the process.

Therefore, since by-products generated during fuse cutting are blocked by an insulating film made of an oxide film and a nitride film, a repair fail can be reduced, thereby improving reliability of the semiconductor memory device.

Claims (14)

A plurality of fuses formed on the first interlayer insulating film; Second and third interlayer insulating layers stacked on the plurality of fuses; And And a plurality of fuse windows formed in the second and third interlayer insulating layers to expose a portion of each fuse and protect adjacent fuses when the fuse is cut. The method of claim 1, And the second interlayer insulating film is an oxide film. The method of claim 2, And the third interlayer insulating film is a nitride film. The method of claim 1, The plurality of fuses are a straight line semiconductor memory device. The method of claim 4, wherein And the plurality of fuse windows are staggered from each other. The method of claim 1, The plurality of fuses are curved and divided into a cutting region and an uncut region. The method of claim 6, The plurality of fuse windows are formed on the cutting region. Forming a plurality of fuses on the first interlayer insulating film, Stacking second and third interlayer insulating layers covering the fuses; And forming a plurality of fuse windows exposing portions of the fuses on the second and third interlayer insulating layers and protecting adjacent fuses when the fuses are cut. The method of claim 8, And the second interlayer insulating film is formed of an oxide film. The method of claim 8, And the third interlayer insulating film is formed of a nitride film. The method of claim 8, The plurality of fuses are a straight line semiconductor memory device manufacturing method. The method of claim 11, The plurality of fuse windows are alternately arranged to each other. The method of claim 8, The plurality of fuses are curved and divided into a cutting region and an uncut region. The method of claim 13, The plurality of fuse windows are formed on the cutting region.

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