KR20110001086A - Nonvolatile memory device and operating method thereof - Google Patents

Nonvolatile memory device and operating method thereof Download PDF

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KR20110001086A
KR20110001086A KR1020090058477A KR20090058477A KR20110001086A KR 20110001086 A KR20110001086 A KR 20110001086A KR 1020090058477 A KR1020090058477 A KR 1020090058477A KR 20090058477 A KR20090058477 A KR 20090058477A KR 20110001086 A KR20110001086 A KR 20110001086A
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South Korea
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voltage
word line
voltage change
global word
global
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KR1020090058477A
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Korean (ko)
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박진수
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

PURPOSE: A nonvolatile memory device and a method for operating the same are provided to detect leakage current by detecting the voltage change of word-lines using a voltage change detecting circuit. CONSTITUTION: A memory cell block(301) includes a memory cell in connection with word-lines. A voltage change detecting part(304) detects the level change of a voltage applied to the word-lines. A latch is in connection with a detection node and saves the voltage change of the word-lines as data value. A switching element(303) connects a voltage change detecting circuit with the word-lines. The switching element transfers the voltage change of the word-lines to the detection node.

Description

Nonvolatile memory device and its operation method

The present invention relates to a nonvolatile memory device and a method of operating the same, and more particularly, to a nonvolatile memory device and a method of operating the same for detecting a leakage current generated from a word line.

1 is a schematic diagram illustrating a path of a word line leakage current due to a void of an isolation layer ISO in the operation of a nonvolatile memory device.

During the erase operation (or during the program operation), a high voltage difference occurs between the word line WL and the P well TPWELL, thereby causing stress. As a result of this stress, the device isolation layer ISO may be destroyed to generate a short path A between the word line WL and the P well TPWELL as shown in FIG. 1. In detail, when the device isolation layer ISO is incompletely formed, voids (not shown) are generated in the device isolation layer ISO. When stress is applied thereto, the device isolation layer ISO is subsequently destroyed, thereby causing a word through the void. A current path is formed between the line WL and the P well TPWELL to generate a leakage current. This is especially a problem in highly integrated circuits.

When the short path A is generated, the voltage on the word line WL increases to 0 V or more due to the high voltage applied to the P well TPWELL during the erase operation, thereby slowing down the erase operation speed. In addition, during the program operation, a voltage applied to the word line WL is lowered, which causes a problem of a slow operation of the program.

FIG. 2 is a circuit diagram for calculating the word line leakage current amount in FIG. 1.

In the erase operation, 0 V is applied from the global word line GWL to the local word line WL, and 20 V is applied to the P well TPWELL. Therefore, the erase operation should be performed due to a high voltage difference between the P well TPWELL and the local word line WL. However, due to the short path, the voltage of the local word line WL rises above 0V, and thus the erase operation is not sufficiently performed. Will not.

Referring to FIG. 2, it is calculated how much leakage current occurs when the word line voltage rises by 1V.

The combined resistance R WL of the word line can be obtained by the following expression (1).

Figure 112009039566518-PAT00001

The voltage V WL at the word line can be obtained by the following expression (2).

Figure 112009039566518-PAT00002

The ISO resistance value (R ISO ) when the voltage of the word line rises by 1 V and the leakage current at that time can be obtained by the following equation (3).

Figure 112009039566518-PAT00003

Figure 112009039566518-PAT00004

That is, when the word line voltage rises by 1V, it can be seen that leakage current of 660 nA is generated. However, it is not easy to confirm that a leakage current actually occurs to change the voltage of the word line.

An object of the present invention is to detect a leakage current generated in a word line by detecting a voltage change of the word line using a voltage change detection means.

In order to achieve the above technical problem, a nonvolatile memory device according to an embodiment of the present invention,

A memory cell block including a memory cell connected to a word line; And

And a voltage change detector configured to detect a change in the level of the voltage applied to the word line.

In this embodiment, the voltage change detector may detect that the level of the voltage is changed after applying the voltage to the word line.

In this embodiment, the voltage change detection unit comprises a voltage change detection circuit; And

And a switching element connecting the voltage change detection circuit to the word line.

In this embodiment, the switching element is connected between the word line and the sense node and transfers the voltage change of the word line to the sense node in a voltage change detection operation,

The voltage change detection circuit may include a latch connected to the sensing node and storing a voltage change of the word line as a data value.

In this embodiment, the switching element may be implemented as a high voltage NMOS transistor to protect the circuit inside the voltage change detection circuit from the high voltage applied to the word line.

In example embodiments, the word line may include a global word line and a local word line.

In this embodiment, the voltage generator circuit for generating a voltage applied to the global word line; And

The electronic device may further include a block switching unit connecting the local word line and the global word line according to a block selection signal.

In this embodiment, the voltage change detector may be connected to the global word line and configured to detect that the voltage level applied to the global word line is changed.

In this embodiment, the voltage change detection unit comprises a voltage change detection circuit; And

And a switching element connecting the voltage change detection circuit to the global word line.

In this embodiment, the voltage change detector may be connected to each global word line.

In example embodiments, the switching device may be connected to each global word line, and the voltage change detection circuit may be connected to the switching device in parallel.

In this embodiment, the switching element is connected between the word line and the sense node and transfers the voltage change of the word line to the sense node in a voltage change detection operation,

The voltage change detection circuit may include a latch connected to the sensing node and storing a voltage change of the word line as a data value.

In this embodiment, the switching element may be implemented as a high voltage NMOS transistor to protect the circuit inside the voltage change detection circuit from the high voltage applied to the global word line.

In this embodiment, it is connected between the operating voltage generating circuit and the global word line,

The apparatus may further include a global word line switch configured to transfer the voltage output from the operating voltage generation circuit to the global word lines.

In an embodiment, the voltage change detector may be configured to detect a change in voltage level caused by leakage current.

Method of operating a nonvolatile memory device according to an embodiment of the present invention,

Applying a voltage to a word line to which a memory cell is connected;

Maintaining the word line applied with the voltage in a floating state for a predetermined time; And

Detecting a change in the level of the voltage after the predetermined time has elapsed.

In this embodiment, the voltage change detection unit may apply the voltage to the word line and detect the level change of the voltage after the predetermined time elapses.

In another embodiment, the voltage is applied from an operating voltage generation circuit to a global word line connected to the word line,

The global word line and the word line may be held in a floating state for a predetermined time.

In an embodiment, in detecting the level change of the voltage,

It is possible to detect the level change of the voltage caused by the leakage current.

In example embodiments, the level change of the voltage may be detected in the global word line.

In an embodiment, applying the voltage may include:

Applying a voltage to the global word line by the operating voltage generating circuit while the global word line is floating; And

Thereafter, the method may include connecting the word line and the global word line.

According to the nonvolatile memory device and the operating method thereof according to the present invention, even a low magnitude leakage current occurring in the word line can be detected by detecting the voltage change of the word line using the voltage change detecting means.

In addition, failure due to voids or the like of the device isolation film ISO can be screened efficiently.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3, a nonvolatile memory device 300 according to an embodiment of the present invention may include a memory cell array 301 including a plurality of memory cell blocks 301a and 301b, an operating voltage generation circuit 302, The block switching unit 303, the voltage change detection unit 304, the global word line switch 305, the block decoder 306, and the page buffer 307 are included.

The memory cell blocks 301a and 301b include memory cells, a drain select transistor, and a source select transistor. The memory cells are connected to the bit line BL through the drain select transistor, and are connected to the common source line CSL through the source select transistor. Gates of the memory cells are connected to local word lines WL0-WL31. The gate of the drain select transistor is connected to the local drain select line DSL, and the gate of the source select transistor is connected to the local source select line SSL.

The page buffer 307 is connected to the bit line BL of the memory cell array 301 to read or program data.

The operating voltage generation circuit 302 outputs voltages necessary for the operation of the memory cells to the global word lines GWL0-GWL31. The operating voltage generator circuit 302 generates a drain bias voltage, a source bias voltage and a word line voltage. In addition, the drain bias voltage is supplied to the global drain select line GDSL through the global word line switch 305, and the source bias voltage is supplied to the global source select line GSSL through the global word line switch 305. The operating voltage generation circuit 302 may supply different levels of word line voltages to the selected global word line and the unselected global word lines.

The global word line switch 305 is connected between the operating voltage generation circuit 302 and the global word lines. The global word line switch 305 may transfer the operating voltages output from the operating voltage generation circuit 302 to the global word lines or cut off the supply of the operating voltage. The global word lines are floating when the supply of the operating voltage is interrupted.

The block decoder 306 outputs block selection signals BSEL0-BSELi for selecting one memory cell block among the plurality of memory cell blocks according to the address signal.

The block switching unit 303 includes a plurality of block switches 303a and 303b that operate according to the block selection signals BSEL0-BSELi, and connect local word lines and global word lines of the selected memory cell block. The block switch 303a is arranged as many as the number of memory cell blocks. The block switch 303a may be implemented with NMOS transistors connected between respective global word lines and local word lines. When the NMOS transistors of the block switch 303a are turned on according to the block select signals BSEL0-BSELi, local word lines of the selected block are connected to the global word lines, respectively.

The voltage change detector 304 is connected to global word lines. The voltage change detector 304 is configured to detect, for each local word line, that the level of the operating voltage is changed after the operating voltage generated and supplied by the operating voltage generating circuit 302 is applied to the global word line. To this end, the voltage change detector 304 includes a voltage change detection circuit connected to the global word lines, respectively.

In FIG. 3, although the voltage change detection unit 304 is connected to the global drain select line GDSL and the global source select line GSSL, the voltage change detector 304 detects a change in the voltage level occurring at the word line. The change detector 304 may be connected to only global word lines except for the global drain select line GDSL and the global source select line GSSL. That is, only the leakage current of the word line can be measured.

The voltage change detector 304 may be configured to apply the precharge voltage directly to the global word line, and then detect that the level of the precharge voltage changes.

In addition, the voltage change detection unit 304, after the operating voltage or precharge voltage is applied to the global word line from the operating voltage generation circuit 302, the level of the operating voltage or precharge voltage due to the leakage current generated in the word line It can be configured to detect this change.

4 is a circuit diagram illustrating an example of a voltage change detector of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the voltage change detection unit 304 includes a voltage change detection circuit 400 and a switching element N44 connecting the voltage change detection circuit 400 to a global word line GWL.

The switching element N44 connects the global word line GWL and the voltage change detection circuit 400 in an operation of detecting a voltage change of the local word line. Since a high voltage of 15 V or more is applied to the global word line GWL, the switching element N44 may be implemented as a high voltage NMOS transistor to protect the internal circuit of the voltage change detection circuit 400. The high voltage NMOS transistor operates in response to the enable signal HV_ISO.

It is apparent to those skilled in the art that the voltage change detection circuit 400 may be one of means capable of detecting a voltage change, and is not limited to the circuit illustrated in the present invention.

The voltage change detection circuit 400 includes a precharge unit 401, a sensing unit 402, a latch unit 403, a data setting unit 404, a sensing node sensing unit 405, and a data transmission unit 406. do.

The voltage change detection circuit 400 and the switching element N44 may be connected to each global word line GWL.

Alternatively, only the switching elements N44 may be connected to each global word line, and each of the connected switching elements N44 may be connected to one voltage change detection circuit 400. Each switching element N44 may be selected by a selection signal. In this case, the number of voltage change detection circuits 400 used can be reduced, thereby reducing the overall layout area.

The precharge unit 401 is composed of a PMOS transistor P41 connected between the power supply terminal and the sensing node SO. The PMOS transistor P41 is turned on in response to the low level precharge signal PRECHb to apply the power supply voltage Vcc to the sensing node SO.

The sensing unit 402 includes an NMOS transistor N43 connected between the switching element N44 and the sensing node SO. In response to the sensing signal PBSENSE, the NMOS transistor N43 is turned on so that the sensing node SO is electrically connected to the global word line GWL through the switching element N44.

The latch unit 403 stores an initial value. The initial value may change with the voltage change of the word line in subsequent operations. To this end, the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the input terminal of the first inverter INV1. . At this time, a node to which the output terminal of the first inverter INV1 and the input terminal of the second inverter INV2 are connected is referred to as a first node Q_N, and the output terminal of the second inverter INV2 and the first inverter INV1. A node to which an input terminal of) is connected is called a second node Q.

The data setting unit 404 applies the ground voltage Vss to the first data setting transistor N42 and the second node Q that apply the ground voltage Vss to the first node Q_N of the latch unit 403. The second data setting transistor N41 is applied.

The first data setting transistor N42 is connected between the sensing node sensing unit 405 and the first node Q_N, and the ground voltage Vss transmitted by the sensing node sensing unit 405 in response to the detection signal MSET. ) Is applied to the first node.

The second data setting transistor N41 is connected between the sensing node sensing unit 405 and the second node Q, and the ground voltage Vss transmitted by the sensing node sensing unit 405 in response to the reset signal MRST. ) Is applied to the second node.

The sensing node sensing unit 405 applies the ground voltage Vss to the data setting unit 404 according to the voltage level of the sensing node SO. To this end, it includes an NMOS transistor N40 connected between the data setting unit 404 and the ground terminal.

The data transmitter 406 selectively outputs data stored in the first node Q_N of the latch unit 403 to the sensing node SO. To this end, the data transfer transistor N45 selectively connects the first node Q_N and the sensing node. The data transmitter 406 may be omitted, and in this case, the sensing node SO and the first node Q_N may be separated.

5 is a schematic diagram illustrating a method of operating a nonvolatile memory device according to an exemplary embodiment of the present invention.

The voltage change detection operation of the voltage change detection circuit 400 will be described with reference to FIGS. 4 and 5 as follows.

1) Initialization stage

The initial value is stored in the latch portion 403. To this end, the PMOS transistor P41 of the precharge unit 401 is turned on to turn on the NMOS transistor N40 of the sensing node sensing unit 405, and the reset signal MRST is applied to the second data setting transistor N41. Is applied to turn on the second data setting transistor N41.

Therefore, the ground voltage Vss is applied to the second node Q to initialize the second node Q to a low level. The first node Q_N is initialized to a high level. The sensing node SO is precharged.

2) Precharge Step

A precharge voltage is applied to the global word line GWL in order to detect a voltage change occurring in the word line.

When the precharge voltage is applied by the voltage change detection circuit 400, the global word line switch 305 is first turned off. The block switch 303a is preferably turned off. As a result, the global word line GWL is in a floating state.

Subsequently, when the switching device N44 is turned on and the sensing signal PBSENSE is applied to the NMOS transistor N43 of the sensing unit 402 at the potential of the first voltage V1, the first switching circuit N44 is applied to the global word line GWL. The voltages V1-Vt minus the threshold voltages of the voltage V1 and the NMOS transistor N43 are applied as the precharge voltage.

In another embodiment, since the first node Q_N is initialized to a high level in the initialization step, the NMOS transistor N45 of the data transfer unit 406 is turned on to turn on the global word line with the voltage of the first node Q_N. A precharge voltage can be applied to the GWL.

Subsequently, the precharge voltage applied to the global word line GWL is applied to the local word line of the memory cell block selected through the NMOS transistor of the block switch 303a by the block select signal BSEL0-BSELi output from the block decoder. WL). As a result, the local word line WL is precharged.

3) Evaluation step

The sensing signal PSENSE is applied at a low level (0V) to the NMOS transistor N43 of the sensing unit 402. As a result, the global word line GWL and the local word line WL remain in a floating state for a predetermined time while being connected to each other.

When there is no leakage current in the local word line WL, the potential of the global word line GWL maintains the potential of (V1-Vt). When the leakage current exists, the potential of the global word line GWL The potential decreases gradually at (V1-Vt).

4) Sensing Step

Before the sensing signal PBSENSE is applied to the NMOS transistor N43 of the sensing unit 402 at a high level, the precharge signal PRECHb is applied to the PMOS transistor P41 of the precharge unit 401 at a high level. The PMOS transistor P41 is turned off.

The switching element N44 is turned on by the enable signal HV_ISO, and the sensing signal PBSENSE is lower than the first voltage V1 in the NMOS transistor N43 of the sensing unit 402. Is applied at the potential of.

When there is no leakage current, the potential of the global word line GWL is maintained at (V1-Vt), so the NMOS transistor N43 is turned off even when the second voltage V2 is applied, and the sensing node SO is applied. The potential will remain at a high level. However, when the leakage current is present, the potential of the global word line GWL is lowered, so the NMOS transistor N43 is turned on, and the potential of the sensing node SO depends on the potential of the global word line GWL. Lowers.

5) latch step

The detection signal MSET is applied to the first data setting transistor N42 to a high level to turn on the first data setting transistor N42. The second data setting transistor N41 is turned off.

If there is no leakage current, the sensing node SO maintains a high level, and the NMOS transistor N40 of the sensing node sensing unit 405 is turned on in response to the high level sensing node SO to turn on the ground voltage. Vss is applied to the first node Q_N. Therefore, the first node Q_N changes from a high level to a low level.

When there is a leakage current, the sensing node SO maintains a low level, and the NMOS transistor N40 of the sensing node sensing unit 405 is turned off in response to the low level sensing node SO. Therefore, even when the detection signal MSET is applied to the NMOS transistor N42, the first node Q_N maintains the initial level high.

That is, the value stored in the latch is changed when there is no leakage current, and the value stored in the latch is maintained when there is a leakage current. By checking this, it is possible to know whether leakage current due to voids of the device isolation layer ISO is present.

6 is a schematic diagram illustrating a method of operating a nonvolatile memory device according to another exemplary embodiment of the present invention.

A voltage change detection operation of the voltage change detection circuit 400 will be described with reference to FIGS. 4 and 6 as follows.

1) Initialization stage

Same as the initialization step described above with reference to FIGS. 4 and 5.

2) Precharge Step

A precharge voltage is applied to the global word line GWL in order to detect a voltage change occurring in the word line.

When the precharge voltage is applied by the operating voltage generating circuit 302, the operating voltage generating circuit 302 outputs a high operating voltage (eg, 5 V) higher than the power supply voltage Vcc. The global word line switch 305 transfers an operating voltage to the global word line GWL. This operating voltage becomes a precharge voltage. The block switch 303a is preferably turned off. As a result, the global word line GWL is in a floating state.

Subsequently, the precharge voltage applied to the global word line GWL is applied to the local word line WL of the memory cell block selected through the NMOS transistor of the block switch 303a by the block select signals BSEL0-BSELi output from the block decoder. Is passed). As a result, the local word line WL is precharged.

If the global word line GWL is precharged at a high voltage without precharging the word line through the voltage change detection circuit 400, the leakage current generated in the word line is precharged to a higher level voltage. ) Can be detected more clearly.

3) Evaluation step

The global word line switch 305 is interrupted while the global word line GWL and the local word line WL are connected to each other so that the global word line GWL and the local word line WL remain in a floating state for a predetermined time. .

When there is no leakage current in the local word line WL, the potential of the global word line GWL maintains the potential of the precharge voltage, and when the leakage current exists, the potential of the global word line GWL becomes It gradually decreases at the potential of the precharge voltage.

4) Sensing Step

Only the potential of the global word line GWL is different, and is the same as the sensing step described with reference to FIGS. 4 and 5.

5) latch step

The difference is only in the potential of the global word line GWL, and is the same as the latch step described with reference to FIGS. 4 and 5.

In this embodiment, in order to protect the circuit inside the voltage change detection circuit 400 from the high voltage because the high voltage is applied to the global word line GWL to precharge the local word line WL, the global word line GWL A high voltage NMOS transistor may be used as the switching element N44 connecting the overvoltage change detection circuit 400.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

FIG. 1 is a schematic diagram illustrating a path of a word line leakage current due to a void of an isolation layer ISO during an erase operation.

FIG. 2 is a circuit diagram for calculating the word line leakage current amount in FIG. 1.

3 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

4 is a circuit diagram illustrating an example of a voltage change detector of a nonvolatile memory device according to an exemplary embodiment of the present invention.

5 is a schematic diagram illustrating a method of operating a nonvolatile memory device according to an exemplary embodiment of the present invention.

6 is a schematic diagram illustrating a method of operating a nonvolatile memory device according to another exemplary embodiment of the present invention.

 <Explanation of symbols for the main parts of the drawings>

300 ... Non-volatile memory device 301 ... Memory cell array

302 ... operating voltage generating circuit

304 ... voltage change detector 305 ... global word line switch

306 ... block decoder 307 ... page buffer

400.Voltage change detection circuit 401 Precharge unit

402.Sensing part 403.Latch part

404 ... data setting unit 405 ... sensing node sensing unit

406 Data transmission unit

Claims (21)

A memory cell block including a memory cell connected to a word line; And And a voltage change detector configured to detect a change in the level of the voltage applied to the word line. The method of claim 1, And detecting that the level of the voltage changes after the voltage change detector applies the voltage to the word line. The method according to claim 1 or 2, The voltage change detection unit includes a voltage change detection circuit; And And a switching element connecting the voltage change detection circuit to the word line. The method of claim 3, wherein The switching element is connected between the word line and the sensing node and transfers the voltage change of the word line to the sensing node in a voltage change detection operation, And the voltage change detection circuit comprises a latch connected to the sense node and storing a voltage change of the word line as a data value. The method of claim 3, wherein And the switching device is implemented with a high voltage NMOS transistor to protect a circuit inside the voltage change detection circuit from a high voltage applied to the word line. The method of claim 1, The word line includes a global word line and a local word line. The method of claim 6, An operating voltage generation circuit for generating a voltage applied to the global word line; And And a block switching unit configured to connect the local word line and the global word line according to a block select signal. The method of claim 7, wherein And the voltage change detector is connected to the global word line and configured to detect a change in a voltage level applied to the global word line. The method of claim 8, The voltage change detection unit includes a voltage change detection circuit; And And a switching element connecting the voltage change detection circuit to the global word line. The method of claim 9, And the voltage change detector is connected to each of the global word lines. The method of claim 9, And the switching element is connected to each of the global word lines, and the voltage change detection circuit is connected in parallel with the switching element. The method of claim 9, The switching element is connected between the word line and the sensing node and transfers the voltage change of the word line to the sensing node in a voltage change detection operation, And the voltage change detection circuit comprises a latch connected to the sense node and storing a voltage change of the word line as a data value. The method of claim 9, And the switching device is implemented with a high voltage NMOS transistor to protect a circuit inside the voltage change detection circuit from a high voltage applied to the global word line. The method of claim 8, Is connected between the operating voltage generating circuit and the global word line, And a global word line switch for transferring a voltage output from the operating voltage generation circuit to the global word lines. The method according to claim 2 or 8, And the voltage change detector is configured to detect a change in voltage level caused by a leakage current. Applying a voltage to a word line to which a memory cell is connected; Maintaining the word line applied with the voltage in a floating state for a predetermined time; And Detecting a change in the level of the voltage after the predetermined time has elapsed. The method of claim 16, And applying a voltage from the voltage change detector to the word line and detecting a level change of the voltage after the predetermined time elapses. The method of claim 16, Applying the voltage to a global word line connected to the word line in an operating voltage generation circuit; And maintaining the floating state for a predetermined time while the global word line and the word line are connected. The method according to any one of claims 16 to 18, In detecting the level change of the voltage, A method of operating a nonvolatile memory device detecting a level change of the voltage caused by a leakage current. The method of claim 18, And detecting a change in level of the voltage in the global word line. The method of claim 18, Applying the voltage, Applying a voltage to the global word line by the operating voltage generating circuit while the global word line is floating; And Thereafter connecting the word line with the global word line.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9842659B2 (en) 2014-04-07 2017-12-12 Samsung Electronics Co., Ltd. Non-volatile memory device for detecting progressive error, memory system, and method of operating the non-volatile memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9842659B2 (en) 2014-04-07 2017-12-12 Samsung Electronics Co., Ltd. Non-volatile memory device for detecting progressive error, memory system, and method of operating the non-volatile memory device

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