KR20100136071A - Method for manufacturing metal oxide semiconductor transistor and metal oxide semiconductor transistor structure - Google Patents

Method for manufacturing metal oxide semiconductor transistor and metal oxide semiconductor transistor structure Download PDF

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Publication number
KR20100136071A
KR20100136071A KR1020090054250A KR20090054250A KR20100136071A KR 20100136071 A KR20100136071 A KR 20100136071A KR 1020090054250 A KR1020090054250 A KR 1020090054250A KR 20090054250 A KR20090054250 A KR 20090054250A KR 20100136071 A KR20100136071 A KR 20100136071A
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South Korea
Prior art keywords
semiconductor substrate
gate electrode
gate
etching process
over etching
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KR1020090054250A
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Korean (ko)
Inventor
윤형선
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주식회사 동부하이텍
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Priority to KR1020090054250A priority Critical patent/KR20100136071A/en
Publication of KR20100136071A publication Critical patent/KR20100136071A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET

Abstract

PURPOSE: In the MOS transistor and manufacturing method thereof is the MOS transistor, while distance between source/drain and the gate being isolated and enhancing the conductivity, the parasitic capacitance effect is reduced. CONSTITUTION: The gate electrode area(116a) is defined after the photoresist pattern forms the gate conductive film on the top of the semiconductor substrate. The gate electrode is formed in the semiconductor substrate. The first overeching process is enforced for the front side of the semiconductor substrate in which the gate electrode is formed.

Description

MOS transistor and its manufacturing method {METHOD FOR MANUFACTURING METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METAL OXIDE SEMICONDUCTOR TRANSISTOR STRUCTURE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a metal oxide semiconductor (MOS) transistor, and more particularly, to a MOS transistor suitable for reducing parasitic capacitance while improving electrical conductivity between a gate and a source / drain of the MOS transistor, and a manufacture thereof. It is about a method.

In general, metal silicide is actively applied to a VLSI (Very Large Scale Integration) wiring process because of low resistance, high thermal stability, and easy application with a current silicon process. Further, the silicide film formed on the gate electrode or the source / drain junction surface can lower the resistivity of the gate electrode and the contact resistance of the source / drain, respectively, and thus, the wiring resistance can be greatly reduced. As a silicide material, rare earth metals that react with silicon, such as tungsten silicide (WSi 2 ), titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ), nickel silicide (NiSi), and the like are used.

Meanwhile, the formation of a silicide film on the gate electrode and the source / drain junction surface simultaneously by a spacer insulating film on the sidewall of the gate electrode is called a salicide process, and is a general MOS transistor (MOS). (Metal Oxide Semiconductor) transistors can use these salicide processes to lower the conductivity of gates and sources / drains.

1A to 1G are cross-sectional views illustrating a salicide film manufacturing process of a semiconductor device according to the prior art, and a brief description of the salicide film manufacturing process will be given with reference to FIGS. 1A to 1G.

First, in FIG. 1A, a device isolation region 12 is formed by performing a device isolation and a well process on a silicon substrate 10 as a semiconductor substrate, and then a gate oxide film (shown on the entire surface of the silicon substrate 10). Omitted), and for example, doped polysilicon is deposited as the gate conductive film 14 on the gate oxide film.

As shown in FIG. 1B, after the photoresist (not shown) is applied on the gate conductive layer 14, the photoresist pattern 16 defining the gate electrode region is formed by performing a photo and etching process. do.

Next, as shown in FIG. 1C, the gate conductive layer 14 is etched by the dry etching process according to the photoresist pattern 16 to form the gate electrode 14 ′, and then the photoresist pattern 16 is removed. For example, a silicon nitride film is deposited as the insulating film 18 over the entire substrate.

Subsequently, as shown in FIG. 1D, etch back is performed on the insulating layer 18 to form sidewall spacers 18 ′ on the sidewalls of the gate electrode 14 ′.

As shown in FIG. 1E, the source / drain junction region 20 is formed in the silicon substrate 10 by ion implantation of high concentration of n-type or p-type impurities on the entire surface of the resultant.

Then, as illustrated in FIG. 1F, a silicide metal 22, for example, titanium (Ti), is deposited on the entire surface of the resultant, and an annealing process is performed.

Then, as illustrated in FIG. 1G, the titanium electrode silicide reacts with the gate electrode 14 ′ except for the sidewall spacer 18 ′ to form a titanium silicide layer 24 a at the gate, and the source / drain junction 20 is formed. Titanium silicide film 24b in the source / drain regions is formed by the silicon surface of the silicon and titanium react with the silicide reaction. In FIG. 1G, reference numeral 14 '' denotes a gate electrode after the titanium silicide film 24a is formed at the gate.

Finally, the conventional salicide process is completed by performing a cleaning process to remove unsilicided titanium.

In this case, a parasitic capacitance, which is a capacitor-like form, may be formed between the metallized gate and the source / drain by the salicide process as described above, and the parasitic capacitance may be combined with a resistance component to form a unit transistor. Can reduce the stability of the amplifier, especially with the miller effect in analog circuitry.

Therefore, there is a limit that the designer has to satisfy the insufficient performance by adding additional circuits for better performance or considering the layout area.

Accordingly, an embodiment of the present invention proposes a MOS transistor and a method of manufacturing the MOS transistor which can reduce the parasitic capacitance effect while increasing the electrical conductivity by separating the distance between the gate and the source / drain in the MOS transistor.

According to an embodiment of the present invention, a process of forming a photoresist pattern defining a gate electrode region after forming a gate conductive layer on the semiconductor substrate, and forming the gate resist along the formed photoresist pattern Removing a portion of the film to form a gate electrode, and performing an over etching process on the semiconductor substrate on which the gate electrode and the photoresist pattern are formed to form a separation distance between the gate electrode and a source / drain of the semiconductor substrate. It provides a MOS transistor manufacturing method comprising the process.

According to another exemplary embodiment of the present invention, a first separation distance between a gate region on a semiconductor substrate, a source / drain region on the semiconductor substrate, and the gate region and the source / drain region by over etching is performed. And a second sidewall spacer formed outside the first sidewall spacer such that a second separation distance between the gate region and the source / drain region is formed by the over etching. It provides a MOS transistor.

According to the present invention, the parasitic capacitance effect can be reduced while increasing the electrical conductivity by separating the distance between the gate and the source / drain in the MOS transistor.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A to 2K are cross-sectional views illustrating a method of manufacturing a MOS transistor according to an embodiment of the present invention, specifically, a salicide layer manufacturing process of a semiconductor device. Referring to FIGS. 2A to 2K, FIGS. The salicide film production process will be described in detail.

First, in FIG. 2A, a device isolation region 102 is formed by performing a device isolation and a well process on a silicon substrate 100 as a semiconductor substrate, and then a gate oxide film (shown on the entire surface of the silicon substrate 100). Omitted), and for example, doped polysilicon is deposited as the gate conductive film 104 on the gate oxide film.

As shown in FIG. 2B, after the photoresist (not shown) is coated on the gate conductive layer 104, the photoresist pattern 106 defining the gate electrode region is formed by performing a photo and etching process. do.

Next, as shown in FIG. 2C, a dry etching process is performed along the photoresist pattern 106 to remove a portion of the gate conductive layer 104. In FIG. 2C, reference numeral 104 ′ denotes a gate conductive layer to which the dry etching process is applied. The gate conductive layer 104 ′ to which the dry etching process is applied may be referred to as a gate electrode.

Subsequently, in FIG. 2D, a first over etching process according to the present exemplary embodiment is performed on the entire surface of the silicon substrate 100 on which the above-described gate electrode 104 ′ is formed. This first over etching is one of the features of the present embodiment, and the photoresist pattern 106 left after the gate electrode 104 'is formed, rather than the entire surface etching after removing the photoresist pattern 106 as in the prior art. 1st over etching is performed, leaving it as it is. In FIG. 2D, reference numerals 100 ′ and 102 ′ denote silicon substrates and device isolation regions after the first over etch process, respectively, and silicon substrate 100 ′ and device isolation regions 102 ′ after the first over etch process. It can be seen that the height is lower than the original silicon substrate 100 and the isolation region 102.

Meanwhile, in FIG. 2E, the photoresist pattern 106 of FIG. 2D is removed, and then a primary insulating film 108, for example, a silicon nitride film is deposited on the entire surface of the silicon substrate 100 ′.

Subsequently, as shown in FIG. 2F, a second over-etching process is performed on the entire surface of the silicon substrate 100 ′ on which the primary insulating film 108 is deposited to remove a portion of the primary insulating film 108. Thus, the primary sidewall spacers 108 'are formed on the sidewalls of the gate electrode 104'.

At this time, during the second over-etching to remove a part of the primary insulating layer 108, a part of the silicon substrate 100 ′ and the device isolation region 102 ′ are also removed together. 102 " represents the silicon substrate and the device isolation region after the secondary over-etch process, respectively, and the height of the silicon substrate 100 " and the device isolation region 102 " It can be seen that it is lower than the silicon substrate 100 'and the isolation region 102' after the first over etching process.

2G, a second insulating layer 110, for example, a silicon nitride layer, is deposited on the entire surface of the resultant product of FIG. 2F.

Subsequently, as shown in FIG. 2H, a third over-etching process is performed on the entire surface of the silicon substrate 100 ″ on which the secondary insulating film 110 is deposited, thereby removing a part of the secondary insulating film 110. By removing, the secondary sidewall spacers 110 'are formed on the sidewalls of the gate electrode 104' where the primary sidewall spacers 108 'are formed.

At this time, during the third over-etching to remove a part of the secondary insulating layer 110, a part of the silicon substrate 100 ″ and the device isolation region 102 ″ are also removed together. In FIG. 2H, reference numeral 100 ′ is used. '' And 102 '' 'represent the silicon substrate and the isolation region after the third over-etch process, respectively, and the silicon substrate 100' '' and the isolation region 102 'after the third over-etch process. It can be seen that the height is lower than the silicon substrate 100 " and the isolation region 102 " after the secondary over etching process.

When the tertiary over-etching process is completed, in FIG. 2I, a high concentration of n-type or p-type impurities are implanted into the entire surface of the resultant to form source / drain regions 112 in the silicon substrate 100 ′ ″.

Next, as shown in FIG. 2J, a silicide metal 114, for example, titanium (Ti), is deposited on the entire surface of the resultant, and an annealing process is performed.

Then, as shown in FIG. 2K, except for the primary sidewall spacers 108 ′ and the secondary sidewall spacers 110 ′, the titanium electrode silicide reacts with the gate electrode 104 ′ and the titanium silicide layer 116a in the gate region. ), And the silicon surface of the source / drain junction undergoes a silicide reaction to form a titanium silicide film 116b in the source / drain region 112. In FIG. 2K, reference numeral 104 '' denotes a gate electrode after the titanium silicide layer 116a is formed in the gate region, and reference numeral 112 'denotes a source after the titanium silicide layer 116b is formed in the source / drain region. Each of the / drain regions is shown.

Finally, the salicide process according to the present embodiment is completed by performing a washing process to remove unsilicided titanium.

As shown in FIG. 2K, the MOS transistor implemented by the MOS transistor manufacturing process according to the present embodiment as described above includes a silicon substrate including the source / drain regions 112 ′ by at least two or more over etching processes. In addition to lowering the height of 100 " 'as well as having a double sidewall spacer 108 ' and 110 ", the gap between the gate 104 " and the source / drain regions 112 ' Increasing the distance is expected to improve the electrical conductivity between gate and source / drain and reduce parasitic capacitance.

3A to 3G are cross-sectional views illustrating a method of manufacturing a MOS transistor according to another exemplary embodiment of the present invention, specifically, a process of manufacturing a salicide layer of a semiconductor device, which is described with reference to FIGS. 3A to 3G. The salicide film production process according to the example will be described in detail.

First, in FIG. 3A, the device isolation region 202 is formed by performing a device isolation and a well process on the silicon substrate 200 as a semiconductor substrate, and then a gate oxide film (not shown) on the entire surface of the silicon substrate 200. Is formed and, for example, doped polysilicon is deposited as the gate conductive film 204 on the gate oxide film.

As shown in FIG. 3B, after the photoresist (not shown) is applied on the gate conductive layer 204, the photoresist pattern 206 defining the gate electrode region is formed by performing a photo and etching process. do.

Next, in FIG. 3C, a dry etching process is performed along the photoresist pattern 206 to remove a portion of the gate conductive layer 204. In FIG. 3C, reference numeral 204 ′ denotes a gate conductive layer to which the dry etching process is applied. The gate conductive layer 204 ′ to which the dry etching process is applied may be referred to as a gate electrode.

In FIG. 3C, after forming such a gate electrode 204 ′, the photoresist pattern 206 is removed, and a silicon nitride film is deposited as the insulating film 208 on the entire surface of the substrate.

Subsequently, in FIG. 3D, a front surface etching process is performed on the entire surface of the silicon substrate 200 on which the gate electrode 204 ′ is formed to remove a portion of the insulating layer 208, thereby forming sidewalls on the sidewalls of the gate electrode 204 ′. Spacer 208 'is formed.

At this time, the front etching process applied to the present embodiment is characterized in that the over etching process is applied. That is, in FIG. 3D, the sidewall spacer 208 ′ is formed by the over etching process, and a part of the silicon substrate 200 and the device isolation region 202 are also removed. Reference numerals 200 ′ and 202 ′ are used to describe the present embodiment. Shows the silicon substrate and the device isolation region after the over-etching process, respectively, and the heights of the silicon substrate 200 'and the device isolation region 202' after the over-etching process are the original silicon substrate 200 and the device isolation region. It can be seen that the lower than (202).

When the over-etching process is completed, in FIG. 3E, the source / drain regions 210 are formed in the silicon substrate 200 ′ by ion implanting a high concentration of n-type or p-type impurities on the entire surface of the resultant of FIG. 3D.

Next, as shown in FIG. 3F, a silicide metal 212, for example, titanium (Ti), is deposited on the entire surface of the resultant of FIG. 3E, and an annealing process is performed.

Then, as illustrated in FIG. 3G, the titanium electrode silicide reacts with the gate electrode 204 ′ except for the sidewall spacers 208 ′ to form a titanium silicide film 214a in the gate region, and the silicon of the source / drain junction is formed. The surface and titanium react with silicide to form titanium silicide films 214b in the source / drain regions 210, respectively. In FIG. 3G, reference numeral 204 '' denotes a gate electrode after the titanium silicide layer 214a is formed in the gate region, and reference numeral 210 'denotes a source after the titanium silicide layer 116b is formed in the source / drain region. Each of the / drain regions is shown.

Finally, the salicide process according to the present embodiment is completed by performing a washing process to remove unsilicided titanium.

3A to 3G described above, the separation distance between the gate and the source / drain may be somewhat reduced compared to the embodiment of FIGS. 2A to 2K, but the gate and the source / drain may be separated by a relatively simple process. It is implemented to improve the electrical conductivity between gate and source / drain and reduce parasitic capacitance by separating the distance by a certain distance.

The foregoing embodiments are intended to illustrate, not limit, the invention, and those skilled in the art should note that many other embodiments can be designed without departing from the scope of the invention as defined by the appended claims. do. In the claims, any reference signs placed between parentheses shall not be construed to limit the invention. The expression “comprising”, “comprising” and the like does not exclude the presence of elements or steps other than those listed in all the claims or the specification as a whole. The singular references of components do not exclude a plurality of references of such components, and vice versa.

1A to 1G are cross-sectional views illustrating salicide manufacturing processes in a conventional MOS transistor manufacturing method;

2A to 2K are cross-sectional views illustrating a salicide manufacturing process in a MOS transistor manufacturing method according to an embodiment of the present invention;

3A to 3G are cross-sectional views illustrating a salicide manufacturing process in a MOS transistor manufacturing method according to another embodiment of the present invention.

Claims (9)

Forming a photoresist pattern defining a gate electrode region after forming a gate conductive layer on the semiconductor substrate; Removing a portion of the gate conductive layer along the formed photoresist pattern to form a gate electrode; Forming a separation distance between the gate electrode and the source / drain of the semiconductor substrate by performing an over etching process on the semiconductor substrate on which the gate electrode and the photoresist pattern are formed MOS transistor manufacturing method comprising a. The method of claim 1, The separation distance forming process, Performing a first over etching process on the entire surface of the semiconductor substrate on which the gate electrode is formed; Removing the photoresist pattern and depositing a primary insulating film on the entire surface of the semiconductor substrate; Forming a primary sidewall spacer on the sidewall of the gate electrode by performing a second overetch process on the entire surface of the semiconductor substrate on which the primary insulating film is deposited, to remove a portion of the primary insulating film; Depositing a secondary insulating film on an entire surface of the semiconductor substrate on which the primary sidewall spacers are formed; A secondary sidewall spacer is formed on the sidewall of the gate electrode on which the primary sidewall spacer is formed by performing a tertiary over etching process on the entire surface of the semiconductor substrate on which the secondary insulating film is deposited. Process MOS transistor manufacturing method comprising a. The method of claim 2, The first over etching process, The MOS transistor manufacturing method performed by leaving the said photoresist pattern. The method of claim 2, The first over etching process, And a height of the semiconductor substrate is reduced within a first set range. The method of claim 2, The second over etching process, And forming a portion of the semiconductor substrate while forming the primary sidewall spacers. The method of claim 2, The second over etching process, And a height of the semiconductor substrate is reduced within a second set range than a height of the semiconductor substrate after the first overetching process. The method of claim 2, The third over etching process, And removing a portion of the semiconductor substrate together while forming the secondary sidewall spacers. The method of claim 2, The third over etching process, And a height of the semiconductor substrate is reduced in a third set range from a height of the semiconductor substrate after the second overetching process. A gate region on the semiconductor substrate, Source / drain regions on the semiconductor substrate; A first sidewall spacer for forming a primary separation distance between the gate region and the source / drain region by over etching; A second sidewall spacer formed outside of the first sidewall spacer such that a second separation distance between the gate region and the source / drain region is formed by the overetching Morse transistor comprising a.
KR1020090054250A 2009-06-18 2009-06-18 Method for manufacturing metal oxide semiconductor transistor and metal oxide semiconductor transistor structure KR20100136071A (en)

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