KR20100132197A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a method for manufacturing the same are provided to reduce gate-induced-drain-leakage(GIDL) by alleviating electric field among a gate electrode, a source, and a drain. CONSTITUTION: An active region(10A) is defined on a substrate(10) by an element isolating film(13). A trench is formed in the active region. A source(S) and a drain(D) are formed on both sides of the trench. A first gate conductive film(18) is formed on the lower side of the trench along the surface of the trench. A second gate conductive film(19) is formed on the first gate conductive film.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same for reducing gate induced drain leakage (GIDL).

In DRAM devices, in which a unit cell is composed of one MOS transistor and one capacitor, it is highly integrated to reduce the area while increasing the capacitance of a capacitor that occupies a large area on a chip. Has become an important factor.

In order to form a capacitor having a high capacitance in a small area, attempts have been made to increase the height of the capacitor or to reduce the thickness of the dielectric film.

However, when the height of the capacitor is increased, there is a problem that the step difference between the cell region and the peripheral region is increased, and when the thickness of the dielectric film is decreased, the leakage current increases as the thickness of the dielectric film is decreased.

In order to overcome these problems, recently, a method of using embedded gates to reduce the bit line parasitic capacitance to half level has been introduced to drastically lower the capacitance of the capacitor required to maintain the same sense amplifier driving capability. .

As the gate electrode of the buried gate, a metal having a low specific resistance is usually adopted.

However, when a metal is used instead of an N + type polysilicon film as the gate electrode of the N-channel transistor, a high electric field is applied to the gate insulating film between the gate electrode, the source, and the drain because the work function value of the metal is larger than that of the N + type polysilicon film. Application of GIDL (Gate Induced Drain Leakage) increases, thereby reducing the refresh characteristics of the DRAM device.

The present invention provides a semiconductor device and a method of manufacturing the same for reducing GIDL and improving retrace characteristics.

A semiconductor device according to an embodiment of the present invention includes a substrate in which an active region is defined by an isolation layer, trenches formed in the active region including the isolation layer, sources and drains formed in both sides of the trench, and the trenches. A first gate conductive layer formed along the trench surface at a lower portion thereof, a second gate conductive layer formed on the first gate conductive layer and separated from the trench side surface at a predetermined interval, and the second gate conductive layer and the And an insulating film filling the space between the trench sides.

The upper surface of the first gate conductive layer is positioned 10 to 600 kV below the upper surface of the second gate conductive layer.

The top surface of the second gate conductive layer is positioned below the top surfaces of the source and drain.

The insulating layer fills a space between the second gate conductive layer and the trench side surface and gap fills the trench on the second gate conductive layer.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a trench in a substrate, forming a second gate conductive film through the first gate conductive film, and forming the trench; Selectively etching the first gate conductive layer by using an etching rate difference between the second gate conductive layers to form a space between the second gate conductive layer and the trench side surface, and forming an insulating layer in the space It is characterized by including.

The thickness of the first conductive layer etched in the etching of the first gate conductive layer is 10 to 600 kPa.

The forming of the space may be performed by a wet etching process or a dry etching process having a higher etching rate with respect to the first gate conductive layer compared to the second gate conductive layer.

The forming of the first and second gate conductive layers may include forming a first gate conductive layer along a surface curvature on the entire surface including the trench, and forming a second gate on the first gate conductive layer to fill the trench. And forming a conductive film, and removing the second and first gate conductive films formed outside the trench.

And removing the first and second gate conductive layers formed on the trench after the forming of the first and second gate conductive layers to expose the upper portions of the trenches.

And performing a post-cleaning process after removing the first and second gate conductive layers formed on the trench.

Forming the space is characterized in that the same as the step of performing the post-cleaning process.

The post-cleaning process may be performed using a cleaning liquid including an etchant having a higher etching rate with respect to the first gate conductive layer than the second gate conductive layer.

According to the present invention, since the thickness of the insulating film between the gate electrode, the source and the drain is increased, the electric field between the gate electrode, the source, and the drain is alleviated, thereby reducing the GIDL, thereby improving the relash characteristics of the device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

1 and 2, a semiconductor device according to the present invention may include a substrate 10, a trench 16 formed in the substrate 10, a first gate conductive layer 18 formed under the trench 16, and A gate electrode G formed on the first gate conductive layer 18 and including a second gate conductive layer 19 separated from the side surface of the trench 16 at a predetermined interval, and the second gate conductive layer 19. And an insulating film 21 filling the space between the substrate 10 and the substrate 10.

More specifically, an isolation layer 13 is formed on the substrate 10 to define the active region 10A.

In order to increase the degree of integration, the active region 10A may be designed to be inclined in a diagonal direction with a predetermined angle θ1 rather than in a vertical or horizontal direction.

The trench 16 is formed in one direction in the active region 10A including the device isolation layer 13.

The source S and the drain D are formed in the active region 10A on both sides of the trench 16.

The gate insulating film 17 is formed along the surface curvature on the active region 10A in the trench 16.

Meanwhile, a first gate conductive film 18 is formed under the trench 16.

The first gate conductive layer 18 may have a conformal structure formed along surface curvature.

A titanium nitride film TiN may be used as the first gate conductive film 18.

The second gate conductive film 19 is formed on the first gate conductive film 18 at regular intervals from the side surface of the trench 16. The second gate conductive film 19 functions as the substantially gate electrode G together with the first gate conductive film 18.

Tungsten (W) may be used as the second gate conductive layer 19.

An interval between the sides of the second gate conductive layer 19 and the trench 16 may be equal to the thickness of the first gate conductive layer 18.

The height from the top surface of the second gate conductive film 19 to the top surface of the first gate conductive film 18 may range from 10 to 600 kV.

Meanwhile, the top surface of the second gate conductive layer 19 may be positioned below the top surface of the source and drain (S and D).

As such, when the upper surface of the second gate conductive layer 19 is positioned below the upper surfaces of the sources and drains S and D, the overlap area between the gate electrode G and the sources and drains S and D is reduced, thereby reducing GIDL. Is reduced.

The insulating film 21 fills a space between the second gate conductive film 19 and the side surface of the trench 16, and gap fills the trench 16 on the second gate conductive film 19.

The insulating film 21 may be composed of an oxide film, for example, an LP-TEOS film.

A method of manufacturing a semiconductor device having the above structure is as follows.

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 3A, pad insulating layers 11 and 12 are formed on a substrate 10, and an isolation layer 13 is formed by a shallow trench isolation (STI) process to define an active region 10A.

The pad insulating films 11 and 12 can be formed by stacking the pad oxide film 11 and the pad nitride film 12.

In the device isolation layer 13, a portion of the pad nitride layer 12, the pad oxide layer 11, and the substrate 10 are etched to form trenches for device isolation, and an insulating layer is formed on the entire surface so that the device isolation trenches are gap-filled. The insulating film can be etched in its entirety so that the (12) is exposed to form it.

A SOD (Spin On Dielectric) film may be used as the insulating film. When the SOD film is used as the insulating film, a heat treatment process for curing the SOD film may be performed before the entire surface of the insulating film is etched.

As the front etching process, a chemical mechanical polishing (CMP) process or an etchback process may be used.

Next, source and drain impurities are implanted into the substrate 10 of the active region 10A to form the impurity implantation layer 14.

Referring to FIG. 3B, a mask pattern 15 for opening a gate predetermined region is formed on the resultant, and the device isolation layer 13, the pad nitride layer 12, and the pad oxide layer 11 are formed using the mask pattern 15 as an etch barrier. And a portion of the substrate 10 are etched to form the trench 16.

At this time, as the impurity implantation layer 14 of the gate predetermined region is etched, the impurity implantation layer 14 is separated with the trench 16 interposed therebetween, so that the source S and the drain D are formed.

Referring to FIG. 3C, the mask pattern 15 is removed and the gate insulating layer 17 is formed on the active region 10A in the trench 16.

The gate insulating layer 17 may be an oxide layer formed by an oxidation process. Alternatively, the gate insulating film 17 may be a composite film of an oxide film and a nitride film.

Then, the first gate conductive film 18 is formed on the entire surface including the trench 16 along the surface curvature, and the second gate conductive film 19 is formed on the first gate conductive film 18 to fill the trench 16. ).

The first gate conductive layer 18 and the second gate conductive layer 19 may be heterogeneous metals. For example, the first gate conductive layer 18 may be a titanium nitride layer, and the second gate conductive layer 19 may be a tungsten layer.

Referring to FIG. 3D, the first and second gate conductive layers 18 and 19 are removed from the trench 16 by removing the second and first gate conductive layers 19 and 18 formed outside the trench 16 by the entire surface etching process. Isolate inside.

As the front surface etching process, a CMP process or an etch back process may be used.

Referring to FIG. 3E, the first and second gate conductive layers 18 and 19 formed on the trench 16 are removed by the entire surface etching process to expose the upper portion of the trench 16. An etch back process may be used as a front etch process.

Subsequently, a post cleaning process can be performed.

Referring to FIG. 3F, the second gate conductive layer is selectively etched by selectively etching the first gate conductive layer 18 by an etching process using an etching rate difference between the first gate conductive layer 18 and the second gate conductive layer 19. A space 20 is formed between 19 and the side of trench 16.

In this case, the thickness of the first gate conductive layer 18 to be etched may have a range of 10 to 600 kPa.

The etching process may be performed by a wet etching process or a dry etching process having a higher etching rate with respect to the first gate conductive layer 18 than the second gate conductive layer 19.

The etching process may be performed during the post-cleaning process, which is performed after the first and second gate conductive layers 18 and 19 on the trench 16 are removed without separately etching the first gate conductive layer 18. .

In this case, the post-cleaning process is performed using a cleaning liquid containing an etchant having a high etching rate with respect to the first gate conductive film 18 relative to the two gate conductive film 19.

Thereby, the gate electrode G which consists of the 1st, 2nd gate conductive films 18 and 19 is formed.

Referring to FIG. 3G, an insulating film 21 gap-filling the space 20 and the trench 16 is formed.

The insulating layer 21 may be formed by depositing an insulating layer on the entire surface including the space 20 and the trench 16, and removing the insulating layer formed outside the space 20 and the trench 16 by a front surface etching process.

The insulating film 21 may be formed of an oxide film-based material. The insulating film 21 is preferably formed of an LP-TEOS oxide film so that oxidation of the first and second gate conductive films 18 and 19 can be suppressed as much as possible.

As described in detail above, the thickness of the insulating film between the gate electrode G and the source and drain S and D is increased to reduce the electric field between the gate and the source and drain S and D, thereby suppressing GIDL. This has the effect of improving the reflash characteristics of the DRAM device.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of main parts of drawing>

10: substrate

16: trench

18, 19: 1st, 2nd gate conductive film

22: insulating film

Claims (12)

A substrate in which an active region is defined by an isolation layer; A trench formed in the active region including the device isolation layer; Source and drain formed in the active region on both sides of the trench; A first gate conductive layer formed below the trench along the surface of the trench; A second gate conductive layer formed on the first gate conductive layer and separated from the trench side surface at a predetermined interval; And An insulating layer filling a space between the second gate conductive layer and the trench side surface; A semiconductor device comprising a. The method of claim 1, And a top surface of the first gate conductive film is located 10 to 600 microseconds below the top surface of the second gate conductive film. The method of claim 1, And a top surface of the second gate conductive layer is positioned below a top surface of the source and drain. The method according to claim 1 or 3, And the insulating layer fills a space between the second gate conductive layer and the trench side surface and gap fills the trench on the second gate conductive layer. Forming a trench in the substrate; Forming a second gate conductive film through the trench through a first gate conductive film; Selectively etching the first gate conductive layer by using an etching rate difference between the first gate conductive layer and the second gate conductive layer to form a space between the second gate conductive layer and the trench side surface; And Forming an insulating film in the space; Method of manufacturing a semiconductor device comprising a. The method of claim 5, And a thickness of the first conductive film etched in the step of etching the first gate conductive film is 10 to 600 kV. The method of claim 5, The forming of the space may be performed by a wet etching process or a dry etching process having a higher etching rate with respect to the first gate conductive layer compared to the second gate conductive layer. The method of claim 5, Forming the first and second gate conductive layers may include Forming a first gate conductive film along a surface curvature on the entire surface including the trench; Forming a second gate conductive layer on the first gate conductive layer to fill the trench; And Removing the second and first gate conductive layers formed outside the trenches; Method of manufacturing a semiconductor device comprising a. The method of claim 5, And removing the first and second gate conductive layers formed on the trenches to expose the upper portions of the trenches after the forming of the first and second gate conductive layers. The method of claim 9, And performing a post-cleaning process after removing the first and second gate conductive layers formed on the trench. The method of claim 5 or 10, Forming the space is a method of manufacturing a semiconductor device, characterized in that the same as the step of performing the post-cleaning process. The method of claim 11, The post-cleaning process is a semiconductor device manufacturing method characterized in that the progress using a cleaning liquid containing an etchant having a higher etching rate for the first gate conductive film than the second gate conductive film.

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