KR20100128852A - Solar cell including barrier layer and method for fabricating of the same - Google Patents

Abstract

PURPOSE: A solar cell including barrier layer and a method for fabricating of the same are provided to restrain the delamination phenomenon of a semiconductor layer by improving the interfacial properties between the bottom electrode and the semiconductor layer. CONSTITUTION: A bottom electrode(110) is formed on a substrate(100). A barrier layer(130) is formed on the bottom electrode. A semiconductor layer(200) is formed on the barrier layer. A top electrode(300) is formed on the semiconductor layer. The metal silicide layer is formed between the barrier layer and the semiconductor layer.

Description

SOLAR CELL INCLUDING BARRIER LAYER AND METHOD FOR FABRICATING OF THE SAME}

The present invention relates to a solar cell and a manufacturing method comprising a barrier layer. In more detail, it is possible to prevent diffusion of impurities into the semiconductor layer in which photoelectric conversion is performed and to improve interfacial characteristics, and to include a barrier layer capable of forming a metal silicide layer on a junction surface with the semiconductor layer by low temperature heat treatment. It relates to a solar cell and a manufacturing method.

In the field of thin film type solar cells using a semiconductor layer, a polycrystalline semiconductor layer is mainly used to improve photoelectric conversion efficiency. For example, when the semiconductor layer is silicon, the photoelectric conversion efficiency of the solar cell is improved when polycrystalline silicon is used rather than amorphous silicon. In general, a polycrystalline silicon solar cell is manufactured by forming an amorphous silicon layer and crystallizing the amorphous silicon layer by a solid phase crystallization method or the like.

However, in order to fabricate a polycrystalline silicon solar cell, when the amorphous silicon is crystallized, predetermined impurities included in the lower electrode are light because amorphous silicon is formed on the lower electrode and then a high temperature heat treatment is performed for crystallization. There was a problem in that the diffusion layer to the silicon layer.

In addition, the high temperature heat treatment may cause unnecessary chemical reactions, resulting in deterioration of device characteristics and interfacial properties, resulting in a phenomenon that the silicon layer is peeled off.

In addition, such a decrease in interface characteristics also has a problem of lowering the electrical conductivity of the solar cell.

Problems that may occur in the production of the polycrystalline silicon solar cell as described above may act as an important factor to reduce the photoelectric conversion efficiency of the solar cell formed in the silicon layer.

Accordingly, the present invention has been made to solve the above problems of the prior art, a barrier layer which can prevent the diffusion of impurities in the semiconductor layer (for example, silicon layer) and improve the interface characteristics Its purpose is to provide a solar cell and a manufacturing method comprising the same.

In addition, another object of the present invention is to provide a solar cell and a manufacturing method further comprising a metal silicide layer capable of improving conductivity at a junction between the semiconductor layer and the barrier layer.

The object of the present invention is a substrate; A lower electrode formed on the substrate; A barrier layer formed on the lower electrode; A semiconductor layer formed on the barrier layer; And an upper electrode formed on the semiconductor layer.

In addition, the object of the present invention comprises the steps of (a) providing a substrate; (b) forming a lower electrode on the substrate; (c) forming a barrier layer on the lower electrode; (d) forming a semiconductor layer on the barrier layer; (e) is also achieved by a method of manufacturing a solar cell comprising the step of forming an upper electrode on the semiconductor layer.

In this case, the barrier layer may include any one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd or Pt, and a group containing them. .

The barrier layer may have a multilayer structure including a layer made of any one of the above groups.

A metal silicide layer may be further formed between the barrier layer and the semiconductor layer.

The lower electrode may be any one of AZO (ZnO: Al), ITO (Indium-Tin-Oxide), GZO (ZnO: Ga), BZO (ZnO: B), SnO ₂ (SnO ₂ : F).

The step (d) may further include forming a metal silicide layer based on the bonding surface of the barrier layer and the semiconductor layer.

According to the present invention, a barrier layer is provided between the lower electrode and the semiconductor layer to prevent diffusion of impurities into the semiconductor layer and to improve the interface characteristics (adhesive force).

In addition, according to the present invention, a metal silicide layer may be further provided between the barrier layer and the silicon layer to more effectively prevent diffusion of impurities into the silicon layer, and at the same time, to improve electrical conductivity.

Moreover, according to this invention, the photoelectric conversion efficiency of a solar cell can be improved by the above effect.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. In the drawings, like reference numerals refer to the same or similar functions throughout the several aspects, and length, area, thickness, and the like may be exaggerated for convenience.

DETAILED DESCRIPTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

Example 1

1A and 1B illustrate a solar cell including a barrier layer 120 according to Embodiment 1 of the present invention.

First, referring to FIG. 1A, a substrate 100 is provided, and the material of the substrate 100 may be a transparent material or an opaque material. For example, it may be glass, plastic, silicon, and metal (eg, SUS or Invar).

In this case, a texturing process may be performed on the surface of the substrate 100, wherein the texturing is to prevent optical loss due to reflection of light incident from the substrate surface of the solar cell, and to roughen the surface of the substrate. will be. That is, it may mean comprehensively to form an uneven pattern on the substrate surface. If the surface of the substrate is roughened by such texturing, the light reflected once from the surface is re-reflected to reduce the reflectance of the incident light, thereby increasing the amount of light trapped in the photoelectric device, thereby improving the photoelectric conversion efficiency of the solar cell.

Subsequently, a lower electrode 110 of a conductive material may be formed on the substrate 100. The material of the lower electrode 110 may be a transparent conductive oxide (TCO), which is a transparent electrode having a low contact resistance and having a transparent property. For example, AZO (ZnO: Al), ITO (Indium-Tin-Oxide), and GZO (ZnO: Ga), BZO (ZnO: B), and SnO ₂ (SnO ₂ : F) may be any one, but are not limited thereto, and a conventional conductive material may be used without limitation.

The lower electrode 110 may be formed by physical vapor deposition (PVD), such as thermal evaporation, e-beam evaporation, or sputtering, and LPCVD, PECVD, and metal organic compounds. Chemical Vapor Deposition (CVD), such as Metal Organic Chemical Vapor Deposition (MOCVD).

Subsequently, the barrier layer 120 may be formed on the lower electrode 110. The barrier layer 120 may function to prevent diffusion of impurities from the lower electrode 110 into another layer, in particular, a semiconductor layer such as the silicon layer 200 formed thereon. The peeling phenomenon may be reduced by improving the interface property between the semiconductor layer 110 and the semiconductor layer. The barrier layer 120 may be formed using physical vapor deposition (PVD) or chemical vapor deposition (CVD), such as sputtering.

In this case, the barrier layer 120 may include any one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, or Pt and a group containing them. For example, TiN and AlN may be formed, but the present invention is not limited thereto. More preferably, it may be a multi-layer structure including a layer made of any one of the above-described group in order to effectively prevent peeling phenomenon and diffusion between layers. As an example, a Ti / TiN / Ti structure may be used, but the present invention is not limited thereto, and it will be apparent that other numbers of layers and stacking orders are included in the present invention.

Next, referring to FIG. 1B, p-type and n-type or p-type, i-type, and n-type semiconductor layers may be stacked and formed on the barrier layer 120. The case where the n-type silicon layer 200 is formed in order will be described. The silicon layer 200 may be formed by a CVD method such as PECVD or LPCVD, and the silicon layer 200 may perform a function of an optoelectronic device that may receive power by producing a power by a subsequent process. .

Subsequently, the upper electrode 300 may be formed on the silicon layer 200. The upper electrode 300 may be any one of ITO, ZnO, IZO, AZO (ZnO: Al), and FSO (SnO: F) as a transparent conductive material, but is not limited thereto, and a conventional conductive material may be used without limitation. have. As the method of forming the upper electrode 300, a PVD method such as sputtering and a CVD method such as LPCVD, PECVD, and MOCVD may be used.

As described above, the solar cell including the barrier layer 120 between the lower electrode 110 and the silicon layer 200 can easily prevent the diffusion of impurities from the lower electrode 110 to the silicon layer 200. . In addition, the barrier layer 120 may improve the interface property (adhesive force) between the lower electrode 110 and the silicon layer 200, thereby reducing the phenomenon that the silicon layer 200 is peeled off.

[Example 2]

In the solar cell according to the second embodiment of the present invention, the metal silicide layer 130 is added to the solar cell of the first embodiment with reference to FIGS. 1A and 1B. Therefore, in the following Embodiment 2, other detailed descriptions except the process of forming the metal silicide layer 130 are omitted in order to avoid duplication of description.

FIG. 2 is a diagram illustrating a solar cell including a barrier layer 120 and a metal silicide layer 130 according to a second embodiment of the present invention.

Referring to FIG. 2, the silicon layer 200 may be formed on a layer in which the substrate 100, the lower electrode 110, and the barrier layer 120 are sequentially formed. In this case, a low temperature heat treatment process (crystallization temperature to be described later) By means of lower temperature), the metal silicide layer 130 may be formed based on the bonding surface of the barrier layer 120 and the silicon layer 200.

In more detail, by performing a low temperature heat treatment on the entire substrate 100, the metal component of the barrier layer 120 and the silicon (Si) of the silicon layer 200 are formed at the bonding surface of the barrier layer 120 and the silicon layer 200. ) May be chemically bonded to the metal silicide layer 130. For example, when the barrier layer 120 is TiN, heat treatment may be performed at low temperature (eg, 350 ° C.) to generate titanium silicide (TiSi _x ) in which Ti and Si are bonded. In addition, even when the barrier layer 120 is Ti / TiN / Ti, titanium silicide (TiSi _x ) in which Ti and Si are combined may be generated through a low temperature heat treatment process.

Meanwhile, the metal silicide layer 130 may be generated through a separate low temperature heat treatment process as described above, but in some cases, the low temperature heat treatment process may be omitted and may be generated through a crystallization heat treatment process of the silicon layer 200 in the future. Note that it may be.

Meanwhile, another modified method may be used to control the material and the uniformity of the metal silicide layer 130.

First, a separate metal layer (not shown) may be further formed on the barrier layer 120. The metal layer may be Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, or Pt. Preferably, nickel (Ni) for easy reaction control Can be used. The metal layer may be deposited by a PVD method, and then nickel silicide may be generated by combining with silicon (Si) of the silicon layer 200 by a low temperature heat treatment process.

In addition, a buffer layer (not shown) made of any one of p-type, i-type, and n-type amorphous silicon may be further formed on the metal layer, and then a low temperature heat treatment may be performed to obtain a more uniform metal silicide layer 130. There is a way.

In addition, the metal silicide layer 130 may be formed on the barrier layer 120 from the beginning.

Accordingly, the solar cell including the barrier layer 120 and the metal silicide layer 130 may include a double layer to more effectively prevent the diffusion of impurities into the silicon layer 200 and the conductivity. It is possible to improve the electrical conductivity of the solar cell by having a high metal silicide layer is electrically connected (in particular, it is possible to connect different unit cells through the metal silicide layer).

Barrier layer  Equipped Polycrystalline  Silicon solar cells

3A and 3B are diagrams illustrating the configuration of the silicon layer 200 according to the embodiment of the present invention.

First, referring to FIG. 3A, for example, three layers of amorphous silicon layers 210, 220, and 230 may be formed in the silicon layer 200.

In more detail, the first amorphous silicon layer 210 is formed on the metal silicide layer 130, and then the second amorphous silicon layer 220 is formed on the first amorphous silicon layer 210, and then the lower agent is formed. The third amorphous silicon layer 230 may be formed on the second amorphous silicon layer 220 to form one optoelectronic device. In this case, the first, second, and third amorphous silicon layers 210, 220, and 230 may be formed using a CVD method such as PECVD or LPCVD.

Next, referring to FIG. 3B, the first, second, and third amorphous silicon layers 210, 220, and 230 are subjected to high temperature heat treatment (in this case, the high temperature heat treatment is compared with the low temperature heat treatment in the process of forming the metal silicide layer 130). Means a high temperature) to crystallize. That is, the first amorphous silicon layer 210 is the first polycrystalline silicon layer 211, the second amorphous silicon layer 220 is the second polycrystalline silicon layer 221, and the third amorphous silicon layer 230 is formed of the first amorphous silicon layer 210. Each of the three polycrystalline silicon layers 231 may be crystallized. As a result, an optoelectronic device including the first, second, and third polycrystalline silicon layers 211, 221, and 231 is formed on the metal silicide layer 130.

Such an optoelectronic device may have a structure of a pin diode in which p-type, i-type, and n-type polycrystalline silicon layers, in which a polycrystalline silicon layer is stacked, may generate power with photovoltaic power generated by receiving light, are sequentially stacked. . Type i here means intrinsic without impurities. In addition, n-type or p-type doping is preferably doped with impurities in situ (in situ) when forming the amorphous silicon layer. Boron (B) is used as an impurity in p-type doping, and phosphorus (P) or arsenic (As) is used as an impurity in n-type doping, but the present invention is not limited thereto, and known techniques may be used without limitation.

In this case, the crystallization methods of the first, second, and third amorphous silicon layers 210, 220, and 230 may include solid phase crystallization (SPC), excimer laser annealing (ELA), sequential lateral solidification (SLS), and metal induced crystallization (MIC). ) And MILC (Metal Induced Lateral Crystallization) can be used. Since the crystallization method of the amorphous silicon is a known technique, a detailed description thereof will be omitted herein.

In the above description, the first, second, and third amorphous silicon layers 210, 220, and 230 are all formed, and the layers are simultaneously crystallized, but the present invention is not limited thereto. For example, the crystallization process may be performed separately for each amorphous silicon layer, and the two amorphous silicon layers may simultaneously undergo a crystallization process and the other amorphous silicon layer may be separately crystallized.

Although not shown, the first polycrystalline silicon layer 211, the second polycrystalline silicon layer 221, and the third polycrystalline silicon layer 231 may further perform a defect removal process to further improve the properties of the polycrystalline silicon. have. In the present invention, the polycrystalline silicon layer may be subjected to high temperature heat treatment or hydrogen plasma treatment to remove defects (eg, impurities and dangling bonds) present in the polycrystalline silicon layer.

Meanwhile, another optoelectronic device may be further formed on the optoelectronic device described above. The other optoelectronic device may have a structure in which an amorphous silicon layer is stacked (that is, a tandem structure). In addition, the above-described optoelectronic devices may be stacked in double or more, and the optoelectronic devices may use a p-n type instead of a p-i-n type.

In the foregoing detailed description, the present invention has been described by specific embodiments such as specific components and the like, but the embodiments and drawings are provided only to help a more general understanding of the present invention, and the present invention is limited to the above embodiments. However, one of ordinary skill in the art can make various modifications and variations from this description.

Therefore, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, I will say.

1A and 1B illustrate a solar cell including a barrier layer 120 according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating a solar cell including a barrier layer 120 and a metal silicide layer 130 according to a second embodiment of the present invention.

3A and 3B are diagrams illustrating the configuration of the silicon layer 200 according to the embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: substrate

110: lower electrode

120: barrier layer

130: metal silicide

200: silicon layer

300: upper electrode

Claims (7)

Board; A lower electrode formed on the substrate; A barrier layer formed on the lower electrode; A semiconductor layer formed on the barrier layer; And An upper electrode formed on the semiconductor layer Solar cell comprising a. The method of claim 1, The barrier layer comprises any one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd or Pt and the group containing them. Solar cells. The method of claim 2, The barrier layer is a solar cell, characterized in that the multi-layer structure including a layer consisting of any one of the group. The method of claim 1, And a metal silicide layer is further formed between the barrier layer and the semiconductor layer. The method of claim 1, The lower electrode may be any one of AZO (ZnO: Al), ITO (Indium-Tin-Oxide), GZO (ZnO: Ga), BZO (ZnO: B), and SnO ₂ (SnO ₂ : F). Solar cells. (a) providing a substrate; (b) forming a lower electrode on the substrate; (c) forming a barrier layer on the lower electrode; (d) forming a semiconductor layer on the barrier layer; And (e) forming an upper electrode on the semiconductor layer Method for manufacturing a solar cell comprising a. The method of claim 6, The step (d) further comprises the step of forming a metal silicide layer on the basis of the junction surface of the barrier layer and the semiconductor layer.

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