KR20100128751A - Method for fabricating thin film transistor and method for fabricating display device having thin film transistor - Google Patents

Abstract

PURPOSE: A manufacturing method and a display device manufacturing method thereof are provided to improve the reliability of a thin film transistor by executing the crystallization process of a semiconductor pattern. CONSTITUTION: A gate electrode(8) is formed on a substrate(1). A gate insulating layer(16), which has at least two first holes(18), is formed on the substrate. A semiconductor pattern(14) is formed on the gate insulating layer. A conductive layer(10a), which is contacted with the gate electrode through the first hole, is formed. The semiconductor pattern is crystallized by applying an electric field to the conductive layer.

Description

A manufacturing method of a thin film transistor and a manufacturing method of a display device including the thin film transistor {METHOD FOR FABRICATING THIN FILM TRANSISTOR AND METHOD FOR FABRICATING DISPLAY DEVICE HAVING THIN FILM TRANSISTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor having a bottom gate structure and a display device having the same, and more particularly, to a method of manufacturing a thin film transistor which can improve the reliability of a thin film transistor by performing a crystallization process on a thin film transistor having a bottom gate structure. And a display device including a thin film transistor.

The liquid crystal display device includes a liquid crystal display panel and a driver for driving the liquid crystal display panel. The liquid crystal display panel includes a color filter array substrate and a thin film transistor array substrate bonded together with a liquid crystal interposed therebetween.

The color filter array substrate includes a color filter and a black matrix, and the thin film transistor array substrate includes a gate line and a data line crossing each other, a thin film transistor formed between the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like. do.

Organic electroluminescent display devices (hereinafter, abbreviated as "EL") are self-luminous devices that emit light by themselves, and have fast response speed, high luminous efficiency, brightness, and viewing angle. In addition, the organic EL display device is driven at a low DC voltage of several tens of volts, has a fast response speed, obtains high luminance, and emits various colors of R, G, and B, which is suitable for next-generation flat panel display devices. The organic EL display device includes a thin film transistor array portion formed on a transparent substrate, an organic EL array portion located on the thin film transistor array portion, and a cap for isolating the organic EL array portion from an external environment. The thin film transistor array unit includes switching elements such as a driving thin film transistor and a switching thin film transistor.

The structure of the thin film transistor included in the thin film transistor array substrate of the liquid crystal display panel and the thin film transistor array portion of the organic EL display device is largely divided into a bottom gate type thin film transistor and a top gate type thin film transistor. In general, a semiconductor layer of a top gate thin film transistor has an advantage of being more reliable than a bottom gate thin film transistor as a crystallization process may be performed. However, the top gate thin film transistor has a disadvantage in that the manufacturing cost is high and the manufacturing process is complicated compared to the bottom gate thin film transistor. Accordingly, a method of performing a crystallization process on a bottom gate type thin film transistor has been continuously studied.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to perform a crystallization process in a thin film transistor having a bottom gate structure, thereby improving the reliability of the thin film transistor. And it provides a method of manufacturing a display device including a thin film transistor.

In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention comprises the steps of forming a gate electrode on a substrate; Forming a gate insulating film having at least two first holes exposing the gate electrode on the substrate and forming a semiconductor pattern on the gate insulating film; Forming a conductive layer formed on the semiconductor pattern and in contact with the gate electrode through the first hole; Crystallizing the semiconductor pattern by applying an electric field to the conductive layer; Patterning the conductive layer to form a source electrode and a drain electrode in contact with the semiconductor pattern.

The conductive layer and the gate electrode are characterized in that they are equipotential to each other.

A method of manufacturing a display device including a thin film transistor according to the present invention includes forming a gate pattern on a substrate, the gate pattern including a gate electrode, a gate line connected to the gate electrode, and a gate pad lower electrode connected to the gate line; Forming a gate insulating film having at least two first holes exposing the gate pattern on the gate pattern, and forming a semiconductor pattern on the gate insulating film; Forming a conductive layer formed on the semiconductor pattern and in contact with the gate pattern through the first hole; Crystallizing the semiconductor pattern by applying an electric field to the conductive layer; Patterning the conductive layer to form a data line crossing the gate line and a data pad lower electrode connected to the data line, and forming a thin film transistor including the gate electrode and the semiconductor pattern; Forming a protective film having a second hole exposing a portion of the thin film transistor, a third hole exposing the gate pad lower electrode, and a fourth hole exposing the data pad lower electrode; A pixel electrode in contact with the thin film transistor through the second hole, a gate pad upper electrode connected to the gate pad lower electrode through the third hole, and a data pad connected to the data pad lower electrode through the fourth hole Forming a transparent electrode pattern including an upper electrode characterized in that it comprises a.

A method of manufacturing a display device including a thin film transistor according to the present invention includes forming a thin film transistor array unit on a substrate; And forming an organic light emitting array on the thin film transistor array, wherein forming the thin film transistor array comprises forming a gate pattern on the substrate, the gate pattern including a gate line and a gate electrode connected to the gate line; ; Forming a gate insulating film having at least two first holes exposing a gate pattern on the substrate and forming a semiconductor pattern on the gate insulating film; Forming a conductive layer formed on the semiconductor pattern and in contact with the gate pattern through the first hole; Crystallizing the semiconductor pattern by applying an electric field to the conductive layer; Patterning the conductive layer to form a data line crossing the gate line, and forming a thin film transistor including the gate electrode and the semiconductor pattern.

The organic light emitting array includes a plurality of organic light emitting cells arranged in a matrix form, the thin film transistor is characterized in that the driving element for supplying a driving voltage to the organic light emitting cell.

The conductive layer and the gate electrode are characterized in that they are equipotential to each other.

As described above, the manufacturing process according to the present invention enables crystallization of a semiconductor pattern in a thin film transistor having a simple bottom gate structure, thereby improving electron mobility and lifetime of the thin film transistor having a bottom gate structure. It is possible to improve the reliability of the thin film transistor. In addition, the semiconductor pattern can be crystallized in the bottom gate structure thin film transistor used in the liquid crystal display panel and the organic EL display device. Accordingly, the reliability of the display device as well as the thin film transistor can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view illustrating a thin film transistor having a bottom gate structure according to an exemplary embodiment of the present invention.

In the thin film transistor having a bottom gate structure shown in FIG. 1, the thin film transistor 6 may include a gate electrode 8, a source electrode 10, a drain electrode 12 facing the source electrode 10, formed on the substrate 1, A semiconductor pattern 14 overlapping the gate electrode 8 and including a channel between the source electrode 10 and the drain electrode 12, and positioned between the semiconductor pattern 14 and the gate electrode 8 to form a semiconductor pattern 14. ) And a gate insulating film 16 that electrically insulates the gate electrode 8 from each other.

The semiconductor pattern 14 is further disposed on the active layer 11 and the active layer 11 to further form an ohmic contact layer 9 for ohmic contact with the source electrode 10 and the drain electrode 12. In the liquid crystal display panel, the thin film transistor 6 keeps the pixel voltage signal supplied to the data line charged in the pixel electrode in response to the gate signal supplied to the gate line. The organic light emitting display device is used as a driving element or a switching element of the thin film transistor array unit.

Although the thin film transistor of FIG. 1 has a bottom gate structure, the semiconductor pattern 14 is in a state in which it is crystallized by a Joule heating crystallization process.

Hereinafter, a manufacturing process of a thin film transistor including a process in which amorphous silicon is crystallized into polysilicon will be described with reference to FIGS. 2A to 2F.

First, a gate metal layer is formed on the substrate 1 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a mask to form the gate electrode 8 as shown in FIG. 2A. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

The gate insulating layer 16, the amorphous silicon layer, and the n + amorphous silicon layer are formed on the substrate 1 on which the gate patterns are formed through a deposition method such as PECVD. Subsequently, an amorphous silicon layer and an n + amorphous silicon layer are patterned by a photolithography process and an etching process using a mask process to form an ohmic contact layer 9 and an active layer 11 on the gate insulating layer 16 as shown in FIG. 2B. A semiconductor pattern 14 is formed.

Thereafter, the gate insulating layer 16 is patterned by a photolithography process and an etching process using a mask to form at least two first holes 18 exposing the gate electrode 8, as shown in FIG. 2C.

The conductive layer 10a is formed on the substrate 1 on which the semiconductor pattern 14 and the first hole 18 are formed, as shown in FIG. 2D through a deposition method such as sputtering. Here, the conductive layer 10a is in contact with the gate electrode 8 through at least two first holes 18.

Thereafter, as shown in FIG. 2E, a strong electric field is applied to the conductive layer 10a to generate high heat instantaneously by Joule heating. High heat is heat generated by resistance when current flows in a conductive layer.

The amount of energy per unit time applied to the conductive layer 10a by Joule heating due to application to an electric field may be represented by the following equation.

W = V × I

W represents the amount of energy per unit time, V represents the voltage across the conductive layer, and I represents the current. It can be seen from Equation 1 that a high electric field is instantaneously generated by Joule heating since a strong electric field is applied to the conductive layer 10a.

The high heat is conducted to the semiconductor pattern 14 under the conductive layer 10a, so that the semiconductor pattern 14 is crystallized as the heat treatment proceeds rapidly.

Here, as the conductive layer 10a is in contact with the gate electrode 8 through the two first holes 18, the equipotential is formed between the conductive layer 10a and the gate electrode 8 so that a potential difference does not occur. As a result, no arc is generated during the heat treatment.

This will be described in more detail as follows.

When the conductive layer 10a and the gate electrode 8 do not electrically form an equipotential, a potential difference occurs between the conductive layer and the conductive layer peripheral material in the vertical direction of the electric field applied to the conductive layer. When this potential difference exceeds the dielectric breakdown voltage of the gate insulating film 16, a current flows in the gate insulating film 16 and an arc is generated. As a result, damage to not only the gate insulating film 16 but also the gate electrode 80 occurs.

In order to prevent this, in the present invention, first holes 18 are formed through the gate insulating layer 16 to expose the gate electrode 8, and the conductive layer 10a and the gate are formed through the first holes 18. The electrode 8 is brought into contact. Accordingly, the conductive layer 10a and the gate electrode 8 can form an equipotential, thereby preventing arc generation. Through this structural deformation, the semiconductor pattern 14 may be crystallized in the thin film transistor 6 having the bottom gate structure.

Subsequently, the conductive layer 10a is patterned by a photolithography process and an etching process using a mask to form the source electrode 10 and the drain electrode 12 as shown in FIG. 2F, as well as the source electrode 10 and the drain. As the ohmic contact layer 12 is removed between the electrodes 12, the active layer 14 of the channel region is exposed. Here, the source electrode 10 and the drain electrode 12 are electrically separated from the gate electrode 8.

As described above, the method for manufacturing a thin film transistor according to the present invention enables crystallization of a semiconductor pattern in a thin film transistor having a bottom gate structure with a simple manufacturing process. Accordingly, it is possible to improve the reliability of the thin film transistor having the bottom gate structure, such as to improve the electron mobility and the lifetime of the thin film transistor having the bottom gate structure.

3 is a cross-sectional view illustrating a thin film transistor array substrate of a liquid crystal display panel among display devices including a thin film transistor formed by the manufacturing method illustrated in FIGS. 2A to 2F.

The thin film transistor array substrate illustrated in FIG. 3 includes a gate line 2 and a data line (not shown) formed to intersect on the substrate 1 with a gate insulating layer 16 interposed therebetween, and the thin film transistor 6 formed at each intersection thereof. ) And the pixel electrode 19 formed in the cell region provided in the intersection structure. The thin film transistor array substrate includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 19 and the front gate line 2, a gate pad portion 26 connected to the gate line 2, and a data line. And a data pad portion 34 connected to it.

The thin film transistor 6 overlaps the gate electrode 8, the source electrode 10, the drain electrode 12 facing the source electrode 10, and the gate electrode 8 formed on the substrate 1 and the source electrode 10. ) Between the semiconductor pattern 14 including the channel and the semiconductor pattern 14 and the gate electrode 8 between the drain electrode 12 and the drain electrode 12 to electrically insulate the semiconductor pattern 14 from the gate electrode 8. A gate insulating film 16 is provided.

The semiconductor pattern 14 is further disposed on the active layer 11 and the active layer 11 to further form an ohmic contact layer 9 for ohmic contact with the source electrode 10 and the drain electrode 12. In the liquid crystal display panel, the thin film transistor 6 keeps the pixel voltage signal supplied to the data line charged in the pixel electrode in response to the gate signal supplied to the gate line 2.

The pixel electrode 19 is connected to the drain electrode 12 of the thin film transistor 6 through the second hole 21 penetrating the protective film 50. The pixel electrode 19 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. This potential difference causes the liquid crystal located between the thin film transistor substrate and the upper substrate to rotate by dielectric anisotropy, and transmits light incident through the pixel electrode 19 from the light source (not shown) toward the upper substrate.

The storage capacitor 20 includes the front gate line 2, the front gate line 20, the gate insulating layer 16, and the pixel electrode 19 overlapping each other with the passivation layer 50 interposed therebetween. The storage capacitor 20 allows the pixel voltage charged in the pixel electrode 19 to be stably maintained until the next pixel voltage is charged.

The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad portion 26 is formed through the gate pad lower electrode 28 extending from the gate line 2, and the third gate 30 penetrating through the gate insulating layer 16 and the passivation layer 50. And a gate pad upper electrode 32 connected thereto.

The data line (not shown) is connected to a data driver (not shown) through the data pad unit 34. The data pad part 34 is connected to the data pad lower electrode 36 through the data pad lower electrode 36 extending from the data line 4 and the fourth hole 38 penetrating through the passivation layer 50. The pad upper electrode 40 is formed.

In the thin film transistor array substrate of FIG. 3, although the thin film transistor 6 has a bottom gate structure, the semiconductor pattern 14 is crystallized by a Joule heating crystallization process.

Hereinafter, a manufacturing process of the thin film transistor array substrate of FIG. 3 including a process in which amorphous silicon is crystallized into polysilicon will be described with reference to FIGS. 4A to 4H.

First, a gate metal layer is formed on the substrate 1 through a deposition method such as a sputtering method. Subsequently, as the gate metal layer is patterned by a photolithography process and an etching process using a mask, a gate pattern including the gate line 2, the gate electrode 8, and the gate pad lower electrode 28 as shown in FIG. 4A. Are formed.

As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or double layer structure.

The gate insulating layer 16, the amorphous silicon layer, and the n + amorphous silicon layer are formed on the substrate 1 on which the gate patterns are formed through a deposition method such as PECVD. Subsequently, the amorphous silicon layer and the n + amorphous silicon layer are patterned by a photolithography process and an etching process using a mask process to form an ohmic contact layer 9 and an active layer 11 on the gate insulating layer 16 as shown in FIG. 4B. A semiconductor pattern 14 is formed.

Thereafter, the gate insulating layer 16 is patterned by a photolithography process and an etching process using a mask to form at least two first holes 18 exposing the gate electrode 8 as shown in FIG. 4C.

The conductive layer 10a is formed on the substrate 1 on which the semiconductor pattern 14 and the first holes 18 are formed as shown in FIG. 4D through a deposition method such as sputtering. Here, the conductive layer 10a is in contact with the gate electrode 8 through at least two first holes 18.

Thereafter, as shown in FIG. 4E, a strong electric field is applied to the conductive layer 10a to generate high heat instantaneously by Joule heating.

The high heat is conducted to the semiconductor pattern 14 under the conductive layer 10a, so that the semiconductor pattern 14 is crystallized as the heat treatment proceeds rapidly.

Here, as the conductive layer 10a is in contact with the gate electrode 8 through the two first holes 18, the equipotential is formed between the conductive layer 10a and the gate electrode 8 so that a potential difference does not occur. As a result, no arc is generated during the heat treatment.

Then, the conductive layer 10a is patterned by a photolithography process using a mask and a wet etching process, so that the source electrode 10, the drain electrode 12, the data line, and the data pad lower electrode 36 are shown in FIG. 4F. The active layer 11 of the channel region is exposed by forming a source / drain pattern including the N and an ohmic contact layer 9 between the source electrode 10 and the drain electrode 12. Here, the source electrode 10 and the drain electrode 12 are electrically separated from the gate electrode 8.

Then, as illustrated in FIG. 4G, the second to fourth holes 21, 30, and 38 are included on the gate insulating layer 16 on which the source / drain patterns are formed by a photolithography process and an etching process using a mask. A protective film 50 is formed. Here, the second hole 21 exposes the drain electrode 12 of the thin film transistor 60, the third hole 30 exposes the gate pad lower electrode 28, and the fourth hole 38 represents data. The pad lower electrode 36 is exposed.

Subsequently, as shown in FIG. 4H, the transparent electrode material is entirely deposited on the substrate 1 on which the protective film 50 is formed by a deposition method such as sputtering, and then the photolithography process and an etching process using a mask. The material is patterned to form transparent electrode patterns including the pixel electrode 19, the gate pad upper electrode 32, and the data pad upper electrode 40.

As described above, the method of manufacturing a thin film transistor array substrate according to the present invention enables crystallization of a semiconductor pattern in a thin film transistor having a bottom gate structure with a simple manufacturing process. Accordingly, it is possible to improve the reliability of the thin film transistor having the bottom gate structure, such as to improve the electron mobility and the lifetime of the thin film transistor having the bottom gate structure.

FIG. 5 is a cross-sectional view illustrating an organic EL display device among display devices including a thin film transistor formed by the manufacturing method illustrated in FIGS. 2A to 2F. FIG. A circuit diagram schematically showing P).

First, referring to FIG. 6, the organic EL display device has a structure in which pixels P, which are respectively provided in regions defined by intersections of the gate line GL and the data line DL, are arranged in a matrix form. Each pixel P receives a data signal from the data line DL when a gate pulse is supplied to the gate line GL, and generates light corresponding to the data signal.

For this purpose, each of the pixels P is connected to an organic EL cell EL having a cathode connected to a base voltage source GND, a gate line GL, a data line DL, and a supply voltage source VDD, and an organic EL. It is provided with the cell drive part 60 connected to the anode of the cell EL, and for driving the organic EL cell EL. The cell driver 152 includes a switching thin film transistor T1, a driving thin film transistor T2, and a capacitor C.

The switching thin film transistor T1 is turned on when a scan pulse is supplied to the gate line GL, and supplies the data signal supplied to the data line DL to the first node N1. The data signal supplied to the first node N1 is charged to the capacitor C and supplied to the gate terminal of the driving thin film transistor T2. The driving thin film transistor T2 controls the amount of light emitted from the organic EL cell EL by controlling the amount of current I supplied from the supply voltage source VDD to the organic EL cell EL in response to a data signal supplied to the gate terminal. Done. Since the data signal is discharged from the capacitor C even when the switching thin film transistor T1 is turned off, the driving thin film transistor T2 is a current from the supply voltage source VDD until the data signal of the next frame is supplied. (I) is supplied to the organic EL cell EL so that the organic EL cell EL maintains light emission.

As shown in FIG. 5, the organic EL display device includes a thin film transistor array unit 115 formed on the transparent substrate 102, an organic EL array unit 120 positioned on the thin film transistor array unit 115. A glass cap 152 is provided to isolate the organic EL array 120 from the external environment.

The thin film transistor array unit 115 includes driving elements for driving the organic EL cell EL, such as the gate line, the data line, and the cell driver 160 of FIG. 1 or 5.

The organic EL array 120 includes organic EL cells EL connected to the driving thin film transistor T of the thin film transistor array 115 in a matrix form.

The organic EL cell EL is a first electrode (or "anode electrode") 104 connected to the driving thin film transistor T2, and a bank (or "insulating film") for separating each pixel ( 6) an organic light emitting layer 10 and a second electrode (or "cathode electrode") 112. In this case, the organic light emitting layer 110 includes an electron injection layer, an electron transporting layer, a light emitting layer, a hole transporting layer, and a hole injection layer, and the light emitting layer is formed of any one of red (R), green (G), and blue (B). Will be implemented.

The organic EL cells EL of the organic EL array 120 have a property of being easily degraded by moisture and oxygen. In order to solve this problem, an encapsulation process is performed to bond the substrate 102 and the glass cap 152 on which the organic EL array 120 is formed through the sealant 126. The glass cap 152 emits heat generated during light emission and protects the organic EL array unit 120 from external force or oxygen and moisture in the atmosphere.

The glass cap 152 is provided with a groove 152a on the surface facing the organic EL array 120, and the moisture absorbent 154 is positioned in the groove 152a.

In the organic EL display device having such a configuration, the thin film transistors T such as the switching thin film transistor T1 and the driving thin film transistor T2 are formed by the manufacturing method shown in Figs. 2A to 2F.

Hereinafter, a manufacturing method of the organic EL display device illustrated in FIG. 5 will be described.

First, a thin film transistor array unit 115 including a thin film transistor T such as a switching thin film transistor T1 and a driving thin film transistor T2 is formed on the substrate 102. Here, the thin film transistors T such as the switching thin film transistor T1 and the driving thin film transistor T2 are formed in the same manner as the method shown in Figs. 2A to 2F.

5, 6, and 2A to 2F, a method of manufacturing an organic EL display device includes a gate line GL and a gate electrode 8 connected to a gate line GL on a substrate 102. Forming a gate pattern, and forming a gate insulating layer 16 having at least two first holes 18 exposing the gate pattern on the substrate 102 and a semiconductor pattern positioned on the gate insulating layer 16. (14) forming a conductive layer (10a) formed on the semiconductor pattern 14 and in contact with the gate pattern through the first hole (18), applying an electric field to the conductive layer (10a) Crystallizing the semiconductor pattern 14, patterning the conductive layer 10a to form a data line DL crossing the gate line GL, and forming the gate electrode 8 and the semiconductor pattern 14. Forming a thin film transistor (6).

Here, the thin film transistor 6 is a switching thin film transistor T1 and a driving thin film transistor T2.

Subsequently, after the organic EL array 120 is formed, an encapsulation process is performed to bond the substrate 102 and the glass cap 152 on which the organic EL array 120 is formed through the sealant 126. Accordingly, the organic EL display device can crystallize the semiconductor pattern in the thin film transistor having the bottom gate structure with a simple manufacturing process. Accordingly, it is possible to improve the reliability of the thin film transistor having the bottom gate structure, such as to improve the electron mobility and the lifetime of the thin film transistor having the bottom gate structure.

As described above, in the present invention, the semiconductor pattern in the thin-film transistor having a simple bottom gate structure can be crystallized. The semiconductor pattern in the bottom gate structure thin film transistor used in the liquid crystal display panel and the organic EL display device can be crystallized.

Accordingly, the reliability of the display device as well as the thin film transistor can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

1 is a cross-sectional view showing a thin film transistor according to the present invention.

2A through 2F are cross-sectional views illustrating a method of manufacturing the thin film transistor illustrated in FIG. 1 in steps.

3 is a cross-sectional view illustrating a thin film transistor array substrate including the thin film transistor illustrated in FIG. 1.

4A through 4H are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 3.

FIG. 5 is a cross-sectional view illustrating an organic light emitting display device including the thin film transistor illustrated in FIG. 1.

FIG. 6 is a circuit diagram illustrating one pixel in the organic light emitting display device of FIG. 5. FIG.

* Brief description of symbols for the main parts of the drawings.

8 gate electrode 10 source electrode

12 drain electrode 18 first hole

16 gate insulating film 1102 substrate

6: thin film transistor 14: semiconductor pattern

9: ohmic contact layer 11: active layer

10a: conductive layer 28: gate pad lower electrode

2 gate line 26 gate pad portion

32: gate pad upper electrode 21: second hole

34: data pad portion 40: data pad upper electrode

30: third hole 38: fourth hole

50: protective film 19: pixel electrode

20: storage capacitor 152: cap

126: sealant 115: thin film transistor array unit

120: organic EL array 104: first electrode

110: organic light emitting layer 112: second electrode

Claims (7)

Forming a gate electrode on the substrate; Forming a gate insulating film having at least two first holes exposing the gate electrode on the substrate and forming a semiconductor pattern on the gate insulating film; Forming a conductive layer formed on the semiconductor pattern and in contact with the gate electrode through the first hole; Crystallizing the semiconductor pattern by applying an electric field to the conductive layer; Patterning the conductive layer to form a source electrode and a drain electrode in contact with the semiconductor pattern. The method of claim 1, The conductive layer and the gate electrode is a method of manufacturing a thin film transistor, characterized in that the equipotential with each other. Forming a gate pattern including a gate electrode on the substrate, a gate line connected to the gate electrode, and a gate pad lower electrode connected to the gate line; Forming a gate insulating film having at least two first holes exposing the gate pattern on the gate pattern and forming a semiconductor pattern on the gate insulating film; Forming a conductive layer formed on the semiconductor pattern and in contact with the gate pattern through the first hole; Crystallizing the semiconductor pattern by applying an electric field to the conductive layer; Patterning the conductive layer to form a data line crossing the gate line and a data pad lower electrode connected to the data line, and forming a thin film transistor including the gate electrode and the semiconductor pattern; Forming a protective film having a second hole exposing a portion of the thin film transistor, a third hole exposing the gate pad lower electrode, and a fourth hole exposing the data pad lower electrode; A pixel electrode in contact with the thin film transistor through the second hole, a gate pad upper electrode connected to the gate pad lower electrode through the third hole, and a data pad connected to the data pad lower electrode through the fourth hole A method of manufacturing a display device including a thin film transistor, comprising forming a transparent electrode pattern including an upper electrode. The method of claim 3, wherein The conductive layer and the gate electrode of the display device including a thin film transistor, characterized in that the equipotential with each other. Forming a thin film transistor array unit on the substrate; Forming an organic light emitting array on the thin film transistor array; Forming the thin film transistor array unit Forming a gate pattern on the substrate, the gate pattern including a gate line and a gate electrode connected to the gate line; Forming a gate insulating film having at least two first holes exposing a gate pattern on the substrate and forming a semiconductor pattern on the gate insulating film; Forming a conductive layer formed on the semiconductor pattern and in contact with the gate pattern through the first hole; Crystallizing the semiconductor pattern by applying an electric field to the conductive layer; Patterning the conductive layer to form a data line crossing the gate line, and forming a thin film transistor including the gate electrode and the semiconductor pattern. Manufacturing method. The method of claim 5, The organic light emitting array includes a plurality of organic light emitting cells arranged in a matrix form, The thin film transistor includes a thin film transistor including a thin film transistor, characterized in that the driving element for supplying a driving voltage to the organic light emitting cell. The method of claim 5, And the conductive layer and the gate electrode are equipotential to each other.

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