KR20100123799A - Probe block of method of manufacturing the silicon electrode substrate thereof - Google Patents

Abstract

PURPOSE: A silicon electrode manufacturing method is provided to have a separation prevention function between a probe block, a probe pin, and a contact pin which inspect a semiconductor chip where a circuit pattern is formed on a wafer. CONSTITUTION: An oxide film is deposited on the upper surface of a silicon substrate with a chemical vapor deposition process or a physical vapor deposition process. A photoresist is spread on a silicon substrate where the oxide film is deposited. A perpendicular penetration hole is patterned in the photoresist spread on the upper surface of the silicon substrate. The perpendicular penetration hole is processed in the silicon substrate in which the perpendicular penetration hole is patterned with a reactive ion etching method.

Description

Probe block of method of manufacturing the silicon electrode substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe block for semiconductor chip inspection, and more particularly, to a conductive wiring pattern added to a silicon electrode substrate of a probe block and to improved functionality and assemblability.

As is known, a probe card assembled with a probe block is a device for inspecting a defect of a semiconductor chip having a pattern formed on a wafer, and is used by being mounted on a prober device. The probe pin attached to the probe block uses tungsten wire. The blade-shaped MEMS probe pins are finely and uniformly processed by using needles or by using the CVD process, lithography process, etching process, metal plating process, planarization process (CMP), residue removal and cleaning process. It is produced and used.

1A, 1B, and 1C illustrate a conventional probe block head.

As shown in FIG. 1A, the probe head for semiconductor chip inspection is assembled into a plurality of probe blocks, such as a semiconductor chip region in which a pattern is formed by arranging a plurality of probe blocks in a row with semiconductor chips having a pattern formed on a wafer.

As shown in FIG. 1B, the probe block is made of a ceramic material to groove one side or both sides of the ceramic to process the probe slit groove. The ceramic material is strong so that the grooving depth and width are first set when the slit groove is processed. As the value of the slit groove processed to the numerical value and the middle of the slit groove is not processed the same as the value of the first processed slit groove, the slit groove is continuously processed with the last processed slit groove due to the cumulative tolerance generated during processing. In the processing dimensions of the slit grooves, a large number of processing errors occur, and the gap is broken when the gap between the slit grooves and the slit grooves is minute.

The probe block of FIGS. 1A and 1B has a structure in which the outside of the ceramic without the wiring pattern is simply machined to fix the probe pin with an adhesive to the processing part, and a screw hole is attached to both ends of the probe block to provide a probe block housing or a printed circuit board. It was difficult to detach the probe block by fastening the screw to the adhesive and fixing it with an adhesive. Also, the central part mounted on the longer length of the probe block generates fine lifting phenomenon when used in high temperature conditions.

As shown in Fig. 1C, there is a probe head made of a multi-layered circuit board (MLC) made of a single plate of the same size as a semiconductor chip formed on the entire wafer.

Conventional single-headed probe head is made of multilayer circuit board by molding ceramic and divided into transformer and interposer.

In recent years, the size of a probe head is required to be 12 inches in size. The reason is that wafer size is large and semiconductor chip manufacturing is manufactured with 12-inch wafers, so 12-inch wafers are inspected with the probe head # 1 touch.

In the future, manufacturing process equipment is being developed to manufacture semiconductor chips from 16-inch and 18-inch wafers. However, in the manufacture of ceramic multilayer circuit boards (MLC) made of single plate, the inner wiring pattern due to shrinkage when ceramic is sintered is shorted in manufacturing the size of the area more than 8 inches in width and length. Due to the difficulty of processing, supply becomes a problem.

Tens of thousands of pins must be assembled in the probe head of the probe card. However, due to the large size of the probe head, it is difficult to supply the material of the probe head and the delivery time is delayed.

The present invention has been proposed to solve the problems pointed out as a problem in the above, the vertical through the silicon substrate using the MEMS process using the electrode substrate of the probe block as the material of the silicon substrate of the same material as the thermal expansion coefficient It is made of a structure that can cope with the enlargement of the probe head by forming a hole and a horizontal groove.

In addition, in the method of fastening the probe block to the printed circuit board, an ejector is added to both ends of the contact block storage box without fastening the bolts at both ends of the probe block, so that the attachment and detachment is quick and the opening is formed at a predetermined interval in the length direction of the probe block. The hole is an empty opening hole, and the next opening hole is a bolt hole, which is to be fastened with a printed circuit board.

It is preferable that the intervals of the opening holes are formed at equal intervals. In addition, the fastening bolt can adjust the probe block Z axis flatness according to the degree of locking.

The probe block is a structure that is separated into a contact block and a connection block.

The contact block is a storage type and a silicon electrode substrate is stored therein.

In addition, the connection block is also an accommodating anisotropic electrode substrate therein.

The connection block is fixed and standardized and attached to the printed circuit board, and the contact block is replaced with only the contact block in the probe card during inspection of a memory semiconductor having a reduced circuit line width of the same storage capacity type. It can be reused.

As such, the price of printed circuit boards and equipment to be reused is excluded, which enables fast delivery and fast repair, and also reduces semiconductor chip inspection costs.

As described above, the present invention is a useful invention in which a probe block, a probe pin, and a contact pin, which can inspect a semiconductor chip on which a circuit pattern is formed on a wafer of 12 inches or more at once, have a function of preventing departure from a negative pad conducting electrode.

In addition, the probe block is composed of a contact block and a connection block in a detachable form, and the detachable type is to use the connection block as a standard type and replace only the contact block without having to manufacture a new probe card due to the change of the semiconductor device.

The ejector is attached to the detachable probe block, so if the problem occurs during use, the probe pin of the probe card is easy to replace and repair, so that only the corresponding contact block is detached and maintained, and the electrode substrate of the probe block is formed of a multilayer silicon electrode substrate and is energized. The pad may be formed as a negative pad so that the contact pin may be in contact with the conductive electrode negative pad, or the probe block may be selected according to the type of semiconductor to be tested to manufacture a probe card.

Hereinafter, the silicon electrode substrate manufacturing method and embodiment of the present invention and the specific effects obtained therefrom will be described in detail with reference to FIG. 5.

As shown in Figure 5a, the electrode substrate is made of a single crystal silicon substrate of 100 directions with good etching using a MEMS process, the silicon substrate cleans the surface to improve the adhesion and coating performance.

Next, an oxide film is deposited on the upper surface of the silicon substrate by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

The oxide film deposition is preferably performed by an atmospheric pressure CVD apparatus.

As shown in FIG. 5B, the photoresist is applied on the silicon substrate by using a spin coater.

As shown in FIG. 5C, a SiO 2 mask or a photoresist mask is prepared for drilling vertical through holes on the upper surface of the silicon substrate, and is prebaked and developed with a through mask prepared to evaporate the solvent of the photoresist-coated silicon substrate. Is to pattern the holes.

As shown in FIG. 5D, a dry etching process is performed on the upper surface of the silicon substrate to process a plurality of deep vertical through holes at narrow pitch intervals. Etching may be used by an anisotropic dry etching technique such as a bosch process using inductivity coupled plasma (ICP).

Anisotropic dry etching such as the bosch process is dry etching while maintaining verticality by repeating etching with SF6 gas and sidewall protection process with C4F8 gas.

As shown in Fig. 5E, the oxide film and the remaining photoresist are removed. When the SiO 2 mask is used as the photoresist mask, the SiO 2 photoresist mask is removed by ashing.

As shown in FIG. 5F, an oxide film is deposited on a lower surface of the silicon substrate by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

As shown in Fig. 5G, the photoresist is uniformly and evenly applied to the lower surface of the silicon substrate using a spin coater device.

As shown in FIG. 5H, a SiO 2 mask or a photoresist mask for digging a horizontal groove on the bottom surface of the silicon substrate is prepared, and the photoresist is exposed and developed with a horizontal groove mask prepared and prebaked to evaporate the solvent of the photoresist coated silicon substrate. Pattern.

Since the SiO 2 mask has the same selectivity as that of the silicon substrate, it is advantageous to form deep holes and grooves.

As shown in Figure 5i, by performing a dry etching process on the lower surface of the silicon substrate to process a plurality of horizontal grooves at a narrow pitch interval. Etching may use an anisotropic dry etching technique such as a bosch process using inductivity coupled plasma (ICP). The bosch process is dry etching while maintaining verticality by repeating etching with SF6 gas and sidewall protection process with C4F8 gas.

As shown in Fig. 5J, the oxide film and the remaining photoresist are removed. When the SiO 2 mask is used as the photoresist mask, the SiO 2 photoresist mask is removed by ashing.

As shown in Fig. 5k, an insulating film is formed in the vertical grooves and the horizontal grooves in front of the silicon substrate.

Then, the via bottom SiO 2 is removed by etching to expose the metal surface of the via bottom.

As shown in FIG. 5L, a barrier film and a seed film are formed in the vertical through hole and the horizontal groove. As the barrier film, Ti / Au, titanium nitride, and the seed film are preferably Cu.

The seed film is required as a Cu seed layer for supplying electrons for reducing Cu ions when electroplating is used to embed conductive electrode materials in vertical through holes and horizontal grooves.

As shown in Fig. 5M, plating is carried out by filling and filling the conductive cathode material Cu in the vertical through hole and the horizontal groove by electroplating.

As shown in Fig. 5N, Cu embedded in the vertical through hole and the horizontal groove is polished. Polishing is preferably carried out by a chemical machining (CMP) process.

5A through 5N, a plurality of silicon substrates are processed.

As shown in Fig. 5O, two silicon substrates having vertical through holes and horizontal grooves formed therein and filled with electrode material are aligned so that the horizontal grooves and the vertical through grooves form a wiring pattern, and the silicon electrode substrates are bonded with a special adhesive.

In this way, a plurality of silicon electrode substrates are joined to a desired thickness to form embedded vertical through wiring patterns and horizontal recess wiring patterns.

In a method of forming a negative electrode pad of a silicon electrode substrate, photoresist is applied to a silicon substrate on which upper and lower conducting electrodes are formed in which vertical through holes are embedded.

Patterning is performed with a shape mask in which vertical through holes are formed.

The vertical through hole mask is preferably rectangular or circular.

Next, the insulating material is deposited except for the portion of the conducting electrode in which the vertical through-holes are embedded. Then, the photoresist is removed and washed. In this way, except for the portion of the conducting electrode in which the vertical through-holes are embedded, the insulating material may be applied to a predetermined thickness to engrav the vertical through-holes. The engraved pad shape is formed in a square or a circle.

Alternatively, the intaglio pad forming method of the silicon electrode substrate accommodated in the connection block is filled with the polymer elastomer or the silicon louver except for the portion where the conductive electrode material is embedded in the vertical through holes formed on the upper and lower surfaces of the silicon electrode substrate. The polymer elastomer or silicon louver filled as described above is engraved to protrude to the outside and is engraved with the vertical through hole embedded therein, and the silicon electrode substrate is elastically supported so that it is not broken.

The conductive electrode material is to select one of Cu, Au, Ni, Ag, Al.

The engraved pad formed on the silicon electrode substrate prevents the probe pin or the connecting pin from coming off from the protruding embossed pad and stably makes contact.

The silicon electrode substrate having the electrode engraved therein may be cut into blocks or used in a desired size.

According to the above-described manufacturing method, it can be used as a separate probe block by using a contact block and a connection block according to the method of assembling the probe block, and can be used as a test body as an integrated probe block according to the use.

In addition, the probe block is a fast attachment and detachment with a locking and plumbing device.

The locking and plumbing device is provided in the contact block or the connecting block or the stiffener according to the probe block assembly method.

Example 1

As shown in FIG. 2, the probe block 10 has a structure composed of a contact block 15 and a connection block 25.

The contact block 15 is provided with a test body (3) having a probe pin installed on the top, and then consists of a contact block storage box (18) and a silicon electrode substrate (5).

The contact block storage box 18 is made of a metal material on which an insulating film is deposited.

The metal material is preferably selected from novenite and invar.

A fixed end 18a is formed inside the contact block storage box 18 and the silicon electrode substrate 5 is mounted, and the silicon electrode substrate 5 is accommodated in the fixed end 18a.

In addition, the contact portion of the probe pin contacts the wiring pattern negative pad 95 formed on the upper surface of the silicon electrode substrate 5, and the negative electrode pad formed on the lower surface is connected to the electrode of the anisotropic electrode substrate 7 of the connection block with a connecting pin or a pogo pin. It is energized by touching the pad.

Depending on the semiconductor device to be inspected, the semiconductor device changed according to the circuit line width reduced in the same type of memory by replacing the probe electrode test body 3 and the silicon electrode substrate 5 housed in the contact block storage box 18. It can be.

The silicon electrode substrate 5 has a plurality of silicon substrates bonded to each other, and each layer has a wiring pattern added thereto to accommodate the silicon electrode substrate 5 in the contact block storage box 18.

The conduction electrode of the silicon electrode substrate 5 is formed of the intaglio pad 95.

The intaglio pads 95 are formed as the intaglio pads 95 by forming the intaglio recesses when the insulating film 86 is applied except for the conducting electrode portions formed on the upper and lower surfaces of the silicon electrode substrate 5.

The silicon electrode substrate 5 manufactures a silicon substrate by MEMS process.

The method of manufacturing the silicon electrode substrate 5 is as described above.

As shown in FIG. 5A, the silicon substrate is manufactured by using a MEMS process and is made of a single-crystal silicon substrate having a good etchability in a 100 direction, and the silicon substrate cleans the surface to improve adhesion and coating performance.

Next, an oxide film is deposited on the upper surface of the silicon substrate by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

The oxide film deposition is preferably performed by an atmospheric pressure CVD apparatus.

As shown in FIG. 5B, the photoresist is applied on the silicon substrate by using a spin coater.

As shown in FIG. 5C, a SiO 2 mask or a photoresist mask is prepared in order to drill a vertical through hole on the upper surface of the silicon substrate, and is pre-baked and developed with a vertical through mask prepared in advance to evaporate the solvent of the photoresist-coated silicon substrate. Pattern the through holes.

As shown in FIG. 5D, a dry etching process is performed on the upper surface of the silicon substrate to process a plurality of deep vertical through holes at narrow pitch intervals. Etching may use an anisotropic dry etching technique such as a bosch process using inductivity coupled plasma (ICP). The bosch process is dry etching while maintaining the verticality by repeating the etching process by SF6 gas and the sidewall protection process by C4F8 gas.

As shown in Fig. 5E, the oxide film formed on the upper surface of the silicon substrate and the remaining photoresist are removed. When the SiO 2 mask is used as the photoresist mask, the SiO 2 photoresist mask is removed by ashing.

As shown in FIG. 5F, an oxide film is deposited on the bottom surface of the silicon substrate by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

As shown in FIG. 5G, the photoresist is uniformly and evenly coated on the bottom surface of the silicon substrate using a spin coater device.

As shown in FIG. 5H, a SiO 2 mask or a photoresist mask is prepared to dig a horizontal recess on the bottom surface of the silicon substrate, and the photoresist is prebaked and developed with a horizontal recess mask prepared to evaporate the solvent of the silicon substrate to which the photoresist is applied, thereby horizontally Pattern the grooves.

Since the SiO 2 mask has the same selectivity as that of the silicon substrate, it is advantageous to form vertical through holes and horizontal grooves.

As shown in FIG. 5I, a dry etching process is performed on the bottom surface of the silicon substrate to process a plurality of horizontal grooves at narrow pitch intervals. Etching may use an anisotropic dry etching technique such as a bosch process using inductivity coupled plasma (ICP). The bosch process is dry etching while maintaining verticality by repeating etching with SF6 gas and sidewall protection process with C4F8 gas.

When the SiO 2 mask is used as the photoresist mask, the SiO 2 photoresist mask is removed by ashing.

As shown in Fig. 5J, the oxide film formed on the lower surface of the silicon substrate and the remaining photoresist are removed. When the SiO 2 mask is used as the photoresist mask, the SiO 2 photoresist mask is removed by ashing.

As shown in FIG. 5K, an insulating film is formed in the hole and the horizontal groove vertically penetrated with the front surface of the silicon substrate.

Then, the via bottom SiO 2 is removed by etching to expose the metal surface of the via bottom.

As shown in FIG. 5L, a barrier film and a seed film are formed in the vertical through hole and the horizontal groove.

Ti / Au is used as the barrier film, and Cu is used as the seed film.

The seed film is required as a Cu seed layer for supplying electrons for reducing Cu ions when electroplating is used to embed conductive electrode materials in vertical through holes and horizontal grooves.

As shown in FIG. 5M, electroplating is carried out by filling and filling the conductive electrode material in the vertical through hole and the horizontal groove by electroplating.

The conductive electrode material is to select one of Cu, Au, Ni, Ag, Al.

As shown in Fig. 5N, the conductive electrode material overfilled in the vertical through-hole and the horizontal groove is polished and planarized.

The polishing is preferably carried out by a chemical machining (CMP) process.

5a to 5n, after the process of manufacturing a plurality of silicon substrates,

As shown in FIG. 5O, two silicon electrode substrates having vertical through holes and horizontal grooves formed therein and filled with a conductive electrode material are aligned so that the horizontal grooves and the vertical through grooves form a wiring pattern, and the silicon electrode substrate is bonded with an adhesive.

In this way, a plurality of silicon electrode substrates are bonded to each other at a desired thickness to form a vertical through wiring pattern and a horizontal recess wiring pattern.

Next, the insulating material 86 is applied except for the portion of the conducting electrode where the vertical through hole is embedded.

In addition, the insulating material 86 coated except for the conductive electrode portion in which the conductive electrode material is embedded in the vertical through hole 90 has a predetermined thickness so that the vertical through hole 90 is formed with the intaglio pad 95. .

The engraved pad 95 is formed in a square or circular shape.

The conductive electrode contact pads are engraved when the connecting pins of the bottom surface of the silicon electrode substrate 5 housed in the contact block 15 come into contact with the electrode pads of the anisotropic electrode substrate 7 housed in the connection block 25. To prevent.

The conductive electrode is used by cutting the silicon electrode substrate 5 having the engraved pad 95 into blocks, or by cutting to a desired size.

The silicon electrode substrate 5 housed in the contact block is electrically connected to the pad pin of the printed circuit board 100 by contacting the bottom connection pins with the electrode pads of the anisotropic electrode substrate 7 of the connection block 25.

The intaglio pads 95 of the silicon electrode substrate 5 are arranged in a zigzag arrangement to reduce the number of silicon substrates stacked by arranging the intaglio pads 95 as large as possible.

The connection block 25 has a structure in which the connection block storage box 28 and the anisotropic electrode substrate 7 are provided.

Both ends of the probe block 10 constituted by the contact block 15 and the connection block 25 are formed with a locking and plumbing device.

The locking and the plumbing device is formed in the ejector (1) structure to quickly detachable. The ejector 1 is formed at both ends of the connection block storage box 28, and the ejector 1 is fixed to the ejector holder 1a at both ends of the contact block storage box 18 by locking. The ejector 1 formed in the connection block storage box 28 is provided with a handle and a locker for locking and plumbing, and the ejector holder 1a formed in the contact block storage box 18 becomes a locking piece so that the contact block 15 is provided. Detachable from this connection block (25).

Since the connection block 25 is standardized and fixed, the probe card of the memory semiconductor of the same storage capacity type can be reused by replacing only the contact block 15 and the printed circuit board 100 and the apparatus attached thereto.

As such, the cost of reusable printed circuit boards and fixtures is eliminated, resulting in faster inspection and delivery costs and reduced inspection costs by using a reasonable probe card.

Probe block 10 is formed in the longitudinal direction with a predetermined interval opening hole, the first opening hole is a hollow opening hole, the next opening hole is fastened with a fastening bolt (not shown) by a fastening method (not shown). It is preferable to form the space | interval of an opening hole at equal intervals.

The openings in the probe block 10 are formed in the same line as the opening holes in the printed circuit board (not shown).

The fastening bolt can adjust the probe block Z-axis flatness according to the degree of locking.

In addition, both ends of the contact block 15 and both ends of the connection block 25 are provided with adjusting bolts 99 so that the silicon electrode substrate 5 contained in the contact block 15 and the anisotropic electrode received in the connection block 25 are provided. By adjusting the position of the substrate 7 it is possible to adjust the left and right fine pitch of the X-axis.

The connection block storage box 28 is preferably manufactured by selecting one of machineable ceramic and engineering plastics.

The probe pin is used by the present applicant in the structure and shape of the application and the description is omitted in the present application.

Example 2

As shown in FIG. 3, the probe block 30 is divided into a contact block 35 and a connection block 45. The multilayer ceramic circuit board 9 (MLC) stored in the contact block 35 is blocked and used in the contact block storage box 18 to be used as the contact block 35, and the probe pin is disposed in the test body 3. The test body 3 is energized by contacting the conduction electrode of the bottom surface of the multilayer ceramic circuit board 9 with a connection pin or pogo pin and contacting the conduction electrode formed on the silicon electrode substrate 5 of the connection block 45. .

The multilayer ceramic circuit board 9 is formed into a plurality of layers, and each layer is housed in the contact block storage box 18 in a structure of a built-in wiring pattern.

The connection block 45 has a storage box inside and accommodates the silicon electrode substrate 5 in the connection block storage box 28.

A fixed end 28a is formed in the connection block storage box 28 to open the silicon electrode substrate, and the silicon electrode substrate 5 is accommodated in the fixed end 28a.

The insulating film 87 drilled into the vertical through hole 90 of the silicon electrode substrate 5 is attached to the upper and lower surfaces of the silicon electrode substrate 5 except for the conducting electrode portion having the vertical through hole 90 embedded therein. The conductive electrode can be engraved pad 95.

The intaglio pads 95 on the upper surface of the silicon electrode substrate 5 are arranged in a zigzag arrangement to reduce the number of silicon substrate stacks by arranging the intaglio pads 95 as large as possible.

Probe block 30 is composed of a contact block 35 and the connecting block 45 is a lock and a plumbing device is formed at both ends. The locking and the plumbing device is formed in the ejector 1 structure to quickly detachable.

The ejector 1 is formed at both ends of the contact block storage box 18 to fasten the ejector 1 to the ejector holder 1b at both ends of the connection block storage box 28 by locking. The ejector 1 formed in the contact block storage box 18 is provided with a handle and a locker for locking and plumbing, and the ejector holder 1b formed in the connection block storage box 28 becomes a locking piece so that the contact block 35 is provided. Detachable from this connection block (45).

In addition, the multilayer ceramic circuit board 9 housed in the contact block 35 and the silicon electrode substrate 5 housed in the connection block 45 are provided with adjusting bolts at both ends of the contact block 35 and at both ends of the connection block 45. 99) is added to adjust the left and right fine pitch of the X-axis by positioning the multilayer ceramic circuit board 9 and the silicon electrode substrate (5).

Since the connection block 45 is standardized and fixed, the probe card of the memory semiconductor of the same type of storage capacity can be reused by replacing only the contact block 35 and the printed circuit board 100 and the apparatus attached thereto.

Example 3

As shown in FIG. 4, the probe block 50 is divided into a contact block 55 and a connection block 65. The contact block 55 is composed of an anisotropic electrode substrate (7) and a contact block storage box 18, the test body 3 having a probe pin disposed on the top.

An opening is formed inside the contact block storage box 18 so that a probe pin joint provided in the test body 3 is inserted into an opening of the test specimen alignment substrate so that the probe pin joint contacts the conducting electrode of the anisotropic electrode substrate 7 to conduct electricity. Will be.

The silicon electrode substrate 5 accommodated in the connection block 65 has a silicon substrate composed of a plurality of layers bonded to each other, and each layer has a structure of a wiring pattern to store the silicon electrode substrate 5 in the connection block storage box 28. To be mounted.

The intaglio pad forming method of the silicon electrode substrate 5 accommodated in the connection block 65 may include a polymer elastomer 89 or a silicon louver except for a portion in which the vertical through-holes of the upper and lower surfaces of the silicon electrode substrate 5 are embedded. Fill. The polymer elastomer 89 or silicon louver thus filled protrudes to the outside to engrav the portion where the vertical through hole 90 is embedded, and does not break due to the elastic support of the silicon electrode substrate 5.

In the silicon electrode substrate 5 accommodated in the connection block 65, the contact pins contact the intaglio pads 95 so that the contact pins are provided on the intaglio pads 95 disposed on the bottom surface of the silicon electrode substrate 5 through a wiring pattern. The pad is formed on the printed circuit board 100 to be energized by bonding.

The intaglio pads 95 of the silicon electrode substrate 5 may be arranged in a zigzag arrangement so that the intaglio pads 95 are disposed as large and large as possible, thereby reducing the number of silicon substrate stacks.

The intaglio pad 95 disposed on the bottom surface of the silicon electrode substrate 5 accommodated in the connection block 65 prevents the connecting pin, which is electrically connected to the printed circuit board 100, from contacting the intaglio pad 95 to prevent separation. The poor contact between the printed circuit board 100 and the connection block 65 can be reduced.

Probe block 50 is composed of a contact block 55 and the connecting block 65 is a locking and plumbing device is formed on both ends of the upper stiffener (110). The locking and plumbing device provided in the upper stiffener 110 is formed in the ejector 2a structure to quickly detach the probe block 50 from the upper stiffener 110.

The ejector 2a is formed at both ends of the upper stiffener 110, and is fastened by being fixed to the ejector holders 2 at both ends of the contact block storage box 18 by locking. The ejector (2a) formed in the upper stiffener 110 is provided with a handle and a locker (Locker) for locking and plume, the ejector holder (2) formed in the contact block storage box (18) is a locking piece is a contact block ( 35) is detachable from the upper stiffener (110).

The present invention is not limited to the above-described embodiments, and various modifications may be made by those skilled in the art within the spirit and scope of the present invention.

1A, 1B, and 1C are perspective views illustrating a conventional probe block.

Figure 2 is a perspective view illustrating a configuration state that the ejector of the present invention is provided in the connection block storage box.

Figure 3 is a perspective view illustrating a configuration state that the ejector of the present invention is provided in the contact block storage box.

Figure 4 is a perspective view illustrating a configuration state that the ejector of the present invention is provided in the upper stiffener.

5A to 5O are process drawings illustrating a method of manufacturing a silicon electrode substrate.

Description of the Related Art

1: ejector 3: inspector 5: silicon electrode substrate 7: anisotropic electrode substrate

9: Multilayer ceramic circuit board 10, 30, 50: Probe block 15, 35, 55: Contact block

18: Contact block box 25, 45, 65: Connection block 28: Connection block box

86: insulating film 87: insulating film 89: polymer elastomer

90: vertical through hole 93: horizontal groove 95: intaglio pad

99: adjusting bolt 100: printed circuit board 110: upper stiffener 120: probe block housing

Claims (2)

Silicon electrode substrate (5) manufacturing method A step of depositing an oxide film on the upper surface of the silicon substrate by chemical vapor deposition (CVD) or physical vapor deposition (PVD); B) applying a photoresist to an upper surface of the silicon substrate on which the oxide film is deposited; C) patterning a vertical through hole with a vertical through mask on the photoresist applied on the silicon substrate; A step d for processing the vertical through hole at the anisotropic dry time on the silicon substrate patterned with the vertical through hole; Removing the photoresist and the oxide film remaining on the upper surface of the silicon substrate; Depositing an oxide film on the bottom surface of the silicon substrate by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process; G step of applying a photoresist on the bottom surface of the silicon substrate on which the oxide film is deposited; Patterning the horizontal grooves with a horizontal groove mask on the photoresist applied on the bottom surface of the silicon substrate; I-processing the horizontal grooves by anisotropic dry etching on the bottom surface of the silicon substrate on which the horizontal grooves are patterned; Removing the photoresist and the oxide film remaining on the lower surface of the silicon substrate; K step of depositing an insulating film on the front surface of the silicon substrate, the vertical through hole and the horizontal groove; Removing the SiO 2 at the bottom of the via hole in which the insulating film is deposited, exposing the metal layer at the bottom of the via, and depositing a barrier film and a seed film in the vertical through hole and horizontal groove where the insulating film is deposited; M step of electroplating a conductive electrode material with filling filling into the vertical through hole and the horizontal groove in which the barrier film and the seed film are deposited; N step of flattening the conductive electrode material plated with overfill filling the vertical through hole and the horizontal groove by chemical mechanical processing (CMP); And O-joining the conductive cathode material by matching the vertical through-holes of the plurality of silicon substrates having the planarization process with the horizontal grooves; Method for producing a silicon electrode substrate of the probe block, characterized in that it is produced, including. The method of claim 1, The method of claim m, wherein the conductive electrode material is manufactured by selecting one of Cu, Au, Ni, Ag, Al.

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