KR20100123056A - Light emitting diode display device and method for driving the same - Google Patents

Abstract

PURPOSE: The fault according to the luminescent display device and manufacturing method thereof lice static electricity is prevented. In that way the fabrication Yield of the luminescence display panels is improved. CONSTITUTION: In order to the lower part and upper plate include the image display region and non-display area and it is each other opposite it is attached. A plurality of cell driving parts is formed in the non-emitting area of the image display region. A plurality of light emitting cells is formed in the light emission region of the image display region. The first electrode(19), and the organic light-emitting layer(21) and the second electrode(22) form one light emitting cell.

Description

LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device. In particular, a manufacturing yield of light emitting display panels is prevented by preventing defects caused by static electricity frequently generated during a scribing process or a cutting process during a manufacturing process of the light emitting display panel. The present invention relates to a light emitting display device and a method of manufacturing the same.

Recently, a lightweight thin flat panel display is mainly used as a video display device used for a personal computer, a portable terminal, a monitor of various information apparatuses, and the like. Such flat panel displays include liquid crystal displays, light emitting displays, plasma display panels, field emission displays, and the like.

Among them, a light emitting display device uses a self-luminous display panel that emits light of its own, thereby resulting in high contrast ratio, ultra-thin display, and a response time of several microseconds. It is easy.

Recently, research on active matrix organic light emitting diode (AMOLED) panels, which are self-luminous display panels, has been actively conducted. The AMOLED panel is composed of three color (R, G, B) sub-pixels on one substrate. A plurality of pixels are arranged in a matrix form, and another substrate is formed by encapsulating a substrate including the sub pixels. Here, each of the sub-pixels includes an organic electroluminescent cell and a cell driver for driving the light emitting cells independently. In addition, recently, studies on dual panel type AMOLED panels, in which light emitting cells and cell drivers are formed on different substrates and then coupled to face each other, have been actively conducted.

The light emitting display panels may be formed by depositing a conductive metal layer or an insulating layer, patterning the metal layer or the insulating layer, bonding the at least one substrate, or scribing or cutting the bonded substrates by size. It is commercialized through the process. Here, the scribing process or the cutting process is performed in the case of separating the dummy circuits formed in each of the light emitting display panels in order to test the light emitting display panels in addition to the case of cutting the substrates by size.

However, in the process of scribing or cutting the light emitting display panel, since the friction between the scribing device and the cutting devices and the light emitting display panel is severe, static electricity is frequently generated, thereby increasing the defective rate of the light emitting display panels. In other words, when static electricity is generated largely and frequently, overcurrents frequently damage sub-pixels of the light emitting display panels, thereby increasing the defective rate of the light emitting display panels. In this case, there is a problem that the manufacturing process yield of the light emitting display panels is also lowered.

The present invention is to solve the above problems, to improve the manufacturing yield of the light emitting display panel by preventing the defect caused by the static electricity frequently generated in the scribing process or the cutting process during the manufacturing process of the light emitting display panel It is an object of the present invention to provide a light emitting display device and a method of manufacturing the same.

A light emitting display device according to an embodiment of the present invention for achieving the above object includes a lower and upper substrate bonded to face each other and including an image display area and a non-display area; A plurality of cell drivers formed in the non-emission area of the image display area; A plurality of light emitting cells formed in the light emitting area of the image display area; And at least one antistatic pattern formed on at least one of the upper and lower substrates along the substrate cutting line to overlap the substrate cutting lines formed in the non-display areas of the lower and upper substrates. .

The at least one antistatic pattern is a pattern formed integrally with the antistatic pattern portions formed in the dummy regions of the lower and upper substrates, and the antistatic pattern portion is cut when the dummy regions are removed to form an upper portion of the non-display region. And a pattern remaining on at least one of the lower substrates.

The antistatic pattern portion may be formed on a portion or the entire area of the non-display area and the dummy area, and the lower antistatic pattern may be formed of at least one conductive metal material on the lower substrate of the non-display area and the dummy area. The upper substrate is formed in the non-display area and the dummy area of the upper substrate so as to cover at least one protrusion integrally formed with the upper substrate and the at least one protrusion, and the at least one when the upper substrate and the lower substrate are bonded together. It characterized in that it comprises an upper antistatic pattern electrically connected to the lower antistatic pattern by the projection of.

The lower antistatic pattern may be formed through the same process for forming the gate electrode or the source / drain electrode of the cell driver or through the same process for forming the first or second electrode of the light emitting cell. The antistatic pattern may be separately formed on the upper substrate or may be formed through the same process when forming the first or second electrode of the light emitting cell.

The at least one protrusion is formed integrally with the upper substrate in the dummy region of the upper substrate or through the same process as the structure of at least one of the buffer layer, the contact spacer and the separator when the plurality of light emitting cells and the cell driver are formed. It is characterized by.

In addition, a method of manufacturing a light emitting display device according to an embodiment of the present invention for achieving the above object comprises the steps of preparing an upper and a lower substrate; Forming a plurality of cell drivers in the image display area of the lower substrate; Forming a plurality of light emitting cells in an image display area of the upper or lower substrate; Forming at least one antistatic pattern on at least one of the upper and lower substrates along the substrate cutting line to overlap the substrate cutting lines formed in the non-display areas of the upper and lower substrates; And bonding the upper and lower substrates together.

The forming of the at least one antistatic pattern may include forming an antistatic pattern portion in the upper and lower substrate dummy regions, and cutting and removing the upper and lower substrate dummy regions. The antistatic pattern portion formed in the dummy region may be cut and left on at least one of the upper and lower substrates of the non-display region.

The forming of the antistatic pattern portion may include forming a lower antistatic pattern with at least one conductive metal material on the non-display area and the dummy area of the lower substrate and integrally with the upper substrate on the upper substrate of the dummy area. An upper antistatic pattern is formed on the upper substrate to cover all of the at least one protrusion formed and to be electrically connected to the lower antistatic pattern by the at least one protrusion when the upper substrate and the lower substrate are bonded together. Characterized in that it comprises a step.

The lower antistatic pattern may be formed through the same process for forming the gate electrode or the source / drain electrode of the cell driver or through the same process for forming the first or second electrode of the light emitting cell. The antistatic pattern may be separately formed on the upper substrate or may be formed through the same process when forming the first or second electrode of the light emitting cell.

The at least one protrusion may be formed integrally with the upper substrate in the dummy region of the upper substrate or may be formed through the same process as at least one structure of a buffer layer, a contact spacer and a separator when the plurality of cell drivers are formed. do.

A light emitting display device and a method of manufacturing the same according to an embodiment of the present invention having the above characteristics by preventing the failure caused by the static electricity frequently generated in the scribing process or the cutting process during the manufacturing process of the light emitting display panel, It is possible to improve the manufacturing process yield of the panels.

Hereinafter, a light emitting display device and a method of manufacturing the same according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention. 2 is an equivalent circuit diagram illustrating one sub-pixel of the display panel illustrated in FIG. 1.

1 includes a display panel 1 formed with a plurality of pixel regions, a gate driver 2 driving the gate lines GL1 to GLn of the display panel 1, and a display panel 1. A data driver 3 for driving the data lines DL1 to DLm of the power supply unit and a power supply unit for applying the first and second power signals VDD and GND to the power lines PLn to PLm of the display panel 1. 4) and RGB data (RGB) input from the outside are aligned to the size and resolution of the display panel 1 and supplied to the data driver 3, and the data and gate control signals DVS and GVS are generated. And a timing controller 5 for controlling the data and gate drivers 3 and 2.

In the display panel 1, a plurality of sub-pixels P are arranged in a matrix form in each pixel area to display an image. Each of the sub-pixels P drives a light emitting cell and a cell driver for driving the light emitting cells independently. It is provided. Specifically, as shown in FIG. 2, one sub-pixel P includes a cell driver DRV and a cell driver DRV connected to any one of the gate line GL, the data line DL, and the power supply line PL. ) And a second power supply signal GND, the light emitting cell OEL equivalently represented by a diode.

The cell driver DRV is disposed between the first switching element T1, the first switching element T1, the power line PL, and the light emitting cell OEL connected to any one of the gate line GL and the data line DL. A second switching element T2 connected to the power supply line PL and a storage capacitor C connected between the power supply line PL and the first switching element T1 are provided.

The gate electrode of the first switching element T1 is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the gate electrode of the second switching element T2. When the gate-on signal is supplied to the gate line GL, the first switching element T1 turns on and supplies the data signal supplied to the data line DL to the storage capacitor C and the second switching element T2. It is supplied to the gate electrode of.

The source electrode of the second switching element T2 is connected to the power supply line PL and the drain electrode is connected to the light emitting cell OEL. The second switching element T2 controls the amount of light emitted from the light emitting cell OLE by controlling the current I supplied from the power supply line PL to the light emitting cell OEL in response to a data signal from the first switching element. Will be adjusted.

The storage capacitor C is connected between the power supply line PL and the gate electrode of the second switching element T2. The second switching element T2 remains on by the voltage charged in the storage capacitor C even when the first switching element T1 is turned off, until the data signal of the next frame is supplied. The emission of (OEL) is maintained. Here, the first and second switching elements T1 and T2 may use PMOS or NMOS transistors, but the above description has been made only when NMOS transistors are used.

The gate driver 2 of FIG. 1 responds to a gate control signal GVS from the timing controller 5, for example, a gate start pulse GSP and a gate shift clock GSC. The gate on signal is sequentially generated and the pulse width of the gate on signal is controlled according to a gate output enable (GOE) signal. The gate-on signals are sequentially supplied to the gate lines GL1 to GLn. Here, the gate off voltage is supplied to the gate lines GL1 to GLn during the period when the gate on voltage is not supplied.

The data driver 3 uses the source start pulse SSP, the source shift clock SSC, and the like among the data control signals DVS from the timing controller 5. The expanded RGB data (MData) input from the digital signal is converted into an analog voltage, that is, an analog video signal. The video signal is supplied to each of the data lines DL1 to DLm in response to a source output enable (SOE) signal. Specifically, the data driver 3 latches the extended RGB data MData input according to the SSC, and then horizontally one horizontal cycle in which scan pulses are supplied to the gate lines GL1 to GLn in response to the SOE signal. The video signal for the line is supplied to each of the data lines DL1 to DLm.

The power supply unit 4 supplies the first power signal VDD and the second power signal GND to the display panel 1. Here, the first power signal VDD means a driving voltage for driving the light emitting cell OEL, and the second power signal GND may mean a ground voltage or a low voltage. Due to the difference between the first power signal VDD and the second power signal GND, a current corresponding to an image signal may also flow in each sub-pixel P. FIG.

The timing controller 5 aligns the RGB data RGB input from the outside according to the size and resolution of the display panel 1 and supplies the aligned image data Data to the data driver 3. In addition, the timing controller 5 generates the gate and data control signals GVS and DVS using the synchronization signals MCLK, DE, Hsync, and Vsync input from the outside, and generates the gate driver 2 and the data driver ( Supply to 3).

3 is a circuit diagram illustrating a manufacturing process of the display panel illustrated in FIG. 1.

As shown in FIG. 3, the display panel 1 of the present invention includes a display area 1a in which an image is displayed and a non-display area 1b in which an image is not displayed. In the manufacturing process of the display panel 1, at least one dummy region DU1 and DU2 may be integrally formed in the display panel 1, and the display panel 1 may be formed in each dummy region DU1 and DU2. Dummy circuits for inspecting and testing are formed. Accordingly, the dummy regions DU1 and DU2 are removed from the scribing process and the cutting process in the display panel 1 that have undergone a predetermined inspection and test process. Here, the arrows A and A 'shown in FIG. 3 indicate scribing directions for separating the first dummy region DU1, respectively, and the arrows B and B' indicate slicing directions for separating the second dummy region DU2. The creeping direction is shown respectively. After the dummy regions DU1 and DU2 are cut, the display panel 1 is used as a light emitting display panel as shown in FIG. 1.

As described above, when cutting at least one dummy area DU1 and DU2 in the display panel 1, each sub-pixel P of the display area 1a may be caused by friction with a scribing device or cutting devices. ) May be supplied with overcurrents due to static electricity. In this case, since the defect of the display panel 1 may occur, the display panel 1 of the present invention further includes antistatic patterns for distributing static electricity generated during the scribing process or the cutting process to the outside.

In detail, the display panel 1 including the display area 1a and the non-display area 1b of the image includes lower and upper substrates facing each other, and among the upper and lower substrates of the non-display area 1b. At least one antistatic pattern is formed on the at least one substrate along the cutting points to overlap the cutting line, which is the cutting point of each substrate. The antistatic pattern is a pattern that is integrally formed with the antistatic pattern portion formed in the dummy region DU1 DU2, and the antistatic pattern portion is cut when the dummy regions DU1 DU2 are cut to display the non-display region 1b. The pattern remains on at least one of the upper and lower substrates of the substrate. Such an antistatic pattern of the present invention will be described in more detail with reference to FIGS. 4 to 6C.

4 is a cross-sectional view illustrating a region II ′ shown in FIG. 3.

As shown in FIG. 4, in the display panel 1 of the present invention during the manufacturing process, the cell driver DRV and the light emitting cells OEL are formed in the display area 1a, and the non-display area 1b is provided. The antistatic pattern portion is formed in the dummy regions DU1 and DU2.

Here, both the cell driver DRV and the light emitting cells OEL may be formed on the lower substrate 10. In this case, the cell driver DRV and the light emitting cells OEL may be encapsulated on the lower substrate 10. An encapsulation substrate, that is, an upper substrate EC, is further formed. The lower substrate 10 is bonded to each other by the upper substrate EC and the sealant SL, and the sealant SL is an outer portion of the upper and lower substrate EC 10, that is, the non-display area 1b. Is formed.

The antistatic pattern portion formed over the non-display area 1b and the dummy areas DU1 and DU2 includes at least one conductive metal material on the lower substrate 10 of the non-display area 1b and the dummy areas DU1 and DU2. The lower antistatic pattern 27a formed on the upper substrate EC of the dummy regions DU1 and DU2, at least one protrusion L integrally formed with the upper substrate EC, and the at least one protrusion L. ) Are formed in the non-display area 1b and the dummy areas DU1 and DU2 of the upper substrate EC so that the at least one protrusion is formed when the upper substrate EC and the lower substrate 10 are bonded together. And an upper antistatic pattern 27b electrically connected to the lower antistatic pattern 27a by (L). Here, an insulating pattern 28 may be further formed on a portion of the lower antistatic pattern 27a that is not electrically connected to the upper antistatic pattern 27b.

As described above, dummy circuits for inspecting and testing the display panel 1 are formed in the dummy regions DU1 and DU2 of the display panel 1 in addition to the antistatic pattern. Therefore, after the inspection and testing of the display panel 1, the dummy regions DU1 and DU2 are removed through a scribing process and a cutting process. As described above, the A and A 'arrow points are the points where scribing and cutting are made.

On the other hand, the plurality of switching elements formed on the lower substrate 10 of the display area 1a may have a bottom gate structure using amorphous silicon (a-Si), and although not shown, the respective switching The device may have a top gate structure using polysilicon. Here, the structure of the lower substrate 10 of the display area 1a will be described in more detail as follows.

In the lower substrate 10 of the display area 1a, the gate insulating layer 12 formed on the entire surface of the lower substrate 10 including the gate electrode 11 and the gate electrode 11 formed in the non-light emitting region of the lower substrate 10. ), The semiconductor layer 13 formed on the gate insulating layer 12 to overlap the gate electrode 11, the ohmic contact layer 14 and the ohmic contact layer 14 formed to overlap both edges of the semiconductor layer 13. And a passivation layer 17 formed on the entire surface of the lower substrate 10 including the source / drain electrodes 15 and 16. Here, the gate electrode 11, the source / drain electrodes 15 and 16, the semiconductor layer 13, the ohmic contact layer 14, the gate insulating film 12, and the protective film 17 form one switching element. .

In addition, a contact hole 18 penetrating the passivation layer 17 is formed in each passivation layer in the passivation layer 17 to expose a portion of the drain electrode 16, and the first electrode 19 is formed in each contact hole 18. Is formed and is in electrical contact with the drain electrode. In addition, the lower substrate 10 includes a pixel defining layer 23 formed in the non-emission region of the lower substrate 10 including the contact hole 18 and an organic emission layer 21 formed on the surface of the first electrode 19 of the emission region. ), A second electrode 22 formed on the entire surface of the lower substrate 10 including the organic emission layer 21 is further formed. The first electrode 19, the organic emission layer 21, and the second electrode 22 form one light emitting cell OEL. Here, the lower antistatic pattern 27a and the insulating pattern 28 constituting the antistatic pattern portion may be formed together with the switching element through the same process during the formation of the switching elements, while the light emitting cell OEL is formed. It may be formed together with the light emitting cell OEL through the same process.

In other words, if the lower antistatic pattern 27a and the insulating pattern 28 are formed together when the switching elements are formed, the lower antistatic pattern 27a may be the gate electrode 11 or the source / drain electrode 15 of the switching element. 16 may be formed on the lower substrate 10 of the non-display area 1b and the dummy areas DU1 and DU2 through the same material and process. In this case, the insulating pattern 28 may be formed of the same material through the same process when forming the protective film 17.

If the lower antistatic pattern 27a and the insulating pattern 28 are formed together at the time of forming the light emitting cell OEL, the lower antistatic pattern 27a is formed on the first electrode of the light emitting cell OEL. 19 or the second electrode 22 may be formed on the lower substrate 10 of the non-display area 1b and the dummy areas DU1 and DU2 through the same process using the same material. In this case, the insulating pattern 28 may be formed of the same material through the same process when the pixel defining layer 23 is formed.

An upper antistatic pattern 27b is separately formed in the non-display area 1b and the dummy areas DU1 and DU2 of the upper substrate EC on which the at least one protrusion L is formed. Here, the at least one protrusion L may be integrally formed with the upper substrate EC in a molding production process of the upper substrate EC. Each of the lower and upper antistatic patterns 27a and 27b may have a front surface of the non-display area 1b and the dummy areas DU1 and DU2 of the upper and lower substrates EC and 10 including the protrusions L, respectively. It may be formed on all, or may be formed only in some areas including the respective projections (L) and striving and cutting point.

Although not shown in the drawings, a power line PL is formed on the gate insulating layer positioned in the outer non-display area 1b of the lower substrate 10. The power line PL is a line for transmitting a first power signal or a second power signal, and the first power signal or the second power signal applied through the power line PL is the first of each of the light emitting cells OEL. Or it means a power applied to the second electrode (19, 22). The power line PL is formed of the same material as the source / drain electrodes 15 and 16. In other words, the power line PL and the source / drain electrodes 15 and 16 may be simultaneously manufactured through the same mask process. As such, the power line PL is electrically connected to each of the first or second electrodes 19 and 22 of the light emitting cells OEL through a pad electrode, which is not shown. Therefore, in addition to the contact hole 18 connected to the drain electrode 16, the contact layer connected to the power line PL may be further formed in the passivation layer 17.

The first electrode 19 is formed in front of the emission areas including the contact holes 18 of each sub pixel area. The first electrode 19 may be an anode or a cathode and at least one of Induim Tin Oxide (ITO), Indium Zinc Oxide (IZO), and Al-dopped Zinc Oxide (AZO) may be used to achieve lower emission. It may be formed of a transparent conductive material. Here, ITO is a transparent conductive film having a relatively uniform work function and a small hole injection barrier for the organic light emitting layer 21. On the other hand, the first electrode 19 is ITO / Ag, ITO / Ag / ITO, ITO / Ag / IZO (Indium Zinc Oxide), aluminum (Al), and aluminum alloy to achieve upper emission. It may be formed of at least one metal material of (AlNd), copper (Cu), silver (Ag), and a copper alloy.

Since the lower antistatic pattern 27a may be formed at the same time as the first electrode 19, the material for forming the lower antistatic pattern 27a may also be the same as the material for forming the first electrode 19.

The pixel defining layer 23 is formed in the non-light emitting area to increase the aperture ratio of the light emitting area as a partition wall surrounding each sub-pixel, and may be formed to correspond to each position of the switching elements. The pixel defining layer 23 makes the boundary between the light emitting cells OEL located in each light emitting area clearly distinguished so that the light emitting boundary areas between the light emitting areas are clear. The pixel defining layer 23 includes an inclined surface formed obliquely on the first electrode 19. The inclined surface may have an angle formed with the first electrode 19, that is, a taper angle of 10 degrees to 20 degrees. The pixel defining layer 23 may be formed by coating an insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), photo acryl, benzocyclobutene (BCB), and the like. Similarly, since the insulating pattern 28 may also be formed at the same time as the pixel defining layer 23, the insulating pattern 28 forming material may also be the same as the pixel defining layer 23 forming material.

Although not shown in detail in the drawings, the organic light emitting layer 21 includes a hole injection layer HIL, a hole transport layer HTL, a light emitting layer OEL, an electron injection layer EIL, and an electron transport layer ETL. The hole injection layer HIL is formed on the oxide thin film 20 formed on the surface of the first electrode 19, and the hole transport layer HTL is formed on the entire upper surface of the hole injection layer HIL. The emission layer OEL is formed on the hole transport layer HTL of the emission region, and the electron injection layer EIL is formed on the entire upper surface of the emission layer OEL. In addition, the electron transport layer ETL is formed on the upper surface of the electron injection layer EIL.

The second electrode 22 is formed to cover the entire surface of the lower substrate 10 including the pixel defining layer 23 and the organic emission layer 21. The second electrode 22 may be a cathode or an anode, and in order to achieve lower emission, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, It may be formed of at least one material of ITO, ITO / Ag / ITO, ITO / Ag / IZO (Indium Zinc Oxide) and its equivalents. On the other hand, in order to achieve top emission, at least one of ITO, IZO, and AZO may be formed of a transparent conductive material.

5A and 5B are cross-sectional views illustrating a method of manufacturing the display panel illustrated in FIGS. 1 and 3.

A method of manufacturing a display panel according to an exemplary embodiment of the present invention will be described with reference to FIGS. 5A and 5D.

Referring to FIG. 5A, first, a gate metal material is deposited and patterned on a glass substrate used as the lower substrate 10 to form a gate electrode 11. After the gate insulating film 12 is deposited on the entire surface of the lower substrate 10 including the gate electrode 11, the semiconductor layer forming material, the ohmic contact layer forming material, and the source / drain forming material on the gate insulating film 12. Are deposited sequentially.

Thereafter, the semiconductor layer 13 and the ohmic contact layer 14 and the source / drain electrodes 15 and 16 are patterned by simultaneously or sequentially patterning the semiconductor layer forming material, the ohmic contact layer forming material, and the source / drain forming material. To form a switching element.

Next, referring to FIG. 5B, the protective layer 17 is formed on the entire surface of the lower substrate 10 including the switching element and the gate insulating layer 12 and then patterned to expose the drain electrode 16 of the switching element. The contact hole 18 is formed as much as possible.

The ITO, IZO, AZO, or equivalent material, that is, the first electrode 19 forming material is deposited and patterned on the lower substrate 10 by a deposition method such as plasma enhanced chemical vapor deposition (PPECVD) or sputtering. The lower antistatic pattern 27a is formed together with the first electrode 19. Here, the first electrode 19 is in electrical contact with the drain electrode 16 of the switching element through the contact hole 18.

Next, the silicon oxide (PE oxide, spin coating, spinless coating, etc.) on the entire surface of the lower substrate 10 on which the first electrode 19 and the lower antistatic pattern 27a are formed. Insulating materials such as SiOx), silicon nitride (SiNx), photo acryl, and benzocyclobutene (BCB). By patterning this, the pixel defining layer 23 is formed to correspond to the non-emission area in which the switching element is formed, and the insulating pattern 28 is formed together.

Thereafter, the organic light emitting layer 21 is formed on the entire surface of the first electrode 19 of the light emitting region in which the first electrode 19 is formed by using a printing method, a shadow mask method, a thermal transfer method, or the like. . That is, although not shown in detail in the drawings, the organic light emitting layer 21 may be a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (OEL), an electron injection layer (EIL), and an electron transport layer (by a shadow mask method or a thermal transfer method). ETL) is formed by sequentially depositing.

Thereafter, PECVD or sputtering is performed on the entire surface of the lower substrate 10 on which the organic light emitting layer 21 is formed, and among the aluminum (Al), aluminum alloy (AlNd), copper (Cu), and copper alloy having a relatively small work function value, A second electrode 22 having a structure in which silver / calcium (Ag / Ca) or the like is stacked on at least one metal material is formed. The second electrode 22 is formed to cover the entire surface of the organic light emitting layer 21 including the pixel defining layer 23.

Meanwhile, aluminum (Al) having a relatively small work function value is performed by performing PECVD or sputtering on the non-display area 1b and the dummy areas DU1 and DU2 of the upper substrate EC on which the at least one protrusion L is formed. At least one metal material of aluminum alloy (AlNd), copper (Cu), and copper alloy is deposited and patterned to form an upper antistatic pattern 27b.

Thereafter, as shown in FIG. 5C, the sealant SL is formed in the non-display area 1b of the upper or lower substrate 10 (EC), and then the upper substrate is formed by at least one protrusion L. FIG. The non-display area 1b of the EC and the upper antistatic pattern 27b formed in the dummy regions DU1 and DU2 are bonded to the lower antistatic pattern 27a to be electrically connected to each other.

As shown in FIG. 5D, after scribing any one predetermined point of the non-display area 1b, for example, the A and A 'arrow points, the cutting process is performed to perform the dummy area DU1, DU2) is removed.

Accordingly, the upper antistatic pattern 27b and the lower antistatic pattern 27a after the contact remain in some areas of the completed display panel 1 of the present invention, that is, some areas of the non-display area 1b. do.

As described above, when cutting the display panel 1 of the present invention, the static electricity prevention patterns formed in the dummy areas DU1 and DU2 and the non-display area 1b are simultaneously cut so that the static electricity generated during the cutting may be transferred through the antistatic pattern parts. It can be distributed to the outside.

6A and 6C are cross-sectional views illustrating a method of manufacturing a display panel according to another exemplary embodiment of the present invention.

6A and 6C illustrate an example in which an antistatic pattern portion according to the present invention is applied to an AMOLED panel of a dual panel type, for example, a DOD structure, with reference to FIGS. 6A and 6C. Referring to the display panel manufacturing method according to an embodiment of the present invention.

As shown in FIGS. 6A and 6C, the display panel 1 according to another exemplary embodiment includes lower and upper substrates 10 and 30 bonded to face each other, and upper and lower substrates 10 and 30. In the display area 1a, a cell driver DRV is provided to provide light emitting cells OEL and various signals required to operate the light emitting cells OEL. The lower and upper substrates 10 and 30 are bonded to each other by sealants, which are formed in the non-display area 1b of the lower and upper substrates 10 and 30.

Here, the lower substrate 10 according to another embodiment of the present invention is the same as the lower substrate 10 shown in Figures 5a to 5d except for the first electrode 19 and the contact electrode 25 all the same configuration Do. Therefore, the description of the configuration and manufacturing method for the lower substrate 10 will be replaced by the description with reference to FIGS. 5A and 5D. However, the first electrode 19 of FIGS. 5A to 5D is not formed on the lower substrate 10 illustrated in FIGS. 6A to 6C, and instead, the same contact electrode 25 is formed. Here, the lower antistatic pattern 27a and the insulating pattern 28 formed in the dummy regions DU1 and DU2 and the non-display area 1b are also the same as those shown in FIGS. 5A to 5D.

6A to 6C, the structures of the upper substrate 30 and the upper antistatic pattern 27b on which the light emitting cells OEL are formed will be described in detail as follows.

The upper substrate 30 includes an auxiliary electrode 31 formed in the non-light emitting region of the display area 1a, a first electrode 32 formed on the entire lower surface of the upper substrate 30 including the auxiliary electrode 31, and a first electrode. Non-light emitting area of the upper substrate 30 to correspond to the buffer layer 33 formed of an inorganic insulating material in the non-light emitting region of the upper substrate 30 on which the electrode 32 is formed, and the contact electrode 25 of the lower substrate 10. A contact spacer 35 formed in the first electrode 32, a separator 34 formed to correspond to the auxiliary electrode 31, and a first electrode 32 and the separator 34 and the contact spacer 35. ) Are formed on the lower front surface of the upper substrate 30 and the second electrode 38 formed on the lower front surface of the organic light emitting layer 37.

In addition, a plurality of protrusions formed of the same material as the contact spacer 35 or the separator 34 may be formed in any one of the dummy regions DU1 and DU2 of the upper substrate 30 corresponding to the lower antistatic pattern 27a. (L) is formed. In addition, a portion of the dummy areas DU1 and DU2 including the protrusions L and the non-display area 1b may be formed of the same material as the first or second electrodes 34 and 38 on the upper surface of the upper antistatic pattern. 27b) is formed.

The auxiliary electrode 31 of the upper substrate 30 is formed of a low resistance metal material to compensate for the resistance component of the first electrode 31 and apply a more effective voltage. The auxiliary electrode 31 is formed of the upper substrate 30. Is formed in the non-light emitting region. As the low resistance metal material constituting the auxiliary electrode 31, at least one metal material of aluminum (Al), aluminum alloy (AlNd), copper (Cu), silver (Ag), or a copper alloy may be used.

The first electrode 32 is formed on the lower front surface of the upper substrate 30 to cover all of the auxiliary electrodes 31. The first electrode 32 may be an anode electrode and may be formed of at least one transparent conductive material among ITO, IZO, and AZO. Here, since one side of the first electrode 32 is connected to the common power line through a pad electrode (not shown) of the non-light emitting area, the first electrode 32 and the auxiliary electrode 31 are connected to the common power line from the common power line. To be supplied.

The buffer layer 33 is formed of an inorganic insulating material in the non-light emitting region where the auxiliary electrode 31 is formed. The buffer layer 33 is to compensate for the thickness, height, and adhesion of the contact spacer 35 or the separator 34 and may be made of any one of inorganic insulating materials of SiNx, SiOx, SiON, and SiOy.

The contact spacer 35 is formed in a columnar shape in an area in which electrical contact between the second electrode 38 and the lower substrate 10 of the upper substrate 30 is required. The contact spacer 35 is an inverse taper, that is, an inverted trapezoid. It may be formed in the form. Specifically, the contact spacer 35 is to allow the second electrode 38 formed on the lowermost surface of the upper substrate 30 to be in electrical contact with the contact electrode 25 of the lower substrate 10. It is formed in an inverted trapezoidal shape at a position corresponding to a part of the contact electrode 25 forming region of 10). The contact spacer 35 may be formed by patterning at least one of a transparent organic material having a refractive index of the visible light band, for example, poly styrenr, poly 2-vinylthiophene, and poly vinylcarbazole.

The separator 34 is formed in a region corresponding to the auxiliary electrode 31 in the form of a partition wall surrounding each sub-pixel. The gate line GL or the data line of the lower substrate 10 depends on the position of the auxiliary electrode 31. It may be formed to correspond to the DL. The separator 34 may be formed by applying a photosensitive organic material, for example, photoresist (PR), photo acryl, or benzocyclobutene (BCB), and then patterning the photoresist.

In the formation of at least one structure of the buffer layer 33, the contact spacer 35, and the separator 34, the protrusions L of the present invention described above may be formed together in the same process with the same material.

The organic light emitting layer 37 includes a hole injection layer HIL, a hole transport layer HTL, a light emitting layer OEL, an electron injection layer EIL, and an electron transport layer ETL. The hole injection layer HIL is formed on the lower front surface of the upper substrate 30 including the first electrode 32, for example, the anode electrode and the contact spacer 35, and the hole transport layer HTL is formed in the hole injection layer H. HIL) is formed on the lower front surface of the upper substrate 30. In addition, the emission layer OEL is formed on the hole transport layer HTL of the emission region, and the electron injection layer EIL is formed on the lower front surface of the upper substrate 30 including the emission layer OEL and the hole transport layer HTL. . The electron transport layer ETL is formed on the entire surface of the upper substrate 30 including the electron injection layer EIL.

The second electrode 38 is formed to cover the organic light emitting layer 37 separated by sub-pixel units by the separator 34 or the like. The second electrode 38 may be a cathode electrode, and aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, ITO, ITO / Ag / ITO, or ITO having a relatively small work function value. / Ag / IZO (Indium Zinc Oxide) and the equivalent may be formed of at least one material. Here, silver (Ag) may reflect light from the organic light emitting layer 37 to the upper surface in the upper light emission method. When the second electrode 38 is formed, the upper antistatic pattern 27b of the present invention described above may be simultaneously formed.

6B, a sealant SL is formed in the non-display area 1b of the upper or lower substrates 10 and 30, and the sealant SL is formed by the at least one protrusion L. Referring to FIG. The upper antistatic pattern 27b formed in the non-display area 1b and the dummy regions DU1 and DU2 is bonded to be electrically connected to the lower antistatic pattern 27a. 6C, a predetermined point of the non-display area 1b is scribed and cut to remove the dummy areas DU1 and DU2.

Accordingly, the upper antistatic pattern 27b and the lower antistatic pattern 27a after the contact remain in some areas of the completed display panel 1 of the present invention, that is, some areas of the non-display area 1b. do.

As described above, when cutting the display panel 1 of the present invention, the static electricity prevention patterns formed in the dummy areas DU1 and DU2 and the non-display area 1b are simultaneously cut so that the static electricity generated during the cutting may be transferred through the antistatic pattern parts. It can be distributed to the outside. Therefore, the defect rate during the manufacturing process of the display panel 1 can be reduced to further improve the process yield.

Although the detailed description of the present invention described above has been described with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art have ordinary skill in the art. It is apparent that the present invention can be variously modified and changed without departing from the spirit and technical scope.

1 is a circuit diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention. 2 is an equivalent circuit diagram illustrating one sub-pixel of the display panel illustrated in FIG. 1.

FIG. 3 is a circuit diagram illustrating a manufacturing process of the display panel illustrated in FIG. 1.

4 is a cross-sectional view illustrating a region II ′ shown in FIG. 3;

5A and 5B are cross-sectional views illustrating a method of manufacturing the display panel illustrated in FIGS. 1 and 3.

6A and 6C are cross-sectional views illustrating a method of manufacturing a display panel according to another exemplary embodiment of the present invention.

* Brief description of symbols for the main parts of the drawings.

1: display panel 2: gate driver

3: data driver 4: power supply

5: moving control part 11: gate electrode

19: first electrode 22: second electrode

27a: lower antistatic pattern 27b: upper antistatic pattern

L: projection EC: upper substrate

SL: sealant 28: insulation pattern

Claims (10)

Lower and upper substrates including an image display area and a non-display area and bonded to face each other; A plurality of cell drivers formed in the non-emission area of the image display area; A plurality of light emitting cells formed in the light emitting area of the image display area; And And at least one antistatic pattern formed on at least one of the upper and lower substrates along the substrate cutting line so as to overlap the substrate cutting lines formed in the non-display areas of the lower and upper substrates. Display. The method of claim 1, The at least one antistatic pattern is The pattern is formed integrally with the antistatic pattern portions formed in the dummy regions of the lower and upper substrates. When the dummy regions are removed, the antistatic pattern portion is cut to remove at least one of the upper and lower substrates of the non-display region. A light emitting display device, characterized in that the remaining pattern. The method of claim 2, The antistatic pattern portion Is formed in some or all of the non-display area and the dummy area, A lower antistatic pattern formed of at least one conductive metal material on the lower substrates of the non-display area and the dummy area; At least one protrusion integrally formed with the upper substrate on the upper substrate of the dummy region, and An upper portion formed in the non-display area and the dummy area of the upper substrate to cover all of the at least one protrusion and electrically connected to the lower antistatic pattern by the at least one protrusion when the upper substrate and the lower substrate are bonded together A light emitting display device comprising an antistatic pattern. The method of claim 3, wherein The lower antistatic pattern is It may be formed through the same process for forming the gate electrode or the source / drain electrode of the switching device or through the same process for forming the first or second electrode of the light emitting cell, The upper antistatic pattern may be formed separately on the upper substrate or may be formed through the same process when forming the first or second electrode of the light emitting cell. The method of claim 4, wherein The at least one protrusion Light emission, which is formed integrally with the upper substrate in the dummy region of the upper substrate or is formed through the same process as at least one structure of a buffer layer, a contact spacer and a separator when the plurality of light emitting cells and the cell driver are formed. Display. Preparing upper and lower substrates, respectively; Forming a plurality of cell drivers in the image display area of the lower substrate; Forming a plurality of light emitting cells in an image display area of the upper or lower substrate; Forming at least one antistatic pattern on at least one of the upper and lower substrates along the substrate cutting line to overlap the substrate cutting lines formed in the non-display areas of the upper and lower substrates; And And bonding the upper and lower substrates together. The method of claim 6, The at least one antistatic pattern forming step Forming an antistatic pattern portion on the upper and lower substrate dummy regions, and Cutting and removing the upper and lower substrate dummy regions, And removing the dummy regions so that the antistatic pattern portion formed on the dummy regions is cut and left on at least one of the upper and lower substrates of the non-display region. The method of claim 7, wherein The antistatic pattern portion forming step Forming a lower antistatic pattern on at least one conductive metal material on the non-display area and the dummy area of the lower substrate, and The upper substrate of the dummy region covers all of the at least one protrusion integrally formed with the upper substrate, and is electrically connected to the lower antistatic pattern by the at least one protrusion when the upper substrate and the lower substrate are bonded together. And forming an upper antistatic pattern on the upper substrate such that the upper substrate is connected to the upper substrate. The method of claim 8, The lower antistatic pattern is It may be formed through the same process for forming the gate electrode or the source / drain electrode of the cell driving unit or the same process for forming the first or second electrode of the light emitting cell, The upper antistatic pattern may be formed separately on the upper substrate or may be formed through the same process when forming the first or second electrode of the light emitting cell. The method of claim 9, The at least one protrusion Fabrication of a light emitting display device, characterized in that formed in the dummy region of the upper substrate integrally with the upper substrate or through the same process as at least one structure of a buffer layer, a contact spacer and a separator when the plurality of cell drivers are formed. Way.

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