KR20100121844A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a method for fabricating the same are provided to extend the gap between a storage node contact and bit lines by forming the bit line in different layer which is arranged in a grid. CONSTITUTION: A first interlayer insulating film(13) is formed on a substrate(10). First bit lines are formed on the first interlayer insulating film and are extended in a specific direction. A second interlayer insulating film(14) covers the first bit lines. A third interlayer insulating film(15) is formed on the second interlayer insulating film.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same for reducing the capacitance between the bit line and the storage node.

In DRAM devices, in which a unit cell is composed of one MOS transistor and one capacitor, it is highly integrated to reduce the area while increasing the capacitance of a capacitor that occupies a large area on a chip. Has become an important factor.

In order to form a capacitor having a high capacitance in a small area, attempts have been made to increase the height of the capacitor or to reduce the thickness of the dielectric film.

However, when the height of the capacitor is increased, there is a problem that the step difference between the cell region and the peripheral region is increased, and when the thickness of the dielectric film is decreased, the leakage current increases as the thickness of the dielectric film is decreased.

In order to overcome these problems, recently, a method of using embedded gates to reduce the bit line parasitic capacitance to half level has been introduced to drastically lower the capacitance of the capacitor required to maintain the same sense amplifier driving capability. .

However, there is a need for a method to further reduce the bit line parasitic capacitance in a situation where the cell area is continuously reduced.

Bit line parasitic capacitance is composed of 1) capacitance between bit line and word line, 2) capacitance between bit line and storage node, 3) capacitance between bit line and bit line, and 4) capacitance between bit line and substrate.

Among these, 3) and 4) components are less than 5% of the total bit line parasitic capacitance, and 1) and 2) components contribute about half of the bit line parasitic capacitance.

The buried gate lowers the overall bitline parasitic capacitance to half by lowering component 1) to 1/10.

In this situation, the remaining technical task is to reduce the capacitance between component 2), that is, the bit line and the storage node. If this is achieved, the overall bit line parasitic capacitance can be significantly reduced. It seems to be.

To reduce the capacitance between the bitline and the storage node, the distance between the bitline and the storage node contact should be as large as possible.

However, since the storage node contacts are inevitably formed on the bit lines by the pattern refinement, the distance between the bit lines and the storage node contacts is inevitably determined by the width of the bit line spacers.

Therefore, in order to reduce the capacitance between the bit line and the storage node, the thickness of the bit line spacer must be increased. However, when the thickness of the bit line spacer is increased, it is difficult to actually apply a method of increasing the thickness of the bit line spacer because the side area between the storage node contact and the substrate is reduced to decrease the device driving ability.

In addition, a bit line spacer is formed of a nitride layer in order to secure an etching selectivity with an interlayer dielectric layer of an oxide layer when etching a storage node contact using a self-aligned contact method. Since the nitride layer has a higher dielectric constant than the oxide layer, the bit line and the storage node It is the cause of the increase in liver capacitance.

The present invention provides a semiconductor device and a method of manufacturing the same to reduce the capacitance between the bit line and the storage node.

A semiconductor device according to an embodiment of the present invention includes a first interlayer insulating film formed on a substrate, first bit lines extending in one direction on the first interlayer insulating film, and a second interlayer covering the first bit lines. An insulating film, a third interlayer insulating film formed on the second interlayer insulating film, second bit lines extending in the one direction on the third interlayer insulating film and disposed between the first bit lines, A fourth interlayer insulating film covering second bit lines, first landing plug contacts connected to the substrate through the first interlayer insulating film, and the first interlayer insulating film adjacent to the first bit lines through the second interlayer insulating film; First storage node contacts connected to a portion of the first landing plug contacts in a state of being offset by a predetermined width from the other side of the first landing plug contacts; Second landing plug contacts penetrating the film and connected to the first storage node contacts, and the other side facing the one side of the second landing plug contacts adjacent to the second bit lines through the fourth interlayer insulating layer; And second storage node contacts connected to a portion of the second landing plug contacts in a state of being offset by a predetermined width.

In the semiconductor device, first bit line contacts penetrating the first interlayer insulating layer to connect the substrate and the first bit lines, and the substrate and the third interlayer insulating layer penetrate through the third, second and first interlayer insulating layers. And second bit line contacts connecting the second bit lines.

In the semiconductor device, the second and fourth interlayer insulating films are formed of an oxide film.

The semiconductor device may further include a spacer between the first landing plug contacts and the first interlayer insulating layer.

The semiconductor device may further include a spacer between the first storage node contacts and the second interlayer insulating layer.

The semiconductor device may further include a spacer between the second landing plug contacts and the third interlayer insulating layer.

The semiconductor device may further include a spacer between the second storage node contacts and the fourth interlayer insulating layer.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first interlayer dielectric layer on a substrate in a cell region, and forming first landing plug contacts connected to the substrate through the first interlayer dielectric layer. Forming first bit lines extending in one direction on the first interlayer insulating film, forming a second interlayer insulating film covering the first bit lines, and penetrating the second interlayer insulating film. Forming first storage node contacts connected to a portion of the first landing plug contacts in a state of being offset by a predetermined width from the other side opposite to the one side of the first landing plug contacts adjacent to the first bit lines; Forming a third interlayer dielectric layer on the second interlayer dielectric layer and penetrating the third interlayer dielectric layer to be connected to the second storage node contacts; Forming second landing plug contacts, forming second bit lines extending in the one direction and disposed between the first bit lines on the third interlayer insulating film, and covering the second bit lines. Forming a fourth interlayer insulating film; and displacing the fourth interlayer insulating film by a predetermined width from the other side facing the one side of the second landing plug contacts adjacent to the second bit lines through the fourth interlayer insulating film. Forming second storage node contacts that are connected to a portion of the contacts.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, the second and fourth interlayer insulating films are formed of an oxide film.

In the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, after the forming of the second storage node contacts, the method may further include forming a capacitor on the second storage node contacts.

In the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, the forming of the first landing plug contacts may include forming contact holes exposing a portion of the substrate by patterning the first interlayer insulating layer by a photolithography process. And forming a conductive film on the entire surface including the contact holes, and removing the conductive films formed on the outside of the contact holes.

The method may further include forming spacers on side surfaces of the contact holes before forming the conductive layer.

In the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, the forming of the first storage node contacts may include patterning the second interlayer insulating layer by a photolithography process to form the first landing adjacent to the first bit lines. Forming contact holes exposing a portion of the first landing plug contacts and a portion of the first interlayer insulating layer adjacent to the first landing plug contacts including the other side opposite to one side of the plug contacts, and forming a conductive film on the entire surface including the contact holes. And removing the conductive film formed on the outside of the contact holes.

The method may further include forming spacers on side surfaces of the contact holes before forming the conductive layer.

In the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, the forming of the second landing plug contacts may include contact holes exposing the first storage node contacts by patterning the third interlayer insulating layer by a photolithography process. And forming a conductive film on the entire surface including the contact holes, and removing the conductive films formed on the outside of the contact holes.

The method may further include forming spacers on side surfaces of the contact holes before forming the conductive layer.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, the forming of the second storage node contacts may include patterning the fourth interlayer insulating layer by a photolithography process to form the second landing adjacent to the second bit lines. Forming contact holes exposing a portion of the second landing plug contacts and a portion of the third interlayer insulating film adjacent to the second landing plug contacts including the other side of the plug contacts; and forming a conductive film on the entire surface including the contact holes. And removing the conductive film formed on the outside of the contact holes.

The method may further include forming spacers on side surfaces of the contact holes before forming the conductive layer.

In a method of manufacturing a semiconductor device according to an embodiment of the present invention, in the forming of the first landing plug contacts, a first bit line is connected to the substrate through the first interlayer insulating layer under the first bit line. Further forming contacts.

After forming the second landing plug contacts in the method of manufacturing a semiconductor device according to an embodiment of the present invention, the substrate passes through the third, second, and first interlayer insulating layers under the second bit lines. And forming second bit line contacts connected to the second bit line contacts.

The second bit line contacts may be formed together when bit line contacts are formed in a peripheral region outside the cell region.

The second bit line contacts may form contact holes by etching the third, second and first interlayer insulating layers of the cell region together when the bit line contact holes are formed in a peripheral region outside the cell region. A conductive layer is embedded in the bit line contact holes in a peripheral area, and the contact holes in the cell area are filled together when the bit line contacts are formed.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, when the second landing plug contact is formed, the semiconductor device is connected to the substrate by passing through the third, second, and first interlayer insulating layers under the second bit lines. And further forming second bit line contacts.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, the first bit lines may be formed together when a gate is formed in a peripheral region existing outside the cell region.

The first bit line is formed by extending the gate conductive layer to the cell region when the gate conductive layer is formed in the peripheral region and patterning the gate conductive layer of the peripheral region to pattern the gate conductive layer formed in the cell region when the gate is formed. Characterized in that it is formed.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, the second bit lines may be formed together when the bit lines are formed in the peripheral region existing outside the cell region.

The second bit lines may be formed by extending the bit line conductive layer to the cell region when the bit line conductive layer is formed in the peripheral region, and patterning the bit line conductive layer of the peripheral region to form the bit line conductive layer. And the bit line conductive film is patterned together.

In another embodiment, a method of manufacturing a semiconductor device includes forming a first interlayer insulating film on a substrate in a cell region and a peripheral region, and connecting the substrate to the cell region through the first interlayer insulating film. Forming first landing plug contacts, removing the first interlayer dielectric layer in the peripheral region, and forming and patterning a conductive film on the cell region and the peripheral region to form the first interlayer dielectric layer in the cell region Forming first bit lines extending in one direction on the substrate and forming gates on the substrate in the peripheral region; forming a second interlayer insulating layer on the cell region and the peripheral region; Penetrates through the second interlayer insulating film of the substrate and is offset by a predetermined width from the other side of the first landing plug contacts adjacent to the first bit lines; Forming first storage node contacts connected to a portion of the first landing plug contacts, forming a third interlayer dielectric layer on the cell region and the peripheral region, and forming a third interlayer dielectric layer on the cell region. Forming second landing plug contacts connected to the first storage node contacts through the through hole, and forming and patterning a conductive film on the cell region and the peripheral region on the third interlayer insulating layer of the cell region. Forming second bit lines extending in the one direction and interposed between the first bit lines, and forming third bit lines on the third interlayer insulating layer of the peripheral region; Forming a fourth interlayer dielectric layer over the region, and passing through the fourth interlayer dielectric layer in the cell region to be adjacent to the second bit lines; Article characterized in that it comprises a step of forming a second storage node contacts that are connected to a portion of the second landing plug contacts to the other side out of position by the predetermined width opposite to the one side of the second landing plug contacts.

In the method of manufacturing a semiconductor device according to another embodiment of the present invention, the forming of the first landing plug contacts may include contact holes exposing a portion of the substrate of the cell region by patterning the first interlayer insulating layer by a photolithography process. And forming a conductive film on the entire surface including the contact holes, and removing the conductive films formed on the outside of the contact holes.

The method may further include forming spacers on side surfaces of the contact holes before forming the conductive layer.

In the method of manufacturing a semiconductor device according to another embodiment of the present invention, the forming of the first storage node contacts may include patterning the second interlayer insulating layer by a photolithography process to form the first landing adjacent to the first bit lines. Forming contact holes exposing a portion of the first landing plug contacts and a portion of the first interlayer insulating layer adjacent to the first landing plug contacts including the other side opposite to one side of the plug contacts, and forming a conductive film on the entire surface including the contact holes. And removing the conductive film formed on the outside of the contact holes.

The method may further include forming a spacer on a side of the contact hole before forming the conductive layer.

In the method of manufacturing a semiconductor device according to another embodiment of the present invention, the forming of the second landing plug contacts may include contact holes exposing the first storage node contacts by patterning the third interlayer insulating layer by a photolithography process. And forming a conductive film on the entire surface including the contact holes, and removing the conductive films formed on the outside of the contact holes.

The method may further include forming a spacer on a side of the contact hole before forming the conductive layer.

In the method of manufacturing a semiconductor device according to another embodiment of the present invention, the forming of the second storage node contacts may include patterning the fourth interlayer insulating layer by a photolithography process to form the second landing adjacent to the second bit lines. Forming contact holes exposing a portion of the second landing plug contacts and a portion of the third interlayer insulating layer adjacent to the second landing plug contacts including the other side opposite to one side of the plug contacts, and forming a conductive film on the entire surface including the contact holes And removing the conductive film formed on the outside of the contact holes.

The method may further include forming a spacer on a side of the contact hole before forming the conductive layer.

In the method of manufacturing a semiconductor device according to another embodiment of the present invention, the method may further include forming capacitors on the second storage node contacts after the forming of the second storage node contacts.

In the method of manufacturing a semiconductor device according to another embodiment of the present invention, in the forming of the first landing plug contacts, the cell region and the penetrating layer may pass through the first interlayer insulating layer under the first bit line of the cell region. And forming first bit line contacts respectively connected to the substrates in the peripheral region.

In a method of manufacturing a semiconductor device according to another embodiment of the present invention, before forming the second bit lines and the third bit lines, the third, second, and first portions below the second and third bit lines are formed. And forming second and third bit line contacts penetrating the interlayer insulating layer to be connected to the substrate in the cell region and the peripheral region, respectively.

In the method of fabricating a semiconductor device according to another embodiment of the present invention, the cell region penetrates through the third, second and first interlayer insulating layers under the second and third bit lines when the second landing plug contact is formed. And second and third bit line contacts respectively connected to the substrate in the peripheral region.

According to the present invention, bit lines are formed in different layers in different arrays to increase the distance between the bit lines, and storage node contacts are formed by layering each layer using a landing plug contact to form a storage node contact and a bit. The distance between lines can be maximized. In addition, unlike the conventional technology in which the bit line and the storage node contact are filled only with a nitride-based bit line spacer, the insulating layer between the bit line and the storage node contact is filled with an oxide-based material having a lower dielectric constant than that of the nitride film. The dielectric constant can be lowered. As a result, the capacitance between the bit line and the storage node is reduced by 1/5 to 1/10 as compared with the conventional art.

Since the capacitance between the bit line and the storage node is reduced, the bit line parasitic capacitance is reduced, thereby reducing the capacitance value of the cell capacitor required to maintain the driving ability of the same sense amplifier.

In addition, since the driving capability of the sense amplifier is improved at the same capacitance, the retrace characteristics are improved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along lines II ′ and II-II ′ of FIG. 1.

1 and 2, a semiconductor device according to the present invention includes first, second, third, and fourth interlayer insulating films 13, 14, 15, and 16 stacked on a substrate 10 and a first layer. First bit lines BL1 extending in one direction on the interlayer insulating layer 13 and second bit lines extending in one direction on the third interlayer insulating layer 15 and disposed between the first bit lines BL1. Pass through the lines BL2, the capacitors 100 formed on the fourth interlayer insulating film 16, and the first, second, third, and fourth interlayer insulating films 13, 14, 15, and 16, respectively. The first landing plug contacts LPC1, the first storage node contacts SNC1, the second landing plug contacts LPC2, and the second storage node contacts that connect the substrate 10 and the capacitors 100 to each other. (SNC2).

In this case, the first storage node contacts SNC1 may have a first landing plug adjacent to the first bit lines BL1 to maximize the distance D1 between the first storage node contacts SNC1 and the first bit lines BL1. The first storage plug contacts SPC2 are connected to a portion of the first landing plug contacts LPC1 in a state of being shifted by a predetermined width W1 from the other side facing the one side of the contacts LPC1, and the second storage node contacts SNC2 are connected to the second storage node contacts (SNC2). The other side facing the one side of the second landing plug contacts LPC2 adjacent to the second bit lines BL2 so as to maximize the distance D2 between the SNC2 and the second bit lines BL2 by a predetermined width W2. It is connected to a part of the second landing plug contacts LPC2 in a misaligned state.

More specifically, an isolation layer 11 is formed on the substrate 10 to define the active region 10A.

In order to increase the degree of integration, the active region 10A may be designed to be inclined in a diagonal direction with a predetermined angle θ1 rather than in a vertical or horizontal direction.

The gate line G is formed in one direction on the substrate 10.

The gate line G is composed of a gate electrode film formed through the gate insulating film. The gate electrode film may be made of metal, for example TiN, W, or the like.

The gate line G may have a buried structure embedded in a recess formed in the substrate 10.

Sources and drains S and D are formed in the active region 10A on both sides of the gate line G.

A liner layer (not shown) and a capping layer 12 are stacked on the substrate 10 including the gate line G, and a first interlayer insulating layer 13 is formed on the capping layer 12. The first interlayer insulating layer 13 may be formed of an oxide-based material.

First landing plug contacts LPC1 may be formed on the sources S to be connected to the sources S through the first interlayer insulating layer 13 and the capping layer 12.

The first landing plug contact LPC1 is for connecting the source S and the first storage node contact SNC1 thereon, and keeps the contact resistance between the source S and the first storage node contact SNC1 low. It is configured in a size and shape that may have a sufficient contact area with the source (S) and the first storage node contact (SNC1).

Although not shown, a spacer may be further formed between the first landing plug contacts LPC1 and the first interlayer insulating layer 13. The spacer may be made of a nitride film-based material, and the thickness of the spacer may range from 10 to 50 μs.

First bit lines BL1 extending in a direction perpendicular to the gate line G are formed on the first interlayer insulating layer 13.

The first bit lines BL1 are disposed on the drains D in the odd-numbered columns and are odd through the first bit line contacts BLC1 formed through the first interlayer insulating layer 13 and the capping layer 12. It is electrically connected to the drains D located in the second column.

A second interlayer insulating film 14 covering the first bit lines BL1 is formed on the first interlayer insulating film 13. The second interlayer insulating film 14 may be formed of an oxide film-based material.

First storage node contacts SNC1 are formed on the first landing plug contacts LPC1 and are connected to the first landing plug contacts LPC1 through the second interlayer insulating layer 14.

The first storage node contacts SNC1 may be connected to the first landing plug contacts LPC1 and may be connected to the first bit lines BL1 such that the distance D1 from the first bit lines BL1 is maximized. The first landing plug contact LPC1 is connected to a portion of the first landing plug contact LPC1 adjacent to the other side of the first landing plug contact LPC1 by a predetermined width W1.

In this case, the width W1 of the first storage node contact SNC1 shifted from the other sides of the first landing plug contacts LPC1 may be 1/2 to 1 times the width of the first bit line BL1.

Although not shown, a spacer (not shown) may be further formed between the first storage node contacts SNC1 and the second interlayer insulating layer 14. The spacer may be made of a nitride film-based material, and the thickness of the spacer may range from 10 to 50 μs.

The third interlayer insulating film 15 is laminated on the second interlayer insulating film 14. The third interlayer insulating film 15 may be formed of an oxide film-based material.

Second landing plug contacts LPC2 are formed in the third interlayer insulating layer 15 and are connected to the first storage node contacts SNC1 through the third interlayer insulating layer 15.

The second landing plug contact LPC2 is for connecting the first storage node contact SNC1 and the second storage node contact SNC2 thereon, and the first storage node contact SNC1 and the second storage node contact SNC2. ) And a size and shape that may have a sufficient contact area with the first storage node contact (SNC1) and the second storage node contact (SNC2) to maintain a low contact resistance.

Although not shown, a spacer may be further formed between the second landing plug contacts LPC2 and the third interlayer insulating layer 15. The spacer may be made of a nitride film-based material, and the thickness of the spacer may range from 10 to 50 μs.

Meanwhile, second bit lines BL2 extending in the same direction as the first bit line BL1 and disposed between the first bit lines BL1 are formed on the third interlayer insulating layer 15. The second bit lines BL2 are disposed on the drains D in the even-numbered columns, and the third, second, and first interlayer insulating layers 15, 14, and 13 are disposed below the second bit lines BL2. The second bit line contacts BLC2 passing through the capping layer 12 are electrically connected to drains D positioned in even-numbered columns.

A fourth interlayer insulating layer 16 covering the second bit lines BL2 is formed on the third interlayer insulating layer 15. The fourth interlayer insulating film 16 may be formed of an oxide film-based material.

Second storage node contacts SNC2 are formed in the fourth interlayer insulating layer 16 and penetrate the fourth interlayer insulating layer 16 to be connected to the second landing plug contacts LPC2. The second storage node contacts SNC2 are connected to the second landing plug contacts LPC2 and are adjacent to the second bit lines BL2 such that the distance D2 from the second bit lines BL2 is maximized. The second landing plug contacts LPC2 are connected to a portion of the second landing plug contacts LPC2 in a state of being shifted by a predetermined width W2 from the other side opposite to one side.

In this case, the width W2 of the second storage node contact SNC2 deviated from the other sides of the second landing plug contacts LPC2 may be 1/2 to 1 times the width of the second bit line BL2.

Although not shown, a spacer (not shown) may be further formed between the second storage node contacts SNC2 and the fourth interlayer insulating layer 16. The spacer may be made of a nitride film-based material, and the thickness of the spacer may range from 10 to 50 μs.

A storage node 17 is formed on the second storage node contacts SNC2, and a dielectric film 18 and a plate electrode 19 are stacked on the storage node 17 to form a capacitor 100.

A method of manufacturing a semiconductor device having the above structure is as follows.

3A to 3J are plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 4A to 4J are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. admit.

4A to 4J, the left side shows a cross-sectional view along the line II ′ of FIGS. 3A to 3J, and the right side shows a cross-sectional view along the II-II ′ line of FIGS. 3A to 3J.

3A and 4A, an isolation layer 11 is formed on a substrate 10 having a cell region and a peripheral region (not shown) to define an active region 10A.

In order to increase the degree of integration, the active region 10A may be designed to be inclined in a diagonal direction with a predetermined angle θ1 rather than in a vertical or horizontal direction.

3B and 4B, a gate line G that crosses the active region 10A is formed in the substrate 10 of the cell region.

In order to reduce the bit line parasitic capacitance, the gate line G may be formed in a buried structure.

The buried gate line G forms a recess by etching the device isolation film 11 and the substrate 10 at the gate predetermined portion, forms a gate insulating film on the entire surface including the recess, and forms a gate insulating film on the gate insulating film. The gate electrode film may be formed by filling the recesses, and then etching the entire surface of the gate electrode film so that the surface of the bit electrode film is lowered below the surface of the substrate 10.

As the gate electrode film, a metal such as TiN or WN can be used.

Thus, when the gate electrode film is formed of a metal film (the work function and energy band gap of the metal have an intermediate value between the work function and energy band gap of the N + type polysilicon film and the P + type polysilicon film), the N channel transistor and the P channel It has the advantage of being utilized as a midgap gate that can be used as the gate electrode of a transistor.

As a method of forming the gate electrode layer, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process may be used.

Subsequently, impurities are implanted into the active regions 10A on both sides of the gate line G to form source and drains S and D.

Next, the liner film (not shown) and the capping film 12 are sequentially formed in order to prevent oxidation and other deterioration of the gate electrode film used for the gate line G in a subsequent thermal process.

An oxide film may be used as the liner film, and a nitride film or a composite film of the nitride film and the oxide film may be used as the capping film 12.

3C and 4C, a first interlayer insulating film 13 is formed on the capping film 12. An oxide film-based material may be used for the first interlayer insulating film 13.

Then, the first landing plug contacts LPC1 connected to the sources S through the first interlayer insulating film 13 and the capping film 12 and the drains D located in the odd-numbered column, and First bit line contacts BLC1 are formed.

 The first landing plug contacts LPC1 and the first bit line contacts BLC1 are positioned in the source S and the odd-numbered rows by patterning the first interlayer insulating layer 13 and the capping layer 12 by a photolithography process. It may be formed by forming contact holes exposing the drains D, forming a conductive film, for example, a polysilicon film on the entire surface including the contact holes, and then removing the conductive film formed outside the contact holes.

Although not shown, a spacer may be further formed on the side surfaces of the contact holes before forming the conductive layer. As the spacer, a nitride film-based material may be used. The thickness of the spacer may range from 10 to 50 microns.

The first bit line contacts BLC1 are not connected to the drains D in the even-numbered column, but are connected only to the drains D in the odd-numbered column, so that the number of the first bit line contacts BLC1 is limited. Is half of the number of conventional bit line contacts.

3D and 4D, the first bit lines BL1 connected to the first bit line contacts BLC1 on the first interlayer insulating layer 13 and extending in a direction perpendicular to the gate line G are disposed. Form.

The first bit lines BL1 are formed in the odd column to be connected to the first bit line contacts BLC1 connected to the drains D positioned in the odd column.

Therefore, the number of first bit lines BL1 is half the number of conventional bit lines, and the interval between the first bit lines BL1 is twice the size of the gap between the conventional bit lines.

The first bit lines BL1 may be formed together when the gate electrode is formed in the peripheral area (not shown).

That is, the first bit lines BL1 are formed by extending the gate conductive layer to the cell region when forming the gate conductive layer in the peripheral region, patterning the gate conductive layer in the peripheral region, and patterning the gate conductive layer formed in the cell region when forming the gate together. , Can be formed.

3E and 4E, a second interlayer insulating film 14 is formed on the entire surface including the first bit line BL1. An oxide film-based material may be used for the second interlayer insulating film 14.

Subsequently, a planarization process, for example, a chemical mechanical polish (CMP) process, may be performed to remove the step generated in the second interlayer insulating layer 14 due to the first bit line BL1.

Thereafter, the first landing penetrates through the second interlayer insulating layer 14 to the other side opposite to one side of the first landing plug contacts LPC1 adjacent to the first bit lines BL1 by a predetermined width W1. First storage node contacts SNC1 are formed to be connected to a portion of the plug contacts LPC1.

Since the distance between the first bit lines BL1 is twice as large as the conventional size, general photolithography is performed without forming the first storage node contacts SNC1 on the first bit line BL1 in a self-aligned contact (SAC) manner. It forms using a process.

That is, the first storage node contacts SNC1 may pattern the second interlayer insulating layer 14 by a photolithography process so as to face the other side facing one side of the first landing plug contacts LPC1 adjacent to the first bit lines BL1. Contact holes exposing a portion of the first landing plug contacts LPC1 and a portion of the first interlayer insulating layer 13 adjacent thereto, and a conductive film, for example, a polysilicon layer, is formed on the entire surface including the contact holes. Next, the conductive layer formed on the outside of the contact hole may be removed and formed.

Although not shown, a spacer may be further formed on the side surfaces of the contact holes before forming the conductive layer. As the spacer, a nitride film-based material may be used. The thickness of the spacer may range from 10 to 50 microns.

Since the first storage node contacts SNC1 are formed to be shifted from the other sides of the first landing plug contacts LPC1 farthest from the first bit lines BL1 by a predetermined width W1, the first storage node contacts SNC1. And the distance D1 between the first bit lines BL1 are maximized.

In this case, the width W1 of the first storage node contact SNC1 shifted from the other sides of the first landing plug contacts LPC1 may be 1/2 to 1 times the width of the first bit line BL1.

3F and 4F, a third interlayer insulating layer 15 is formed on the second interlayer insulating layer 14 including the first storage node contact SNC1. As the third interlayer insulating film 15, an oxide-based material may be used.

Subsequently, second landing plug contacts LPC2 are formed through the third interlayer insulating layer 15 to be connected to the first storage node contacts SNC1.

The second landing plug contacts LPC2 may form contact holes exposing the first storage node contacts SNC1 by patterning the third interlayer insulating layer 15 by a photolithography process, and a conductive layer on the entire surface including the contact holes, For example, it may be formed by forming a polysilicon film and removing the conductive film formed outside the contact hole.

Although not shown, a spacer may be further formed on the side surfaces of the contact holes before the conductive film is formed. As the spacer, a nitride film-based material may be used. The thickness of the spacer may range from 10 to 50 microns.

Referring to FIGS. 3G and 4G, the even-numbered columns not penetrating the third bit line contact BLC1 through the third, second, and first interlayer insulating films 15, 14, and 13 and the capping film 12 are connected to each other. Second bit line contacts BLC2 are formed to be connected to the drains D.

The second bit line contacts BL2 may pattern the third, second, and first interlayer insulating layers 15, 14, and 13 and the capping layer 12 by a photolithography process to form drains D positioned in even-numbered columns. It may be formed by forming contact holes exposing, forming a conductive film, for example, a polysilicon film on the entire surface including the contact holes, and removing the conductive film formed outside the contact holes.

The second bit line contacts BLC2 are not connected to the drains D located in the odd-numbered column, but are connected only to the drains D positioned in the even-numbered column, so that the number of second bit line contacts BLC2 is Half the number of conventional bit line contacts.

The second bit line contacts BLC2 may be formed together when the bit line contacts are formed in the peripheral area (not shown).

That is, the second bit line contacts BLC2 may etch the third, second, and first interlayer insulating layers 15, 14, 13, and the capping layer 12 of the cell region together when the bit line contact holes are formed in the peripheral region. The contact hole may be formed, and a conductive film may be filled in the bit line contact hole in the peripheral area to fill the contact hole together when forming the bit line contact.

Meanwhile, in the embodiment illustrated in the drawings, the second landing plug contacts LPC2 and the second bit line contacts BLC2 are formed by separate processes, but may be formed at the same time.

3H and 4H, the first bit line BL1 extends in the same direction as the first bit lines BL1 on the third interlayer insulating layer 15 including the second bit line contacts BLC2. Second bit lines BL2 are disposed between the second bit lines BL2.

The second bit lines BL2 are connected to drains D positioned in even-numbered columns through second bit line contacts BLC2. For this purpose, the second bit lines BL2 are formed in even-numbered columns. Therefore, the number of second bit lines BL2 is half the number of conventional bit lines, and the distance between the second bit lines BL2 is twice the size of the conventional bit lines.

The second bit lines BL2 may be formed together when the bit lines are formed in the peripheral area. That is, the second bit lines BL2 are formed by extending the bit line conductive layer to the cell region when forming the bit line conductive layer in the peripheral region, and patterning the bit line conductive layer in the peripheral region to form the bit line conductive layer in the cell region when forming the bit line. The films can be formed by patterning them together.

3I and 4I, a fourth interlayer insulating film 16 is formed on the third interlayer insulating film 15 including the second bit lines BL2. An oxide film-based material may be used as the fourth interlayer insulating film 16.

Subsequently, a planarization process, for example, a CMP process, may be performed to remove a step generated in the fourth interlayer insulating layer 16 due to the second bit line BL2.

Next, the second landing is deviated by a predetermined width W2 from the other side facing the one side of the second landing plug contacts LPC2 adjacent to the second bit lines BL2 through the fourth interlayer insulating layer 16. Second storage node contacts SNC2 are formed to be connected to a portion of the plug contacts LPC2.

Since the distance between the second bit lines BL2 is twice as large as the conventional size, general photolithography is performed without forming the second storage node contacts SNC2 on the second bit line BL2 in a self-aligned contact (SAC) method. It forms using a process.

That is, the second storage node contacts SNC2 may be patterned by the fourth interlayer insulating layer 16 by a photolithography process so as to face the other side of the second landing plug contacts LPC2 adjacent to the second bit lines BL2. Contact holes exposing a portion of the second landing plug contacts LPC2 and a portion of the third interlayer insulating layer 15 adjacent thereto, and a conductive film, eg, a polysilicon layer, is formed on the entire surface including the contact hole Next, the conductive layer formed on the outside of the contact hole may be removed and formed.

Although not shown, a spacer may be further formed on the side surfaces of the contact holes before forming the conductive layer. As the spacer, a nitride film-based material may be used. The thickness of the spacer may range from 10 to 50 microns.

Since the second storage node contacts SNC2 are formed to be shifted from the other side of the second landing plug contacts LPC2 farthest from the second bit lines BL2 by a predetermined width W2, the second storage node contacts SNC2. And the distance D2 between the second bit lines BL2 is maximized.

In this case, the width W2 of the second storage node contact SNC2 deviated from the other sides of the second landing plug contacts LPC2 may be 1/2 to 1 times the width of the second bit line BL2.

3J and 4J, the capacitor 100 is formed by stacking the storage node 17, the dielectric layer 18, and the plate electrode 19 on the second storage node contact SNC2.

5A through 5J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 5A, an isolation layer 11 is formed on a substrate 10 having a cell region CELL and a peripheral region PERI to define an active region 10A.

In order to increase the degree of integration, the active region 10A of the cell region CELL may be designed to be inclined in a diagonal direction with a predetermined angle θ1 rather than in a vertical or horizontal direction.

Next, a gate line G across the active region 10A is formed in the substrate 10 of the cell region CELL.

In order to reduce the bit line parasitic capacitance, the gate line G may be formed in a buried structure.

The buried gate line G forms a recess by etching the device isolation film 11 and the substrate 10 at the gate predetermined portion, forms a gate insulating film on the entire surface including the recess, and forms a gate insulating film on the gate insulating film. After forming the gate electrode film to fill the recess, the gate electrode film may be completely etched to lower the surface of the gate electrode film below the surface of the substrate 10.

As the gate electrode film, a metal such as TiN or WN can be used.

In this way, when the gate electrode film is formed of a metal film (the metal work function and energy band gap have an intermediate value between the work function and energy band gap of the N + type polysilicon film and the P + type polysilicon film), the N channel transistor and the P channel transistor It has the advantage that can be utilized as a midgap gate (midgap gate) that can be used as a gate electrode of.

As the gate electrode film forming method, a CVD process or an ALD process may be used.

Subsequently, impurities are implanted into the active regions 10A on both sides of the gate line G to form source and drains S and D.

Next, the liner film (not shown) and the capping film 12 are sequentially formed in order to prevent oxidation and other deterioration of the gate electrode film used for the gate line G in a subsequent thermal process.

An oxide film may be used as the liner film, and a nitride film or a composite film of the nitride film and the oxide film may be used as the capping film 12.

Then, the liner film and the capping film 12 formed in the peripheral region PERI are removed.

Referring to FIG. 5B, a first interlayer insulating layer 13 is formed on the cell region CELL and the peripheral region PERI. An oxide film-based material may be used for the first interlayer insulating film 13.

Subsequently, the first landing plug contacts LPC1 connected to the sources S through the first interlayer insulating layer 13 and the capping layer 12 of the cell region CELL and the drain D positioned in an odd-numbered column. The first bit line contacts BLC1 are connected to the plurality of?

The first landing plug contacts LPC1 and the first bit line contacts BLC1 may be patterned by patterning the first interlayer insulating layer 13 and the capping layer 12 of the cell region CELL by a photolithography process. And contact holes exposing the drains D positioned in the odd-numbered columns and the odd-numbered columns, a conductive film, for example, a polysilicon film is formed on the entire surface including the contact hole, and the conductive film formed outside the contact hole is removed. .

Although not shown, a spacer may be further formed on the side surfaces of the contact holes before forming the conductive layer. As the spacer, a nitride film-based material may be used. The thickness of the spacer may range from 10 to 50 microns.

The first bit line contacts BLC1 are not connected to the drains D in the even-numbered column, but only to the drains D in the odd-numbered column, so that the number of the first bit line contacts BLC1 is Half the number of conventional bit line contacts.

Referring to FIG. 5C, the first interlayer insulating layer 13 formed in the peripheral region PERI is removed. Next, the gate insulating film 20 is formed on the substrate 10 of the peripheral region PERI, and the first conductive layer 21 for the gate electrode is formed on the cell region CELL and the peripheral region PERI. .

A polysilicon film may be used as the first conductive film 21.

Referring to FIG. 5D, the first conductive layer 21 formed in the cell region CELL is removed, and the second conductive layer 22 and the hard mask layer (not shown) are formed on the cell region CELL and the peripheral region PERI. Layer).

As the second conductive film 22, a metal or metal silassicide film may be used, and a nitride film may be used as the hard mask film.

Referring to FIG. 5E, the first bit line is formed on the cell region CELL by patterning the hard mask layer and the second and first conductive layers 22 and 21 of the cell region and the peripheral region by a photolithography process. First bit lines BL1 connected to the contact BLC1 and extending in a direction perpendicular to the gate line G are formed, and gates 200 are formed in the peripheral region PERI.

First bit lines BL1 formed in the cell region CELL are formed in odd-numbered columns to be connected to first bit line contacts BLC1 connected to drains D positioned in odd-numbered columns. Therefore, the number of first bit lines BL1 is half the number of conventional bit lines, and the interval between the first bit lines BL1 is twice the size of the gap between the conventional bit lines.

Referring to FIG. 5F, a second interlayer insulating layer 14 covering the first bit lines BL1 and the gates 200 is formed on the cell region CELL and the peripheral region PERI. An oxide film-based material may be used for the second interlayer insulating film 14.

Subsequently, a planarization process, for example, a CMP process, may be performed to remove a step generated in the second interlayer insulating layer 14 due to the first bit line BL1 and the gate 200.

Thereafter, the second interlayer insulating layer 14 of the cell region CELL passes through the second interlayer insulating layer 14 and has a predetermined width W1 on the other side facing the one side of the first landing plug contacts LPC1 adjacent to the first bit lines BL1. The first storage node contacts SNC1 are formed to be connected to a portion of the first landing plug contacts LPC1 in an offset state.

In this case, since the distance between the first bit lines BL1 is twice as large as the conventional size, the first storage node contacts SNC1 are not formed on the first bit line BL1 in the self-aligned contact SAC method. It is formed using a general photolithography process.

That is, the first storage node contacts SNC1 may face the other side of the first landing plug contacts LPC1 adjacent to the first bit lines BL1 by patterning the second interlayer insulating layer 14 by a photolithography process. Forming contact holes exposing a portion of the first landing plug contacts LPC1 and a portion of the first interlayer insulating layer 13 adjacent thereto, and forming a conductive layer, for example, a polysilicon layer, on the entire surface including the contact hole. Next, the conductive layer formed on the outside of the contact hole may be removed and formed.

Although not shown, a spacer may be further formed on the side surfaces of the contact holes before forming the conductive layer. As the spacer, a nitride film-based material may be used. The thickness of the spacer may range from 10 to 50 microns.

Since the first storage node contacts SNC1 are formed to be shifted from the other side of the first landing plug contacts LPC1 farthest from the first bit lines BL1 by a predetermined width W1, the first storage node contacts SNC1. And the distance D1 between the first bit lines BL1 is maximized.

In this case, the width W1 of the first storage node contact SNC1 shifted from the other sides of the first landing plug contacts LPC1 may be 1/2 to 1 times the width of the first bit line BL1.

Referring to FIG. 5G, a third interlayer insulating layer 15 is formed on the cell region CELL and the peripheral region PERI. As the third interlayer insulating film 15, an oxide-based material may be used.

Next, second landing plug contacts LPC2 connected to the first storage node contacts SNC1 are formed through the third interlayer insulating layer 15 of the cell region CELL.

The second landing plug contacts LPC2 pattern contact holes exposing the first storage node contacts SNC1 by patterning the third interlayer insulating layer 15 of the cell region CELL by a photolithography process, and forming contact holes. A conductive film, for example, a polysilicon film, may be formed on the entire surface of the substrate, and the conductive film formed outside the contact hole may be removed.

Although not shown, a spacer may be further formed on the side surfaces of the contact holes before forming the conductive layer. As the spacer, a nitride film-based material may be used. The thickness of the spacer may range from 10 to 50 microns.

Referring to FIG. 5H, the third, second, and first interlayer insulating layers 15, 14, and 13 of the cell region CELL, the capping layer 12, and the third and second regions of the peripheral region PERI may be formed by a photolithography process. The substrate 10 between the drains D located in the even-numbered columns of the cell region CELL and the gates 200 of the peripheral region PERI by patterning the second interlayer insulating layers 15 and 14 and the gate insulating layer 20. To form contact holes exposing).

Next, a conductive film, such as a polysilicon film, is formed on the entire surface including the contact holes, and the second bit line contacts BLC2 are formed in the cell region CELL by removing the conductive film formed outside the contact hole, and the peripheral region PERI. The third bit line contacts BLC3 are formed in the gap.

Since the second bit line contacts BLC2 are not connected to the drains D located in the odd-numbered column, but are connected to the drains D located in the even-numbered column, the number of second bit line contacts BLC2 is a conventional bit. Half the number of line contacts.

In the embodiment shown in the drawings, the second landing plug contacts LPC2 and the second and third bit line contacts BLC2 and BLC3 are formed by separate processes, but may be formed at the same time.

Referring to FIG. 5I, the first bit is connected to the second bit line contacts BLC2 on the third interlayer insulating layer 15 of the cell region CELL and extends in the same direction as the first bit lines BL1. A third bit line BL2 disposed between the lines BL1 and connected to the third bit line contacts BLC3 on the third interlayer insulating layer 15 of the peripheral region PERI The bit line BL3 is formed.

The second bit lines BL2 are connected to drains D positioned in even-numbered columns through second bit line contacts BLC2. For this purpose, the second bit lines BL2 are formed in even-numbered columns. Therefore, the number of second bit lines BL2 is half the number of conventional bit lines, and the distance between the second bit lines BL2 is twice the size of the conventional bit lines.

Next, a fourth interlayer insulating layer 16 covering the second and third bit lines BL2 and BLC3 is formed on the cell region CELL and the peripheral region PERI. An oxide film-based material may be used as the fourth interlayer insulating film 16.

Subsequently, a planarization process, for example, a CMP process, may be performed to remove a step generated in the fourth interlayer insulating layer 16 due to the second and third bit lines BL2 and BL3.

Thereafter, the second interlayer insulating layer 16 penetrates through the fourth interlayer insulating layer 16 of the cell region CELL and has a predetermined width W2 on the other side facing the one side of the second landing plug contacts LPC2 adjacent to the second bit lines BL2. The second storage node contacts SNC2 are formed to be connected to a portion of the second landing plug contacts LPC2 in an offset state.

Since the distance between the second bit lines BL2 is twice as large as the conventional size, general photolithography is performed without forming the second storage node contacts SNC2 on the second bit line BL2 in a self-aligned contact (SAC) method. It forms using a process.

That is, the second storage node contacts SNC2 may be patterned by the fourth interlayer insulating layer 16 by a photolithography process so as to face the other side of the second landing plug contacts LPC2 adjacent to the second bit lines BL2. Contact holes exposing a portion of the second landing plug contacts LPC2 and a portion of the third interlayer insulating layer 15 adjacent thereto, and a conductive film, eg, a polysilicon layer, is formed on the entire surface including the contact hole Then, the conductive film formed outside the contact hole is removed to form.

Although not shown, a spacer may be further formed on the side surfaces of the contact holes before forming the conductive layer. As the spacer, a nitride film-based material may be used. The thickness of the spacer may range from 10 to 50 microns.

Since the second storage node contacts SNC2 are formed to be shifted from the other side of the second landing plug contact LPC2 farthest from the second bit lines BL2 by a predetermined width W2, the second storage node contacts SNC2. And the distance D2 between the second bit lines BL2 is maximized.

In this case, the width W2 of the second storage node contact SNC2 deviated from the other sides of the second landing plug contacts LPC2 may be 1/2 to 1 times the width of the second bit line BL2.

Thereafter, the capacitor 100 is formed by stacking the storage node 17, the dielectric layer 18, and the plate electrode 19 on the second storage node contact SNC2.

On the other hand, in the above-described embodiment, the bit lines are formed in the cell region CELL as the other arrays and not in the peripheral region PERI as the column arrays, but the bit lines are formed in both the cell region CELL and the peripheral region PERI. Can also be formed in a parallel arrangement. To this end, the gate 200 of the peripheral region PERI is formed before the first bit lines BL1 of the cell region CELL, and the third bit line BL3 is divided into a plurality of rows to divide the third bit of the odd-numbered column. The lines BL3 are formed together when the first bit line BL1 is formed in the cell region CELL, and the third bit lines BL3 of even-numbered columns are formed in the cell region CELL. Can be formed together.

As described above in detail, the bit lines are formed in different layers in different arrays to increase the distance between the bit lines, and form a storage node contact for connecting the substrate and the capacitor to each layer by using the landing plug contact. The gap between the storage node contact and the bit line can be maximized. Therefore, the capacitance between the bit line and the storage node is reduced by 1/5 to 1/10 as compared with the conventional art.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

 FIG. 2 is a cross-sectional view taken along the line II ′ and II-II ′ of FIG. 1.

3A to 3J are plan views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4A through 4J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

5A through 5J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

<Description of main parts of drawing>

BL1, BL2: first and second bit lines

SNC1, SNC2: 1st, 2nd Storage Node Contact

LPC1, LPC2: 1st, 2nd landing plug contact

Claims (40)

A first interlayer insulating film formed on the substrate; First bit lines extending in one direction on the first interlayer insulating film; A second interlayer insulating film covering the first bit lines; A third interlayer insulating film formed on the second interlayer insulating film; Second bit lines extending in the one direction on the third interlayer insulating layer and disposed between the first bit lines; A fourth interlayer insulating film covering the second bit lines; First landing plug contacts connected to the substrate through the first interlayer insulating film; A first storage node penetrating the second interlayer insulating layer and connected to a portion of the first landing plug contacts in a state of being offset by a predetermined width from the other side of the first landing plug contacts adjacent to the first bit lines; Contacts; Second landing plug contacts penetrating the third interlayer insulating film and connected to the first storage node contacts; and A second storage node penetrating the fourth interlayer insulating layer and connected to a portion of the second landing plug contacts in a state of being offset by a predetermined width from the other side of the second landing plug contacts adjacent to the second bit lines; Contacts; A semiconductor device comprising a. The method of claim 1, First bit line contacts penetrating the first interlayer insulating layer to connect the substrate and the first bit lines; and Second bit line contacts penetrating the third, second and first interlayer insulating layers to connect the substrate and the second bit lines; A semiconductor device further comprising. The method of claim 1, And said second and fourth interlayer insulating films comprise an oxide film. The method of claim 1, And a spacer between the first landing plug contacts and the first interlayer insulating layer. The method of claim 1, And a spacer between the first storage node contacts and the second interlayer dielectric layer. The method of claim 1, And a spacer between the second landing plug contacts and the third interlayer insulating layer. The method of claim 1, And a spacer between the second storage node contacts and the fourth interlayer insulating layer. Forming a first interlayer insulating film on the substrate in the cell region; Forming first landing plug contacts penetrating the first interlayer insulating film and connected to the substrate; Forming first bit lines extending in one direction on the first interlayer insulating film; Forming a second interlayer insulating film covering the first bit lines; A first storage node penetrating the second interlayer insulating layer and connected to a portion of the first landing plug contacts in a state of being offset by a predetermined width from the other side of the first landing plug contacts adjacent to the first bit lines; Forming contacts; Forming a third interlayer insulating film on the second interlayer insulating film; Forming second landing plug contacts penetrating through the third interlayer insulating layer and connected to the second storage node contacts; Forming second bit lines on the third interlayer insulating layer and disposed in the one direction and disposed between the first bit lines; Forming a fourth interlayer insulating film covering the second bit lines; and A second storage node penetrating the fourth interlayer insulating layer and connected to a portion of the second landing plug contacts in a state of being offset by a predetermined width from the other side of the second landing plug contacts adjacent to the second bit lines; Forming contacts; Method of manufacturing a semiconductor device comprising a. The method of claim 8, And the second and fourth interlayer insulating films are formed of an oxide film. The method of claim 8, After forming the second storage node contacts, And forming a capacitor on the second storage node contacts. The method of claim 8, Forming the first landing plug contacts, Patterning the first interlayer insulating layer by a photolithography process to form contact holes exposing a portion of the substrate; Forming a conductive film on the entire surface including the contact holes; and Removing conductive layers formed outside the contact holes; Method of manufacturing a semiconductor device comprising a. The method of claim 11, And forming a spacer on side surfaces of the contact holes before forming the conductive layer. The method of claim 8, The forming of the first storage node contacts may include: A portion of the first landing plug contacts and the first interlayer adjacent to the second interlayer insulating layer may be patterned by a photolithography process, the second landing plug contacts including the other side facing one side of the first landing plug contacts adjacent to the first bit lines. Forming contact holes exposing a portion of the insulating film; Forming a conductive film on the entire surface including the contact holes; and Removing conductive layers formed outside the contact holes; Method of manufacturing a semiconductor device comprising a. The method of claim 13, And forming a spacer on side surfaces of the contact holes before forming the conductive layer. The method of claim 8, Forming the second landing plug contacts, Patterning the third interlayer dielectric layer by a photolithography process to form contact holes exposing the first storage node contacts; Forming a conductive film on the entire surface including the contact holes; and Removing conductive layers formed outside the contact holes; Method of manufacturing a semiconductor device comprising a. The method of claim 15, And forming a spacer on side surfaces of the contact holes before forming the conductive layer. The method of claim 8, The forming of the second storage node contacts may include: Patterning the fourth interlayer insulating layer by a photolithography process so that a portion of the second landing plug contacts including the other side of the second landing plug contacts adjacent to the second bit lines is opposite to the third landing layer; Forming contact holes exposing a portion of the insulating film; Forming a conductive film on the entire surface including the contact holes; and Removing conductive layers formed outside the contact holes; A method for manufacturing a semiconductor device comprising the. The method of claim 17, And forming a spacer on side surfaces of the contact holes before forming the conductive layer. The method of claim 8, In the forming of the first landing plug contacts, further forming first bit line contacts penetrating the first interlayer insulating layer under the first bit line and connected to the substrate. . The method of claim 8, After forming the second landing plug contacts, forming second bit line contacts connected to the substrate through the third, second, and first interlayer insulating layers under the second bit lines. A method for manufacturing a semiconductor device comprising the. The method of claim 20, And the second bit line contacts are formed together when the bit line contacts are formed in a peripheral region outside the cell region. The method of claim 21, The second bit line contacts may form contact holes by etching the third, second and first interlayer insulating layers of the cell region together when the bit line contact holes are formed in a peripheral region outside the cell region. And embedding a conductive film in the bit line contact holes in a peripheral region to fill the contact holes in the cell region together when the bit line contacts are formed. The method of claim 8, And forming second bit line contacts connected to the substrate through the third, second, and first interlayer insulating layers under the second bit lines when the second landing plug contact is formed. Manufacturing method. The method of claim 8, And the first bit lines are formed together when the gate is formed in a peripheral region outside the cell region. The method of claim 24, The first bit line is formed by extending the gate conductive layer to the cell region when the gate conductive layer is formed in the peripheral region and patterning the gate conductive layer of the peripheral region to pattern the gate conductive layer formed in the cell region when the gate is formed. Method for manufacturing a semiconductor device, characterized in that formed. The method of claim 8, And the second bit lines are formed together when the bit lines are formed in the peripheral region outside the cell region. The method of claim 26, The second bit lines may be formed by extending the bit line conductive layer to the cell region when the bit line conductive layer is formed in the peripheral region, and patterning the bit line conductive layer of the peripheral region to form the bit line conductive layer. A method of manufacturing a semiconductor device, characterized in that formed by patterning the bit line conductive film together. Forming a first interlayer insulating film on the substrate in the cell region and in the peripheral region; Forming first landing plug contacts penetrating the first interlayer insulating film and connected to the substrate of the cell region; Removing the first interlayer dielectric layer in the peripheral region; Forming and patterning a conductive film on the cell region and the peripheral region to form first bit lines extending in one direction on the first interlayer insulating layer of the cell region and forming gates on the substrate of the peripheral region; ; Forming a second interlayer insulating film on the cell region and the peripheral region; Penetrating the second interlayer insulating layer of the cell region and being connected to a portion of the first landing plug contacts in a state of being offset by a predetermined width from the other side opposite to one side of the first landing plug contacts adjacent to the first bit lines; Forming first storage node contacts; Forming a third interlayer insulating film on the cell region and the peripheral region; Forming second landing plug contacts connected to the first storage node contacts through a third interlayer insulating film of the cell region; Forming and patterning a conductive film on the cell region and the peripheral region to form second bit lines extending in the one direction and disposed between the first bit lines on the third interlayer insulating film of the cell region; Forming third bit lines on the third interlayer insulating film in the peripheral region; Forming a fourth interlayer insulating film on the cell region and the peripheral region; and Penetrate the fourth interlayer insulating layer of the cell region and be connected to a portion of the second landing plug contacts in a state of being offset by a predetermined width from the other side of the second landing plug contacts adjacent to the second bit lines; Forming second storage node contacts; Method of manufacturing a semiconductor device comprising a. The method of claim 28, Forming the first landing plug contacts, Patterning the first interlayer dielectric layer by a photolithography process to form contact holes exposing a portion of the substrate in the cell region; Forming a conductive film on the entire surface including the contact holes; and Removing conductive layers formed outside the contact holes; Method of manufacturing a semiconductor device comprising a. The method of claim 29, And forming a spacer on side surfaces of the contact holes before forming the conductive layer. The method of claim 28, The forming of the first storage node contacts may include: A portion of the first landing plug contacts and the first interlayer adjacent to the second interlayer insulating layer may be patterned by a photolithography process, the second landing plug contacts including the other side facing one side of the first landing plug contacts adjacent to the first bit lines. Forming contact holes exposing a portion of the insulating film; Forming a conductive film on the entire surface including the contact holes; and Removing conductive layers formed outside the contact holes; Method of manufacturing a semiconductor device comprising a. 32. The method of claim 31, And forming a spacer on a side of the contact hole before forming the conductive layer. The method of claim 28, Forming the second landing plug contacts, Patterning the third interlayer dielectric layer by a photolithography process to form contact holes exposing the first storage node contacts; Forming a conductive film on the entire surface including the contact holes; and Removing conductive layers formed outside the contact holes; Method of manufacturing a semiconductor device comprising a. The method of claim 33, And forming a spacer on a side of the contact hole before forming the conductive layer. The method of claim 28, The forming of the second storage node contacts may include: Patterning the fourth interlayer insulating layer by a photolithography process so that a portion of the second landing plug contacts including the other side of the second landing plug contacts adjacent to the second bit lines is opposite to the third landing layer; Forming contact holes exposing a portion of the insulating film; Forming a conductive film on the entire surface including the contact holes; and Removing conductive layers formed outside the contact holes; Method of manufacturing a semiconductor device comprising a. 36. The method of claim 35, And forming a spacer on a side of the contact hole before forming the conductive layer. The method of claim 28, After forming the second storage node contacts, And forming capacitors on the second storage node contacts. The method of claim 28, Forming the first landing plug contacts, the first bit line contact penetrating the first interlayer insulating layer under the first bit line of the cell region and connected to the substrate of the cell region and the peripheral region, respectively; Method for manufacturing a semiconductor device, characterized in that further forming. The method of claim 28, The substrate of the cell region and the peripheral region through the third, second, and first interlayer insulating layers under the second and third bit lines before forming the second bit lines and the third bit lines; And forming second and third bit line contacts respectively connected to the second and third bit line contacts. The method of claim 28, A second and a second penetrating through the third, second, and first interlayer insulating layers under the second and third bit lines when the second landing plug contact is formed; And forming 3 bit line contacts.

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