KR20100117193A - Apparatus for channel encoding in a broadband wireless communication system - Google Patents

Abstract

PURPOSE: An apparatus for channel encoding in a broadband wireless communication system is provided to shorten channel coding time by CTC(Convolutional Turbo Code) coding a certain number of pairs of data bits at the same time. CONSTITUTION: A randomizer(210) parallely randomizes a certain number of multiple data bit pairs. A convolution turbo codes encoder(220) stores a plurality of randomized data bit pairs in a plurality of storage area at the same time. The convolution turbo code encodes a data bit pair by using an internal interleaving read address for the storage areas.

Description

Apparatus for channel encoding in a broadband wireless communication system

The present invention relates to a channel encoding apparatus of a broadband wireless communication system, and more particularly, to a channel encoding apparatus using a convolutional turbo code (hereinafter referred to as 'CTC').

Recently, development of broadband wireless communication systems such as a portable Internet system and a WiMAX (Wireless Interoperability for Microwave Access) system for providing high-speed wireless communication services in a wide area are actively underway.

In such a broadband wireless communication system, an error of correcting an error by using an error correction algorithm is transmitted at the transmitting end by attaching an additional bit for error correction to the information bit at the transmitting end in order to improve reliability in high-speed data transmission. Correction technique is used.

In a broadband wireless communication system, a channel encoding apparatus using a turbo code, which is one of such forward error correction (FEC) technologies, is used. In particular, a channel encoding apparatus using a CTC capable of encoding data bits faster than that of a general turbo code method that encodes one data bit every clock has been widely used.

1 is a block diagram schematically illustrating a structure of a conventional CTC encoder.

As shown in FIG. 1, the CTC encoder 100 included in the conventional channel encoding apparatus 100 sequentially encodes an input data bit pair by RSC (Recursive Systematic Convolutional) encoding and outputs the first internal encoder 110. And an internal interleaver 120 for interleaving and outputting a bit pair, and a second internal encoder 130 for receiving and outputting the interleaved data bit pair by RSC encoding.

The conventional CTC encoder 100 performs CTC encoding on an L bit data bit string in units of data bit pairs each including two data bits. At this time, in the CTC encoder 100, the L / 2 clock, the first internal encoder 110 and the second internal required to store the L bit data bit string in a memory (not shown) for interleaving through the internal interleaver 120. The L / 2 clock required to detect the register initial value of the encoder 130 and the L / 2 clock required for the first internal encoder 110 and the second internal encoder 130 to encode and output a pair of data bits are required. .

On the other hand, in recent broadband wireless communication systems, a high speed data transmission technology for multimedia services such as games and video is required. However, when the CTC encoding is performed in units of two data bits using the conventional CTC encoder 100, a long time is required for the CTC encoding process. Therefore, there is a need for a channel encoding apparatus capable of high-speed processing of channel encoding for large data compared to a conventional channel encoding apparatus.

Accordingly, an object of the present invention is to provide a channel encoding apparatus capable of shortening the channel encoding processing time for input data in a broadband wireless communication system.

Another object of the present invention is to provide a channel encoding apparatus capable of simultaneously performing CTC encoding on a plurality of data bit pairs in a broadband wireless communication system.

For this purpose, a channel encoding apparatus of a broadband wireless communication system according to an embodiment of the present invention includes a randomizer for randomizing a plurality of input data bit pairs in parallel by a predetermined number; A convolutional turbo code (CTC) encoder for simultaneously storing the plurality of randomized pairs of data in a plurality of storage regions and then encoding the data using an internal interleaving read address for the plurality of storage regions; An interleaver for interleaving the encoded plurality of data bit pairs according to a predetermined scheme; And a packet generator for generating the interleaved plurality of data bit pairs into a data packet.

The convolutional turbo code (CTC) encoding apparatus according to another embodiment of the present invention simultaneously encodes a plurality of input data bit pairs by a predetermined number according to a predetermined code rate, thereby performing a first parity bit pair. A first encoder for generating a; An input memory configured to store the input plurality of data bit pairs in a plurality of storage areas at the same time by the predetermined number; An internal interleaver for simultaneously generating internal encoded read addresses corresponding to the number of the plurality of storage regions and internally interleaving pairs of data bits stored in each storage region corresponding to the internal encoded read addresses; A second encoder configured to simultaneously encode the internal interleaved data bit pairs by the predetermined number according to a predetermined code rate to generate a second parity bit pair; Among the plurality of data bit pairs, the same systematic bit pair as the predetermined number of data bit pairs, the first parity bit pair, and the second parity bit pair are merged to output output data corresponding to the predetermined number. Generating merger; And an output memory configured to simultaneously store the generated output data by the predetermined number.

According to an embodiment of the present invention, in the broadband wireless communication system, channel encoding time may be shortened by simultaneously performing CTC encoding on a certain number of pairs of data bits during channel encoding on input data bits.

In addition, according to an embodiment of the present invention, the channel encoding time can be shortened by simultaneously processing CTC internal interleaving for a predetermined number of data bit pairs during CTC encoding.

In addition, according to an embodiment of the present invention, an efficient CTC internal interleaving can be performed by simplifying an operation procedure of an equation for obtaining a memory address value for the CTC internal interleaving.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments. For reference, in the following description, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention are omitted.

2 is a block diagram showing the structure of a channel encoding apparatus according to an embodiment of the present invention.

As shown in FIG. 2, the channel encoding apparatus 200 according to the embodiment of the present invention includes a randomizer 210, a CTC encoder 220, an interleaver 230, and a packet generator 240.

The randomizer 210 receives a data bit string in units of FEC blocks and randomizes the input data bit string in units of a plurality of data bit pairs. For reference, the data bit pair includes K data bits (in the embodiment of the present invention, 'K = 2' is shown as an example).

At this time, the randomizer 210 randomizes a plurality of data bit pairs in parallel every clock, and outputs the randomized plurality of data bit pairs to the CTC encoder 220 simultaneously.

For example, randomizer 210 randomizes eight bits of data (ie, four pairs of data bits) in parallel in one clock. At this time, four data bit pairs are randomized in parallel to the first clock and simultaneously output to the CTC encoder 220, and the next four data bit pairs are randomized in parallel to the second clock to the CTC encoder 220. Output at the same time. In this manner, randomizer 210 randomizes N data bit pairs for N / 4 clocks and outputs them to CTC encoder 220.

The CTC encoder 220 encodes a plurality of data bit pairs input from the randomizer 210 at a specific coding rate and then outputs the encoded data bits to the interleaver 230. In this case, the CTC encoder 220 generates a systematic bit pair, a first parity bit pair, and a second parity bit pair from the input data bit pair. Here, the systematic bit pairs are data bit pairs as they are input original data bit pairs, the first parity bit pair is a data bit pair obtained by encoding the original data bit pair at a specific code rate, and the second parity bit pair is the original data bit pair. A data bit pair obtained by encoding a data bit pair internally by the CTC encoder 220 at a specific code rate.

In particular, the CTC encoder 220 according to an embodiment of the present invention simultaneously encodes a plurality of pairs of data bits input from the randomizer 210 by a predetermined number (hereinafter, referred to as 'first number') to determine a first number. The output data is generated, and the generated first number of output data are simultaneously stored in the storage area.

In detail, the CTC encoder 220 simultaneously stores the plurality of data bit pairs input from the randomizer 210 in the internal storage area by the first number in the order of input. The CTC encoder 220 generates a read address of the internal storage area corresponding to the first number every clock, obtains a pair of data bits stored in the storage area corresponding to the read address of the internal storage area, by a first number. The second parity bit pair is generated by encoding at the same time. In addition, the CTC encoder 220 generates a first parity bit pair by simultaneously encoding a plurality of data bit pairs input from the randomizer 210 by the first number in the order of input.

For example, when four data bit pairs are simultaneously input from the randomizer 210 every clock, the CTC encoder 220 divides the four data bit pairs into four storage areas. For reference, the four storage areas are composed of a plurality of storage spaces each having a different storage address. The CTC encoder 220 simultaneously generates one read address, that is, four read addresses for each storage area, and simultaneously obtains and encodes a pair of data bits from storage spaces of four storage areas corresponding to the read address. do. By doing so, CTC encoder 220 generates a second parity bit pair for four data bit pairs per clock.

In addition, the CTC encoder 220 according to an embodiment of the present invention uses a first number using a systematic bit pair, a first parity bit pair, and a second parity bit pair generated corresponding to the first number of data bit pairs. Generate output data for. Thereafter, the CTC encoder 220 outputs the generated first number of output data to the interleaver 230.

In this case, the CTC encoder 220 merges the corresponding systematic bit pair, the first parity bit pair, and the second parity bit pair for each data bit pair of the first number of data bit pairs to form a first number. Generate output data for. For reference, the CTC encoder 220 simultaneously stores the generated first number of output data in the storage area, and then outputs the output data stored in the storage area corresponding to the read address generated from the interleaver 230. Will output

The interleaver 230 receives the output data from the CTC encoder 220 and interleaves (rearranges) the output data to the packet generator 240. At this time, the interleaver 230 generates a read address for the storage area in which the output data encoded by the CTC encoder 220 is stored. The interleaver 230 activates a storage area corresponding to the generated read address, and interleaves the output data by obtaining output data stored in the activated storage area and outputting the output data to the packet generator 240.

The packet generator 240 punches and repetitions the number of bits to correspond to a specific code rate for the data output from the interleaver 230 to generate a sub packet.

Hereinafter, a CTC encoder and a CTC encoding method according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 5.

3 is a block diagram showing the structure of a CTC encoder according to an embodiment of the present invention.

First, as shown in FIG. 3, the CTC encoder 220 according to the embodiment of the present invention may include a first CTC internal encoder 221, a CTC input memory 222, a CTC internal interleaver 223, and a second CTC internal encoder ( 224, a merger 225, and a CTC output memory 226.

The first CTC internal encoder 221 generates a plurality of first parity bit pairs by simultaneously encoding a plurality of data bit pairs input from the randomizer 210 at each clock by using a Recursive Systematic Convolutional (RSC) code. . The first CTC internal encoder 221 outputs the generated plurality of first parity bit pairs to the merger 225.

In FIG. 3, the first to fourth data bit pairs A ₀ B ₀ , in which the first CTC internal encoder 221 is input from the randomizer 210 to the first clock. A ₁ B _1, A ₂ B _2, A ₃ B ₃ ) are simultaneously encoded, and as a result of the encoding, four first parity bit pairs (Y1 ₀ W1 ₀ , Y1 ₁ W1 _1, Y1 ₂ W1 _2, Y1 ₃ W1) ₃ ) output. That is, N / 4 clocks are required for the first CTC internal encoder 221 to encode N data bit pairs.

The CTC input memory 222 includes a plurality of memory banks each having a different storage address, and stores a plurality of data bit pairs inputted every clock in the plurality of memory banks. 3 illustrates that the CTC input memory 222 includes memory bank 0 201, memory bank 1 202, memory bank 2 203, and memory bank 3 204.

Specifically, as shown in FIG. 3, the first to fourth data bit pairs A ₀ B ₀ , input from the randomizer 210. A ₁ B _1, A ₂ B _{2, and} A ₃ B ₃ ) are stored in one clock divided into four memory banks of the CTC input memory 222. In this case, in FIG. 3, an input first data bit pair A ₀ , B ₀ ) is stored in memory bank 0 201, and the second pair of data bits A ₁ ,. B ₁ ) is stored in memory bank 1 202, and the third data bit pair A ₂ , B ₂ ) is stored in memory bank 2 203, and the fourth data bit pair A ₃ , B ₃ ) is simultaneously stored in memory bank 3 204. In this manner, the CTC input memory 222 has N data bit pairs A ₀ B ₀ , during N / 4 clock. A ₁ B _1, A ₂ B _2, A ₃ B ₃ , ...... A _N-1 B _N-1 ) are stored sequentially.

The CTC input memory 222 outputs a pair of data bits stored in a storage area corresponding to a read address generated from the CTC internal interleaver 223 to the second CTC internal encoder 224.

For reference, in the channel encoding apparatus 200 according to the embodiment of the present invention, the randomizer 210 randomizes a plurality of data bit pairs and outputs a predetermined number of them, and at the same time, outputs the random number from the randomizer 210. Pairs of data bits are stored in the CTC input memory 222. At this time, the number of data bit pairs simultaneously output from the randomizer 210 is set equal to the number of memory banks of the CTC input memory 222. Therefore, when four data bit pairs are output from the randomizer 210 and the CTC input memory 222 is composed of four memory banks, N data bit pairs are stored in the CTC input memory 222 to be processed. It takes / 4 clock.

The CTC internal interleaver 223 generates a read address corresponding to the number of memory banks of the CTC input memory 222 every clock, and obtains data bit pairs stored in the storage space of the memory bank corresponding to the generated read address. Outputs simultaneously to the 2 CTC internal encoder 224.

Specifically, the CTC internal interleaver 223 according to the embodiment of the present invention includes a read address generator 231 and a multiplexer 232.

The read address generator 231 generates read addresses corresponding to the number of memory banks of the CTC input memory 222 and transmits the read addresses to the CTC input memory 222 through the multiplexer 232. Then, the storage space of the memory bank corresponding to the read addresses is activated, and the data bit pairs stored in the activated storage space are output to the second CTC internal encoder 224.

Specifically, the read address generator 231 according to the embodiment of the present invention uses the modulo operation as shown in Equation 1 below to read initial value of the read address for each memory bank of the CTC input memory 222. Create

[Equation 1]

for j = 0,… N-1

switch (j mod 4):

case 0: P (j) = (P 0 · j + 1) mod N

case 1: P (j) = (P 0 · j + 1 + N / 2 + P 1) mod N

case 2: P (j) = (P 0 · j + 1 + P 2) mod N

case 3: P (j) = (P 0 · j + 1 + N / 2 + P 3) mod N

In Equation 1, j is a constant value corresponding to the number of N data bit pairs, and P ₀ , P ₁ , P ₂ , and P ₃ are preset constant values. In this case, the read address generator 231 performs a P (j) operation by selecting a corresponding case among four cases (case 0, case 1, case 2, and case 3) based on the remaining value obtained by dividing j by 4. do. That is, the read address generator 231 divides the j value by 4, if the remaining value is 1, case 1, if the remaining value is 2, case 2, if the remaining value is 3, case 3, and if the remaining value is 4, P ( j) Perform a function operation. As such, the read address generator 231 generates the j-th read address initial value by calculating the P (j) function of the corresponding case.

For example, the read address generator 231 according to an embodiment of the present invention assigns four variable j values per counter to Equation 1 to simultaneously perform P (j) operations for four cases, As a result, four initial read address values are generated simultaneously. For reference, the four variable j values are set to constant values that are sequentially increased by '1'. As described above, four P (j) functions are calculated by simultaneously assigning four variable j values to Equation 1, thereby performing N P (j) operations during N / 4 counters.

Then, the read address generator 231 generates read address information corresponding to each memory bank of the CTC input memory 222 by using the generated read address initial value. Thereafter, the read address generator 231 transmits the generated read address information to the multiplexer 232.

In this case, the read address information includes a storage area selection value for selecting a memory bank of the CTC read memory 222 and a read address value matching the storage address of each storage area. At this time, the read address generator 231 generates a storage area selection value based on the lower 2 bit value of the generated read address initial value, and generates a read address value based on the quotient of dividing the read address initial value by four. do.

For example, in FIG. 3, the read address generator 231 generates four read address initial values through a P (j) function operation of four cases of Equation 1 when the value of the variable j is 1 to 4. P (0), P (1), P (2), and P (3), which are read address information of the memory bank of the CTC input memory 222, are generated using the generated four read address initial values. It was shown.

The multiplexer 232 receives a plurality of read address information from the read address generator 231 at the same time, and a pair of data bits stored in each memory bank of the CTC input memory 222 corresponding to the plurality of input read address information is second. Control to output to the CTC internal encoder 224.

At this time, the multiplexer 232 controls to output after performing a bit exchange for some data bit pairs according to a predetermined rule. In detail, the multiplexer 232 exchanges the order of the data bits in the case of the data bit pair obtained using the read address value generated using the specific j value among the variable j values. For reference, the specific j value may be set to an even or odd number value among consecutive N j values.

In addition, in FIG. 3, the multiplexer 232 receives read address information P (0), P (1), P (2), and P (3) generated from the read address generator 231, and receives a CTC read memory ( From 222, four data bit pairs are controlled to be output.

The second CTC internal encoder 224 simultaneously generates a plurality of second parity bit pairs by simultaneously encoding a plurality of data bit pairs input from the CTC input memory 222 every clock using an RSC code. The second CTC internal encoder 224 outputs the generated plurality of second parity bit pairs to the merger 225 at the same time.

In FIG. 3, the second CTC internal encoder 224 simultaneously encodes the first to fourth data bit pairs input from the CTC input memory 222 to the first clock, and as a result of the encoding, four second parity bit pairs. (Y2 ₀ W2 ₀ , Y2 ₁ W2 _1, Y2 ₂ W2 _2, Y2 ₃ W2 ₃ ) was shown to be output. That is, it takes N / 4 clock for the second CTC internal encoder 224 to encode N data bit pairs.

The merger 225 may include a plurality of first parity bit pairs and a plurality of second parity bit pairs input from the first CTC inner encoder 221 and the second CTC inner encoder 224, and the input from the randomizer 210. Generating a plurality of output data by merging a plurality of systematic bit pairs that are identical to the original data bit pair. The merger 225 stores the plurality of output data in a plurality of storage areas of the CTC output memory 226.

In FIG. 3, four output data generated by merging four systematic bit pairs and first and second parity bit pairs through a merger 225 (A ₀ B ₀ Y 1 ₀ Y 2 ₀ W 1 ₀ W 2) ₀ , A ₁ B ₁ Y1 ₁ Y2 ₁ W1 ₁ W2 ₁ , A ₂ B ₂ Y1 ₂ Y2 ₂ W1 ₂ W2 ₂ , A ₃ B ₃ Y1 ₃ Y2 ₃ W1 ₃ W2 ₃ ) are each in the CTC output memory 226. It is shown dividedly stored in the storage area.

The CTC output memory 226 is composed of a plurality of memory banks each having a plurality of storage addresses, and simultaneously stores a plurality of data bit pairs inputted every clock in the plurality of memory banks.

3 shows that the CTC output memory 226 includes memory bank 0 261, memory bank 1 262, memory bank 2 263, and memory bank 3 264. The CTC output memory 226 transmits the output data stored in the storage address of the corresponding storage area to the interleaver 230 according to the read address generated from the interleaver 230.

As such, the CTC encoder 220 according to the embodiment of the present invention may include an N / 4 clock required to store N data bit pairs input from the randomizer 210 in four memory banks of the CTC input memory 222. N / 4 clock required for encoding the data bit pairs in the first internal CTC encoder 221 and the second internal CTC encoder 224, and N / 4 clock required for outputting the output data generated through the merger 225. This takes

Meanwhile, FIG. 3 shows that the read address generator 231 generates N read address initial values by performing P (j) operations of four cases shown in Equation 1 during the N / 4 counter. However, the read address generator 231 according to the embodiment of the present invention may generate the read address initial value more efficiently by using the algorithm shown in FIG. 4.

4 is a flowchart illustrating a read address generation method according to an embodiment of the present invention. 5 is a diagram illustrating a parameter table of a CTC internal interleaver according to an embodiment of the present invention.

In FIG. 4, when the N data bit pairs are input, the first four read address initial values are generated using Equation 1, and the generated first four read address initial values and a preset reference increment value (JN: Jumping Number) are generated. (Hereinafter referred to as 'JN') shows how to generate the remaining N-4 read addresses. For reference, JN is a constant value to be applied to read address initial values after the first four read address initial values.

In FIG. 5, the first four read addresses using the result of calculating the P (j) function of Equation 1 with respect to N j values by the read address generator 231 according to the embodiment of the present invention. Initial values and parameter table resulting from generating the JN are shown.

5 shows a parameter table in which the size of the FEC block used in the broadband wireless communication system according to the embodiment of the present invention is divided into 12 pieces. For reference, the initial read address initial value and the JN of each of the 12 FEC block sizes are matched and stored in the parameter table.

First, the initial read address initial values P0, P1, P2, and P3 are set using Equation 1 (S410).

At this time, in the method of generating a read address according to an embodiment of the present invention, a plurality of read addresses corresponding to the number of storage regions in which N data bit pairs are divided and stored are simultaneously generated.

For example, in order to simultaneously acquire four data bit pairs divided and stored in four storage areas, four read addresses per counter are generated simultaneously.

Specifically, in step S410, four initial read address initial values are set when the counter value i is 0, and the four initial read address initial values are set to P of each case when j values are 0 to 3 in Equation 1 above. j) It is calculated through a function operation.

For reference, when a 48-bit FEC block, that is, 24 data bit pairs (N = 24) is input, the four initial read address initial values are P0 = 1, P1 = 18, as shown in the parameter table of FIG. It has a value of P2 = 11 and P3 = 4. A storage area selection value for selecting a corresponding storage area among a plurality of storage areas is generated based on each of the lower two bit values of the four initial read address initial values, and each of the four initial read address initial values is 4. The quotient divided by is generated as the read address value.

Next, a second read address initial value is set by adding preset JNs to preset read address initial values (hereinafter, referred to as 'first read address initial value') (S420).

In FIG. 4, four initial read address values set through Equation 1 are represented as PO (i), P1 (i), P2 (i), and P3 (i). In addition, the JN is a predetermined constant value using a result obtained by sequentially substituting the values of the variable j corresponding to the number N of the entire data bit pairs input into Equation 1 above.

Specifically, if the value of j increasing by the value of '1' is substituted into each of the four case-specific P (j) function operations of Equation 1, the four P (j) function operation result values may be obtained. have. In this manner, the regular increase value JN may be calculated from the result values obtained by sequentially substituting the N j values into the P (j) function operation of Equation 1 above. For example, FIG. 5 shows that when the value of N is 24, the value of JN corresponding to the result of calculating Equation 1 for the values of 24 variables j is 20. In this way, by calculating the value of each JN corresponding to the remaining 11 N values and storing 12 JN values in the parameter table, the read address initial values after the initial read address initial value can be quickly set.

Meanwhile, the second read address initial value obtained by adding JN to the first read address initial value does not exceed the number N of the entire data bit pairs.

Therefore, after step S420, it is determined whether the second read address initial value has a value greater than or equal to the number N of all data bit pairs, and when the second read address initial value has the above value, the second read address initial value has a value less than or equal to the N value. An operation process generates a third read address initial value (S430).

In detail, as a result of the determination in step S430, for the second read address initial value having the value equal to or greater than the N value among the second read address initial values, the third read address initial value is limited to the N value, and the second read address is generated. For the second read address initial value having a value less than the N value among the initial values, a third read address initial value as the second read address initial value set in step S420 is generated.

Then, a plurality of read address information is generated by outputting an initial value of a third read address having a value equal to or less than the N value (S440).

In this case, the read address information includes a storage area selection value and a read address value. Here, a storage area selection value for selecting a corresponding storage area among a plurality of storage areas is generated based on each of the lower 2 bits of the third read address initial value, and the quotient of dividing the third read address initial value by 4 is read. Create with address value.

For example, referring to the parameter table of FIG. 5, if there are 24 total data bit pairs input (N = 24), the preset initial read address value (that is, the first read address initial value) is P0 = 1, P1. = 18, P2 = 11, P3 = 4, and the next read address initial value (that is, the second read address initial value) is P0 = 21, P1 = 38, P2 = 31, P3 = 24, i. Second read address initial value when = 1). At this time, since P1, P2, and P3 of the initial values of the second read address each have a value of N or more, the operation of subtracting the N value is performed. As a result, the initial value of the third read address when i = 1 has a value of P0 = 21, P1 = 14, P2 = 7, P3 = 0. Then, the lower two bits of the third read address initial values are '01' at P0, '10' at P1, '11' at P2, and '00' at P3, so that P0, P1, P2, and P3 are each A storage area selection value for selecting the first to fourth storage areas. In addition, the quotients of the third read address initial value divided by 4 are 5 at P0, 3 at P1, 1 at P2, and 0 at P3, respectively, and the shares are read address values. In this way, read address information for 24 data bit pairs can be generated during the N / 4 counter (i.e. i = 6).

Then, it is determined whether the counter i value corresponding to the generated plurality of read address information exceeds the (N / 4) -1 value (S450).

In this case, the read address generation method according to the embodiment of the present invention shows that four read addresses are generated at the same time. Therefore, the P (j) functions of the four cases of Equation 1 correspond to the number of pairs of input data bits (N). ) Is divided by 4 times. That is, the counter i is counted for a number of times from 0 to (N / 4-1).

On the other hand, if the value of i is less than the (N / 4) -1 value in step S450 to return to step S420 to increase the value of i '1' to calculate the equation (1). On the other hand, when the value of i exceeds the value of (N / 4) -1 in step S450, the read address generation operation ends.

As described above, according to the method of generating a read address according to an embodiment of the present invention, the initial read address initial value and the JN value generated by performing Equation 1 in advance are stored as a parameter table, and the parameter table is used. Generates a read address initial value corresponding to the total number of input data bit pairs. In this way, the calculation process of Equation 1 can be reduced, and thus the read address information can be generated more quickly and simply.

6 is a flowchart illustrating a channel encoding method according to an embodiment of the present invention.

As shown in FIG. 6, in the channel encoding method according to the embodiment of the present invention, a plurality of data bit pairs inputted first are randomized in parallel (S610).

Then, CTC encoding is simultaneously performed on the plurality of randomized data bit pairs (S620).

Specifically, in the CTC encoding, the first parity bit pair and the input data bit pair obtained by encoding the same systematic bit pair and the input data bit pair using the RSC code for the plurality of data bit pairs. After interleaving, a second parity bit pair encoded using an RSC code is generated. In this case, the systematic bit pair and the first and second parity bit pairs are merged to generate a plurality of CTC-coded data bit pairs (ie, output data).

Then, interleaving is performed on the plurality of CTC-coded data bit pairs (S630).

Finally, the plurality of interleaved data bit pairs are generated as data packets (S640). At this time, unnecessary bits are deleted (punched) or repeated in the plurality of interleaved data bit pairs to generate the data packet.

FIG. 7 is a flowchart for explaining a CTC encoding step in FIG. 6.

As shown in FIG. 7, in the CTC encoding step according to the embodiment of the present invention, first, a plurality of M randomized pairs of data bits that are input first are simultaneously stored in the input storage region (S710). At this time, M data bit pairs among all input data bit pairs are simultaneously stored in M storage areas.

Thereafter, M read addresses for the M storage areas are simultaneously generated, and M read data pairs are sequentially interleaved from M bit pairs stored at an address corresponding to M read addresses among the stored data bit pairs (S720).

In operation S730, M input data pairs are encoded by M to generate M first parity bit pairs, and the M interleaved M data bit pairs are encoded to generate M second parity bit pairs (S730).

Thereafter, M output data is generated by performing merge processing on the M data bit pairs, the M first parity bit pairs, and the M second parity bit pairs identical to the input original data bit pairs (S740). ).

The generated M output data are divided and stored in M output storage areas at the same time (S750).

As such, the output data stored in the output storage area are then interleaved from the output data stored in the storage area corresponding to the read address generated from the interleaver.

Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art to which the present invention pertains can implement the present invention in other specific forms without changing the technical spirit or essential features, The examples are to be understood in all respects as illustrative and not restrictive.

In addition, the scope of the present invention is specified by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention. Should be interpreted as

1 is a block diagram schematically illustrating a structure of a conventional CTC encoder.

2 is a block diagram showing the structure of a channel encoding apparatus according to an embodiment of the present invention.

3 is a block diagram showing the structure of a CTC encoder according to an embodiment of the present invention.

4 is a flowchart illustrating a read address generation method according to an embodiment of the present invention.

5 is a diagram illustrating a parameter table of a CTC internal interleaver according to an embodiment of the present invention.

6 is a flowchart illustrating a channel encoding method according to an embodiment of the present invention.

FIG. 7 is a flowchart for explaining a CTC encoding step in FIG. 6.

Claims (11)

In the channel encoding apparatus of a broadband wireless communication system, A randomizer for randomizing a plurality of input data bit pairs in parallel by a predetermined number; A convolutional turbo code (CTC) encoder for simultaneously storing the plurality of randomized pairs of data in a plurality of storage regions and then encoding the data using an internal interleaving read address for the plurality of storage regions; An interleaver for interleaving the encoded plurality of data bit pairs according to a predetermined scheme; And And a packet generator for generating the plurality of interleaved data bit pairs as data packets. The method of claim 1, The CTC encoder is configured to simultaneously interleave the first parity bit pair and the plurality of data bit pairs internally by a predetermined number of data bit pairs among the plurality of data bit pairs according to a predetermined code rate. And performing encoding by generating a systemic bit pair identical to the predetermined number of data bit pairs among the encoded second parity bit pair and the plurality of data bit pairs. The method of claim 1, The CTC encoder sets an internal interleaving address initial value corresponding to the predetermined number, generates an internal interleaving address initial value based on the internal interleaving address initial value and a predetermined reference increment value, and the internal interleaving address initial value. And generating the internal interleaving read address by using the SRS. The method of claim 3, The internal interleaving address initial value is set to a value less than a value obtained by dividing the number of the plurality of data bit pairs by the predetermined number. The method of claim 1, The CTC encoder is configured to simultaneously set an internal interleaving address initial value by a predetermined number, and generate the internal interleaving read address using the internal interleaving address initial value. The method of claim 1, The CTC encoder generates a storage area selection value by using a lower 2 bit value of an internal interleaving address initial value, and uses a quotient obtained by dividing the internal interleaving address initial value by a constant value corresponding to the number of the plurality of storage areas. And generating an internal interleaving read address value for the selected storage area. A first encoder generating a first parity bit pair by simultaneously encoding a plurality of input data bit pairs by a predetermined number according to a predetermined code rate; An input memory configured to simultaneously store the input plurality of data bit pairs in the plurality of storage areas by the predetermined number; An internal interleaver for simultaneously generating internal encoded read addresses corresponding to the number of the plurality of storage regions and internally interleaving pairs of data bits stored in each storage region corresponding to the internal encoded read addresses; A second encoder configured to simultaneously encode the internal interleaved data bit pairs by the predetermined number according to a predetermined code rate to generate a second parity bit pair; Among the plurality of data bit pairs, the same systematic bit pair as the predetermined number of data bit pairs, the first parity bit pair, and the second parity bit pair are merged to output output data corresponding to the predetermined number. Generating merger; And And a convolutional turbo code (CTC) encoding apparatus including an output memory configured to simultaneously store the generated output data by the predetermined number. The method of claim 7, wherein The internal interleaver may sequentially output the predetermined number of data bit pairs stored in a storage area corresponding to the internal encoding read address among the data bit pairs stored in the input memory to the second encoder. . The method of claim 7, wherein The internal interleaver sets a predetermined number of internal interleaving read address initial values, and generates the internal interleaving read address based on the initial interleaved read address initial value and a predetermined reference increment value. .  10. The method of claim 9, And the internal interleaver generates storage area selection values for the plurality of storage areas based on values of each of the lower two bits of the initial value of the internal interleaving read address. 10. The method of claim 9, The internal interleaver generates the quotient obtained by dividing the initial interleaving read address initial value by a constant value corresponding to the number of the plurality of storage areas as a read address value corresponding to the plurality of storage areas, respectively. Device.

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