JP2010004100A - Transmission data generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce storage parts for respective processing stages, which store the data of a transport block, and to shorten the generation time of transmission data, relating to a transmission data generator for generating the transmission data of the high-speed uplink packet access (HSUPA) of mobile communication. <P>SOLUTION: When performing the processing of repetition, enable signals to be supplied to a CRC computing element 1-2 and an encoder 1-3 are turned to a low level by a rate matching part 1-4 to stop the operations, and the data right before are repeatedly outputted. In order to arrange the transmission data in the final transmission order after interleaving and store them in the storage part, an interleaver 1-5 for generating the write address of the storage part 1-6 is made to activate the operation of generating the address, and the transmission data are stored in the address. When performing the processing of puncture, the interleaver 1-5 is made to stop the operation of generating the address, and the storage of the transmission data to the storage part 1-6 is stopped. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a transmission data generation apparatus, and in particular, is applied to generation of transmission data for high-speed uplink packet access (HSUPA) in mobile communication. High-speed uplink packet access (HSUPA) is a technique for increasing the uplink data communication speed from a mobile terminal to a base station in W-CDMA (Wideband Code Division Multiple Access) mobile communication.

  This transmission data generation device is mounted on a portable terminal or the like, and is provided with a redundancy check code such as CRC calculation, turbo coding, etc. for transmission data such as an HSUPA channel (E-DPDCH: Enhanced Dedicated Physical Data Channel). Encoding, rate matching (bit correction), and interleaving are performed to generate final transmission data.

  FIG. 7 shows a configuration of a conventional HSUPA transmission data generation apparatus. A conventional HSUPA transmission data generation apparatus includes a buffer 7-1 for storing transport block data, a CRC calculator 7-2 for assigning a CRC (Cyclic Redundancy Check) code of a redundancy check code to the data, and a CRC code. A first storage unit (RAM) 7-3 that holds the data to which the CRC code is assigned, an encoder 7-4 that turbo-codes the data after the CRC code is added, and a first code that holds the turbo-coded data. 2 storage unit (RAM) 7-5, rate matching (bit correction) unit 7-6, third storage unit (RAM) 7-7 holding the data after rate matching, and interleaving processing Interleaver 7-8 is provided.

  FIG. 8 shows a timing chart of conventional transmission data generation. (A) of the figure shows the processing time for adding the CRC code by the CRC calculator 7-2, and this processing time is the time for adding the CRC code 24 bits to the data size TrBk of the transport block.

  FIG. 7B shows the processing time of turbo coding by the encoder 7-4. The processing time is calculated by adding systematic bits, parity 1 bits and parity 2 bits to the data (TrBk + 24) after the CRC code is added. It is time to generate a turbo code and add 12 tail bits.

  FIG. 5C shows the rate matching (bit collection) processing time by the rate matching (bit collection) unit 7-6. Rate matching (bit correction) is processing for matching the bit rate of transport block data with the bit rate of the physical channel, and the processing time is the processing time for the data size Ndata of the final transmission data.

  FIG. 4D shows the processing time for interleaving by the interleaver 7-8. Interleaving is a process of rearranging the order of transmission data in units of transport blocks, and the processing time is the processing time for the final transmission data data size Ndata.

  In the conventional transmission data generation, after all the data of the transport block has been assigned the CRC code, the turbo code is applied to all the data of the transport block to which the CRC code is assigned, and the turbo code is generated. After the encoding process is completed, rate matching (bit correction) is performed on all data in the transport block. After the rate matching (bit correction) process is completed, all data in the transport block is processed. On the other hand, the interleaving process is performed serially.

  For this reason, it is necessary to provide storage units (RAM) 7-3, 7-5, and 7-7 that temporarily store all the data of the transport blocks that have undergone each process at each stage. Therefore, the processing time corresponding to the sum of the processing times required for each processing is required. That is, the processing time of (TrBk + 24) × 4 + 12 + Ndata × 2 + α (processing delay time) is required.

In the generation of transmission data, many processes are required for the encoding process of arithmetic codes, and high-speed processing is required. Reducing the processing time required to encode arithmetic codes by performing parallel processing on the audend register and code code register (HSUPA channel) is a big problem as described in Patent Document 1 below. It has become.
Japanese Patent Laid-Open No. 08-46520

  The present invention sequentially assigns a redundancy check code to transmission data, encodes, performs rate matching, and performs interleaving in transmission data generation, and stores each process of storing data of a transport block that is an interleaving processing unit The purpose is to reduce the storage unit for each stage and to shorten the generation time of the transmission data.

  The disclosed transmission data generation apparatus sequentially adds a redundancy check code to high-speed uplink packet access (HSUPA) transmission data for mobile communication, encodes, performs rate matching, and performs interleaving. The apparatus simultaneously executes the redundancy check code assignment, the encoding, the rate matching, and the interleaving processing simultaneously on the data bits of one transport block that is the interleaving processing unit. Is.

  According to this transmission data generation device, the storage unit for storing data output from the encoder through the CRC operation and the storage unit for interleaving can be used together. The number of storage units to be stored can be reduced, and the apparatus can be reduced in size and cost. In addition, the processing time from CRC calculation to interleaving can be greatly shortened, and the power consumption can be reduced.

  FIG. 1 shows a configuration example of the disclosed transmission data generation apparatus. In the figure, 1-1 is a buffer for storing transport block data, 1-2 is a CRC calculator for adding a CRC code as a redundancy check code to the transport block data, and 1-3 is after the CRC code is added. An encoder that performs turbo coding or the like on the data of 1-4, and rate matching that performs repetition or puncture processing in order to match the bit rate of the transport block data to the bit rate of the physical channel (Bit collection) part.

  1-5 is an interleaver for rearranging the order of the transmission data, and the data output from the encoder 1-3 so that the transmission data after the interleaving is stored in the storage unit (RAM) 1-6 in the order of transmission. Is written to the storage unit (RAM) 1-6. A storage unit (RAM) 1-6 stores final transmission data.

  This transmission data generating apparatus uses an enable signal that activates / stops the operations of the CRC computing unit 1-2 and the encoder 1-3 for each data bit of the transport block by the rate matching (bit correction) unit 1-4. Are controlled and their operation / stop is controlled, whereby CRC calculation, encoding, and rate matching (bit correction) processing are simultaneously performed in parallel.

  Further, the rate matching (bit correction) unit 1-4 sends an enable signal for activating / stopping the operation of the interleaver 1-5 for each data bit of the transport block to control the operation / stopping, As a result, rate matching (bit correction) processing and interleaving processing are simultaneously performed in parallel.

  When performing repetition processing as rate matching, the rate matching (bit collection) unit 1-4 stops sending enable signals to the CRC calculator 1-2 and the encoder 1-3 at the repetition execution timing. And stop those operations. At that time, an enable signal is supplied to the interleaver 1-5, and the operation of the interleaver 1-5 is activated.

  In this way, the previous output data is repeatedly output from the CRC calculator 1-2 and the encoder 1-3, and the repeated output data output from the encoder 1-3 is generated by the interleaver 1-5. Are stored in the storage unit (RAM) 1-6 according to the addresses. At this time, the interleaver 1-5 generates an address in the order in which the interleaving is performed, and gives the address as a write address to the storage unit (RAM) 1-6.

  When puncturing is performed as rate matching, the rate matching (bit correction) unit 1-4 sends an enable signal as usual to the CRC calculator 1-2 and the encoder 1-3 at the puncturing timing. To activate these operations. At that time, the sending of the enable signal to the interleaver 1-5 is stopped, the operation of the interleaver 1-5 is stopped, the generation of the write address of the storage unit (RAM) 1-6 is stopped, and the storage unit ( RAM) Writing to 1-6 is stopped.

  By doing so, the transmission data output from the encoder 1-3 at the time of puncturing is not generated by the interleaver 1-5 being stopped, and is not stored in the storage unit (RAM) 1-6. That is, the transmission data is punctured. By performing such control, it is possible to perform processes from CRC code assignment to interleaving in parallel.

  2 and 3 show timing charts of transmission data generation by the transmission data generation apparatus. FIG. 2 is a timing chart when the repetition process is performed. (A) of the figure shows the processing timing of CRC code assignment, (b) shows the processing timing of encoding, (c) shows the processing timing of rate matching (bit correction), and (d) shows the interleaving process. The processing timing is shown.

  In the encoding process timing of FIG. 2B, the gap portion indicates that the encoding operation is stopped and the repetition process is being performed. It should be noted that at the timing when the encoding operation stops, the operation of the CRC code assigning process of FIG.

  Further, the rate matching (bit collection) process is continuously performed as shown in FIG. 5C, and the interleaving process is performed according to the rate matching (bit collection) process as shown in FIG. Sequentially with a slight delay. The transmission data generation processing time when the repetition processing is performed is a time obtained by adding a processing delay time α to the processing time corresponding to the number of data size bits (Ndata) of the final transmission data.

  FIG. 3 is a timing chart when the puncturing process is performed. (A) of the figure shows the processing timing of CRC code assignment, (b) shows the processing timing of encoding, (c) shows the processing timing of rate matching (bit correction), and (d) shows the interleaving process. The processing timing is shown.

  When the puncturing process is performed, the encoding process is a continuous operation as shown in FIG. Further, rate matching (bit correction) processing is continuously performed as shown in FIG. However, the interleaving process stops at the timing when the puncture target bit appears, as indicated by a gap in FIG.

  The processing time for generating transmission data when puncturing is performed is that a turbo code of systematic bits, parity 1 bit, and parity 2 bits is generated in the data (TrBk + 24) after the CRC code is added, and a 12-bit tail is generated. This is the time obtained by adding the processing delay α to the processing time of the data size (TrBk + 24) × 3 + 12 to which bits are added.

  As described above, the transmission data generation processing time by the transmission data generation apparatus varies depending on the rate matching processing contents (repetition or puncture). However, in any case, the processing time is significantly reduced as compared with the conventional transmission data generation shown in FIG.

  4 and 5 show timing charts of operation examples when performing repetition and puncture processing, respectively. Here, it is assumed that the number of encoded data bits is 24 bits. FIG. 4A shows the rate matching execution timing. In the example of FIG. 4, the repetition process is executed at the high level, and in the example of FIG. 5, the puncture process is executed at the high level. Show.

  4 (b), 5 (c), and 5 (d) represent enable signals that enable encoding of systematic bits, parity 1 bits, and parity 2 bits of the encoder, respectively, and are at high levels, respectively. It sometimes shows that it is enabled. Similarly, the following enable signals are also enabled at the high level.

  (E), (f), (g), and (h) in the figure represent a CRC calculator enable signal, CRC calculator output data, encoder enable signal, and encoder output data for systematic bits, respectively. ing.

  (I), (j), (k), and (l) in the figure represent a CRC calculator enable signal, a CRC calculator output data, an encoder enable signal, and an encoder output data, respectively, for one parity bit. ing.

  (M), (n), (o), and (p) in the figure represent a CRC calculator enable signal, a CRC calculator output data, an encoder enable signal, and an encoder output data for 2 bits of parity, respectively. ing.

  (Q) in the figure shows a data series obtained by selecting and extracting output data bits of systematic bits, parity 1 bits, and parity 2 bits for each transmission data from the encoder in this order. 'S' indicates a systematic bit, 'P1' indicates a parity 1 bit, and 'P2' indicates a parity 2 bit.

  (R) of the figure shows an interleave enable signal, and (s) shows an address output generated by the interleaver. (T) indicates a storage enable signal of the storage unit, and the storage enable signal is a signal obtained by delaying the interleave enable signal in accordance with the address output timing of the interleaver, and the storage enable signal is “1” (high level). At this time, the output data of the encoder is stored at the address generated by the interleaver.

  Since the encoder outputs three data (systematic bit, parity 1 bit, parity 2 bit) for one input data, in order to operate the CRC calculator and the encoder in parallel, The CRC calculation may be performed once every three clocks. Accordingly, when the repetition process is not performed, the enable signal ‘1’ (high level) is given to the CRC calculator and the encoder once every three clocks.

  When performing repetition, the operation of the CRC computing unit and the encoder is stopped, and repetition processing is realized by repeatedly outputting the previous data bits for the number of data bits to be repeated. For this purpose, the timing for setting the enable signal of the CRC calculator to ‘1’ is delayed by the number of data bits for which repetition processing is performed, and the encoder enable signal is set to ‘0’ (low level). Since the encoder output data is all valid (previous data is output from the encoder), the address generation is always performed with the interleaver enable signal set to '1', and the encoder output data is output to the generated address. Is stored.

  In the operation example of FIG. 4, the CRC enable signal e1 for systematic bits is set to “0” by the repetition enable signal a1, the CRC calculator output data is stopped, the encoder enable signal g1 is set to “0”, The previous data S is output as the encoder output data.

  Therefore, the 9th systematic bit S becomes the repeated output data of the 6th systematic bit S in the data sequence of the encoder output of (q) by the repetition enable signal a1.

  In the operation example of FIG. 4, the CRC computing unit enable signal m2 for parity 2 bits is set to “0” by the repetition enable signal a2, the CRC computing unit output data is stopped, and the encoder enable signal o2 is set to “0”. The previous data P2 is output as encoder output data.

  Therefore, according to the repetition enable signal a2, the 17th parity 2 bit P2 becomes the repeated output data of the 14th parity 2 bit P2 in the data sequence of the encoder output of (q).

  Similarly, with the repetition enable signal a3, the CRC calculator enable signal e3 for systematic bits is set to “0”, the CRC calculator output data is stopped, the encoder enable signal g3 is set to “0”, and the encoder output data is set. The previous data S is output as follows.

  Therefore, the 21st systematic bit S becomes the repeated output data of the 18th systematic bit S in the data sequence of the encoder output of (q) by the repetition enable signal a3.

  FIG. 5 shows an operation example of the puncturing process. When performing the puncturing process, it is only necessary to delete unnecessary data bits (puncture target data bits) from the encoder output data. An enable signal “1” is given to the CRC calculator and encoder every three clocks.

  However, in accordance with the timing when the data bits to be punctured are output from the encoder and stored in the storage unit, the generation of the storage address is stopped by setting the interleaver enable signal to '0', and the storage enable signal to the storage unit is Stop writing the encoder output data to the storage unit as '0'. As a result, transmission data is not stored in the storage unit (RAM), and puncture processing is realized.

  In the operation example of FIG. 5, the interleave enable signal r1 is set to '0' in accordance with the timing at which the fifth parity 2 bit P2 (puncture target bit) shown in (q) is output by the puncture enable signal a1. Is stopped, the storage enable signal t1 to the storage unit is set to '0', and writing of the encoder output data (fifth P2) to the storage unit is stopped. As a result, transmission of encoder output data (fifth P2) is thinned out.

  Similarly, the generation of the storage address is stopped by setting the interleave enable signal r2 to “0” at the timing when the 13th parity 1 bit P1 (puncture target bit) shown in (q) is output by the puncture enable signal a2. Then, the storage enable signal t2 to the storage unit is set to “0”, and writing of the encoder output data (13th P1) to the storage unit is stopped. As a result, transmission of encoder output data (13th P1) is thinned out.

  Similarly, the generation of the storage address is stopped by setting the interleave enable signal r3 to '0' in accordance with the timing when the 20th parity 2 bit P2 (puncture target bit) shown in (q) is output by the puncture enable signal a3. Then, the storage enable signal t3 to the storage unit is set to “0”, and writing of the encoder output data (20th P2) to the storage unit is stopped. As a result, transmission of encoder output data (20th P2) is thinned out.

  FIG. 6 shows an example of address generation by the interleaver. In order to perform the processes from the CRC calculation to the interleaving in parallel, it is necessary to generate an address for storing the output data of the encoder in the storage unit (RAM) while performing each process.

  In the example shown in FIG. 6, systematic bit, parity 1 bit and parity 2 bit data (0, 1, 2, 3, 3 ', 4, 4', 5, 6, 7, 8,...) Are output. Here, data with an apostrophe such as “3 ′” and “4 ′” indicate that it is the same data as the previous data output by the repetition. The systematic bit, parity 1 bit, and parity 2 bit data are distinguished by applying different pattern patterns in the enclosing frame.

  In order to perform interleaving on the data output in the order shown in FIG. 6 (a), as shown in FIG. 6 (b), for example, the first from left to right in a two-dimensional array of 4 columns × 9 rows. Assume that the rows are arranged in order from the ninth row. The number of rows 9 is a value obtained by dividing the data size by the number of columns 4.

  In order to perform interleaving on the data in the array shown in FIG. 6B, for example, the data is exchanged in the second column and the third column, and rearranged in the array shown in FIG. And the data rearranged in the order shown in FIG. 4D is obtained by sequentially reading the data in the array shown in FIG. 4C from the first to the fourth column from the top to the bottom.

  In order to perform the above interleaving, an address for storing data output in the order shown in FIG. 6A in the storage unit (RAM) is generated as follows. First, a counter (cnt) that counts up in synchronization with the data output of the encoder, a column counter (cnt% 4) that outputs the remainder obtained by dividing the count value of the counter (cnt) by the number of columns 4, and a counter ( A row counter (cnt / 4) that outputs a quotient obtained by dividing the count value of (cnt) by the number of columns 4 is prepared.

  The column counter (cnt% 4) can be a column number (in this case, 4) base counter that counts up each time a clock signal synchronized with the data output of the encoder is input. The row counter (cnt / 4) can be a counter that counts up each time a clock synchronized with the data output of the encoder is input by the number of columns (in this case, 4).

  The interleaver uses the count values of the column counter (cnt% 4) and the row counter (cnt / 4), and when the count value of the column counter (cnt% 4) is 0, the count of the row counter (cnt / 4) A value obtained by adding the value of the product of the number of rows 9 and 0 (in this case 9 × 0 = 0) to the value is output as an address value.

  When the count value of the column counter (cnt% 4) is 1, the product of the number of rows 9 and 2 (in this case 9 × 2 = 18) is added to the count value of the row counter (cnt / 4). The added value is output as an address value. When the count value of the column counter (cnt% 4) is 2, the product of the number of rows 9 and 1 (in this case 9 × 1 = 9) is added to the count value of the row counter (cnt / 4). The added value is output as an address value.

  When the count value of the column counter (cnt% 4) is 3, the product of the number of rows 9 and 3 (9 × 3 = 27 in this case) is added to the count value of the row counter (cnt / 4). The added value is output as an address value. By performing such address generation, storage unit (RAM) storage addresses (0, 18, 9, 27, 1, 19, 10, 28,...) Shown in FIG. .

  Then, the data output in the order shown in FIG. 6A is stored in the storage unit (RAM) using the address generated by the above method as the write address. For example, data 3 'is stored at address 1, data 4 is stored at address 19, data 4' is stored at address 10, and data 5 is stored at address 28. At the time of transmission, it is possible to transmit the interleaved data by sequentially reading the data from address 0 of the storage unit (RAM) 1-6.

Here, the rate matching process will be described in detail. Rate matching calculates rate matching parameters e _ini , e _plus , and e _minus based on the data size of the transport block and the number of physical channel bits,
-If the number of physical channel bits ≤ transport block data size, punctures to reduce the transmission data bits by extracting the transmission data bits,
-If the number of physical channel bits> transport block data size,
The same transmission data bit is repeatedly transmitted, and repetition is performed to increase the transmission data bit (see TS25.212 V6.10.04.8.4, 4.2.7.5).

For example, the output data bits from the turbo encoder are
X ₁ , Z ₁ , Z ' ₁ , X ₂ , Z ₂ , Z' ₂ , X ₃ , Z ₃ , Z ' ₃ , X ₄ , Z ₄ , Z' ₄ , X ₅ , Z ₅ , Z ' ₅
If
In the case of repetition, assuming that Z ₁ , Z ′ ₂ , Z ₃ , X ₄ , and X ₅ are the repetition target bits, the output data after rate matching processing is
X ₁ , Z ₁ , Z ' ₁ , X ₂ , Z ₁ , Z' ₂ , X ₃ , Z ₂ , Z ' ₂ , X ₄ , Z ₃ , Z' ₃ , X ₄ , Z ₃ , Z ' ₄ , X ₅ , Z ₄ , Z ' ₅ , X ₅ , Z ₅
It becomes.

In the case of puncturing, assuming that Z ′ ₁ , Z ₃ , and X ₅ are puncturing target bits, the output data after rate matching processing is
X ₁ , Z ₁ , X ₂ , Z ₂ , Z ' ₂ , X ₃ , Z' ₃ , X ₄ , Z ₄ , Z ' ₄ ,, Z ₅ , Z' ₅
It becomes. A configuration example of the turbo encoder is shown in FIG.

  In the conventional rate matching process, the data output from the CRC calculator and the encoder is temporarily stored in the storage unit (RAM), and the rate matching process is performed when the encoder output data is read from the storage unit (RAM). In the case of repetition, data of the same address is read as many times as the number of repetitions, and in the case of puncture, reading of data from the storage unit (RAM) is skipped.

  On the other hand, the rate matching process of this disclosure performs enable control for the encoder or interleaver and controls the operation / stop of the encoder or interleaver in accordance with the rate matching processing content (repetition or puncture). A rate matching process is performed.

  In the case of repetition, the operation of the encoder is stopped, and the previous output data from the encoder is retained and stored repeatedly in the interleaving storage unit (RAM). In the case of puncturing, the rate matching process is realized by invalidating the data bits to be punctured output from the encoder without storing them in the storage unit (RAM) for interleaving and removing them from the subsequent processing targets.

  By doing so, the storage unit (RAM) for storing data output from the encoder through the CRC operation and the storage unit (RAM) for interleaving can be shared by the same storage unit (RAM). As compared with the above, the memory (RAM) can be reduced and the apparatus can be downsized. Also, by performing the CRC operation, encoding, and interleaving processing in parallel, the processing time from the CRC operation to the interleaving can be significantly shortened compared to the conventional one.

It is a figure which shows the structural example of the transmission data generation apparatus of an indication. It is a timing chart in the case of implementing a repetition process. It is a timing chart in the case of implementing a puncturing process. It is a timing chart of the example of operation in the case of performing a repetition process. 6 is a timing chart of an operation example in the case of performing puncturing processing. It is a figure which shows an example of the address generation by an interleaver. It is a figure which shows the structure of the conventional HSUPA transmission data generation apparatus. It is a figure which shows the timing chart of the conventional transmission data generation. It is a figure which shows the structural example of a turbo encoder.

Explanation of symbols

1-1 Transport Block Data Storage Buffer 1-2 CRC Calculator 1-3 Encoder 1-4 Rate Matching (Bit Correction) Unit 1-5 Interleaver 1-6 Storage Unit (RAM)

Claims (4)

In a transmission data generation apparatus that assigns a redundancy check code to a high-speed uplink packet access transmission data of mobile communication, encodes, performs rate matching, and performs interleaving.
The transmission characterized in that the redundancy check code assignment, the encoding, the rate matching, and the interleaving process are executed in parallel for the data bits of one transport block that is the interleaving processing unit. Data generator. When performing a repetition process when performing the rate matching, stop the operation of applying and encoding the redundancy check code, repeatedly output the immediately preceding data,
The transmission data generation apparatus according to claim 1, wherein when performing puncturing when performing the rate matching, the operation of assigning and encoding the redundancy check code is activated. For the interleaving processing unit that generates the write address of the storage unit so that the transmission data is arranged and stored in the storage unit in the final transmission order after interleaving,
When performing the repetition process when performing the rate matching, activate the operation of generating the address of the interleaving processing unit, and store the transmission data at the generated address,
The puncturing process is performed when the rate matching is performed, the address generation operation of the interleaving processing unit is stopped, and the storage of the transmission data in the storage unit is stopped. The transmission data generation device according to 1 or 2. When performing a repetition process when performing the rate matching, the operation of applying and encoding the redundancy check code is stopped, the previous data is repeatedly output,
In order to store the transmission data in the storage unit in the final transmission order after interleaving, the interleaving processing unit that generates the write address of the storage unit is activated to generate the address. Store the transmission data at the address,
When performing puncturing when performing the rate matching, the interleaving processing unit stops the address generation operation and stops storing the transmission data in the storage unit. The transmission data generation device according to claim 1.

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