JP2003188737A - Interleave processing method and interleave processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely perform rearranging processing with a little hardware quantity by reducing a memory required for an interleaver to be used for a turbo- code or a LDPC code. <P>SOLUTION: The interleave processor is composed of a rearrangement table TB written with rearrangement data for assigning a non-interleaved data symbol sequence or data bit sequence to a prescribed block while defining a partial sequence dividing an interleaved sequence for each of the prescribed number of symbols or the prescribed number of bits relatively to an inputted data symbol sequence or a data bit sequence as a block, a selector SL for assigning the non-interleaved data symbol sequence or the data bit sequence to the prescribed block according to the rearrangement data applied by the rearrangement table TB and a plurality of memory blocks MB1-MB64 to be assigned with the data symbol sequence or the data bit sequence via the selector SL. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is included in a coding unit and a decoding unit of a signal processing apparatus that performs parity distributed transmission using a parallel concatenated convolutional (Turbo) code or an interleave used for a code similar thereto. The present invention relates to an interleave processing method and an interleave processing device applied to an interleaver.

[0002]

2. Description of the Related Art In recent years, for example, research in the field of communication such as mobile communication and deep space communication, the field of broadcasting such as terrestrial wave or satellite digital broadcasting, and the field of information recording for recording / reproducing information via a recording medium have been rapidly conducted. Although progress is being made, along with this, research on code theory is being actively conducted for the purpose of improving the efficiency of error correction coding and decoding.

The performance of the error correction code is evaluated by the decoding error rate, the coding rate, the calculation amount, etc., and the Shannon limit given by the so-called Shannon's channel coding theorem is known as a typical logical limit thereof. There is.

As a code showing a property close to the Shannon limit, a parallel convolutional convolutional (Turbo) code or a low density parity check (LDPC: Low Density Pr) is used.
The "ity Check" code is drawing attention.

These codes are turbo codes and LDPC codes, which are generated by a coding device constructed by combining a plurality of convolutional encoders and an interleaver. Then, on the decoding side, a plurality of soft-outputs (soft-outpu)
A final decoding result can be obtained by exchanging information about the input data between the decoding circuits outputting t).

The basic structure of the turbo code encoder and decoder will be described with reference to FIGS.

As shown in FIG. 3, a turbo code encoder 10 is provided.
In 0, the input data series is input to the first encoder 101, and the first encoder 101 forms the first parity bit string PB1. The data sequences are simultaneously rearranged by the interleaver 102 and input to the second encoder 103, and the second encoder 103 produces a second parity bit string PB2. The first and second parity bit strings PB1 and PB2 are multiplexed while being decimated by the first multiplexer 104, and the second
Is multiplexed with the input data sequence by the multiplexer 5 and transmitted to the communication path.

Also, the turbo code encoder 200 is shown in FIG.
, The first decoder 201, the interleaver 202, the second decoder 203, and the deinterleaver 2
It is composed of 04.

The first decoder 201 performs a decoding process on the input received data sequence and outputs the decoding results of various information symbols and their reliability information. Interleaver 20
2 performs rearrangement processing on the input received data series and the reliability information obtained by the first decoder 201. The second decoder 203 is the first decoder 20.
1 to decode the reliability information by using the reliability information and the received data sequence supplied from the interleaver 202, and the first information via the deinterleaver 204.
To the decoder 201.

In the second and subsequent iterations, the first decoder 201 executes the decoding process using the reliability information from the second decoder 203 and the received data sequence. After repeating this several times to ten or more times, the final decision is made and the final decoding result is output.

Interleaver 20 in decoder 200
The rearrangement of 2 is the same as that of the encoder 100. Decoder 20
In 0, the received data series is rearranged in addition to the reliability information series. This is because the reliability information sequence and the received data sequence are arranged in the order of the parity bit string and are matched in the order of the processing in the second decoder 203. Deinterleaver 20
4 performs a process of returning the rearrangement of the interleaver 202.

Here, the conventional interleaver used in, for example, a turbo code or an LDPC code performs only the operation of rearranging the input data series. 40
FIG. 5 shows a configuration example of the interleaver 310 and the 64/65 single parity encoding circuit 320 which rearranges the 96-bit data sequence.

The input data sequence is an interleaver 310.
, The selector 3 is divided into 4096 bits and operates according to the data of the rearrangement table 311.
12, the sorting process is performed for each 4096 bits, and the sorting process is stored in the 4096-bit memory 313.

64/65 single parity encoding circuit 3
Reference numeral 20 includes an exclusive OR circuit 321 and a latch circuit 322 that latches the output of the exclusive OR circuit 321. The input data series rearranged by the interleaver 310 is input to the exclusive OR circuit 321. 64/65 single parity code is generated by taking the exclusive OR of the input data series and the latch output of the latch circuit 322.

[0015]

By the way, in the conventional interleaver used in the turbo code or the LDPC code, the case where dedicated hardware for rearrangement is used and the table which stores the rearrangement information are used. However, each of them requires a very complicated circuit and a large circuit scale, and the cost for realizing them is great.

Further, after the rearrangement, when the number of data decreases due to puncturing or calculation, data that need not be held is held, resulting in an increase in circuit scale.

Therefore, in view of the conventional problems as described above, the object of the present invention is to reduce the memory required in the interleaver used in the turbo code or the LDPC code, and surely with a small amount of hardware. An object of the present invention is to provide an interleave processing method and an interleave processing device that can perform rearrangement processing.

[0018]

An interleaving processing method according to the present invention is a method in which an interleaved sequence is divided into a predetermined number of symbols or a number of partial sequences for an input data symbol sequence or data bit sequence. As a block, an operation of allocating a data symbol sequence or a data bit sequence before interleaving to a predetermined block is performed to substitute for an interleaving operation for an input sequence.

In the interleave processing method according to the present invention, when assigning a data symbol sequence or data bit sequence before interleaving to a predetermined block, the data assigned to the block in the past and the data to be assigned at present are used as arguments. The predetermined calculation is performed in block units.

Further, in the interleave processing method according to the present invention, in the block code used in the turbo code or a code similar thereto, the code length of the block code is the above block, and the constraint condition of the block code is assigned to the above block. I do.

The interleave processing apparatus according to the present invention is
With respect to the input data symbol series or data bit series, a partial series obtained by dividing the interleaved series by a predetermined number of symbols or bits is used as a block, and the data symbol series or data bit series before interleaving is used as a predetermined block. Through a sorting table in which sorting data for allocation is written, a selector that assigns a data symbol sequence or a data bit sequence before interleaving to a predetermined block according to the sorting data given by the sorting table, and the selector. And a plurality of memory blocks to which the data symbol sequence or the data bit sequence is assigned.

In the interleave processing device according to the present invention, the plurality of memory blocks, when allocating a data symbol sequence or a data bit sequence before interleaving to a predetermined block, data assigned to the block in the past and present allocation. Each is provided with an arithmetic means for performing a predetermined arithmetic operation performed in block units using the data to be obtained as an argument.

Further, in the interleave processing apparatus according to the present invention, in the block code used in the turbo code or a code similar thereto, the code length of the block code is set to the above block, and the constraint condition of the block code is assigned to the block. Is performed by the calculation means.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will now be described in detail with reference to the drawings.

The present invention is applied to an interleaver included in an encoding unit and a decoding unit of a signal processing device which performs parity distribution transmission using interleaving used for a turbo code or a code similar to the turbo code.

In the interleaver according to the present invention, the block accumulating described below is used instead of the interleaver used in the turbo code or a code similar thereto.
Data conversion is performed using interleaver.

That is, according to the present invention, when an interleaving operation is performed on an input data symbol sequence or data bit sequence, a partial sequence obtained by dividing the interleaved sequence into predetermined symbols or bits is blocked. The interleaved sequence is treated as a block sequence. Then, an operation of allocating the data symbol series or the data bit series before interleaving to a predetermined block (this operation is called Block
By using Accumulating Interleaving),
It is an alternative to the interleave operation for the input sequence.

Here, the case of using an interleaver for rearranging a 4096-bit data sequence is taken as an example, and at this time, an example of the configuration of the interleaver using a block accumulating interleaver is shown in FIG.

The interleaver 10 shown in FIG. 1 includes a 1-bit memory M and an exclusive OR circuit EXOR.
64 memory blocks MB1 to MB64
A selector SL for allocating the input data series to a predetermined block, and a rearrangement table TB in which rearrangement data for allocating the input data series to the predetermined block is written.

Here, the block code is 64/65.
Assume a single parity code. In 64/65 single parity block code, for 64-bit data,
A 65-bit code word is obtained by adding 1 bit of the result of the exclusive OR of all 64-bits. However, in the turbo code or the LDPC code, only 1 bit that is a parity is transmitted, and the remaining 64 bits of data are not transmitted by so-called puncturing. 4096 bit data sequence interleaved by a predetermined method
Assuming a bit sequence, for example, a partial sequence for every 64 bits is called a block. That is, the sequence after interleaving consists of 1 block (64 bits) × 64 4096 bits.

Next, the present invention will be described using a specific example of the series.

The input 4096-bit data series is defined as follows.

{A ₀ , a ₁ , a ₂ , a ₃ ,. ． ． , A
₄₀₉₅ } The result of rearranging this data series by applying the conventional interleaving method is defined as follows.

{B ₀ , b ₁ , b ₂ , b ₃ ,. ． ． , B
₄₀₉₅ } That is, the sequence {b ₀ , b ₁ , b ₂ ,
b ₃ ,. ． ． , B ₄₀₉₅ } is a data series {a ₀ , a
₁ , a ₂ , a ₃ ,. ． ． , A ₄₀₉₅ } is rearranged using a predetermined rule. In order to realize the predetermined rearrangement, the following rearrangement circuit having 4096 indexes is required.

[0035] _{a 0} from _{b 0 b 4096} index _{a 1} indicating how are sorted in the throat of bits from _{b 0 b 4096} index _{a 2} indicating how are sorted in the throat of bits from _{b 0} of _{b 4096} Index indicating which bit is rearranged: An index sequence {b ₀ , b ₁ , b ₂ , b ₃ , ... _That indicates which bit a ₄₀₉₅ is rearranged from b ₀ to b ₄₀₉₆ . ． ． , B ₄₀₉₅ }
On the other hand, when the 64/65 single parity code is applied, the data is divided every 64 bits from the beginning of the sequence, and the following calculation is performed.

C₀= (B₀+ B₁+ B_Two+ B_Three+. ． ．
+ B₆₃) Mod2 c₁= (B₆₄+ B₆₅+ B₆₆+. ． ． + B₁₂₇)
mod2 : c₆₃= (B₄₀₃₂+ B₄₀₃₃+. ． ． + B
₄₀₉₅) Mod2 That is, {c₀, C₁,. ． ． , C₆₃} Is {b₀，
b₁,. ． ． , B_{40 95}} Every 64 bits from the beginning
2 blocks for each block
Modulo addition, i.e. exclusive OR of all bits
It becomes a series of those that have been calculated. 4096 bit
Input data series {a₀, A₁, A_Two, A _Three,. ． ． , A
₄₀₉₅} For a 64-bit parity sequence
{C₀, C₁,. ． ． , C₆₃} Will be output.
It At this time, input data series {a₀, A ₁, A_Two, A
_Three,. ． ． , A₄₀₉₅}, The sequence {b₀, B
₁, B_Two, B_Three,. ． ． , B₄₀₉₅} Rearrange
And the output parity sequence {c ₀, C₁,. ． ． ，
c₆₃}, The temporary series {b₀, B₁, B
_Two, B_Three,. ． ． , B₄₀₉₅} And the memory to store
And selector circuit for 4096-bit rearrangement deleted
It is possible to reduce.

Therefore, in the present invention, the following grouping is performed. This grouping is a block in the present invention. Temporary sequences {b ₀ , b ₁ , b ₂ , b ₃ ,. ． ． , B ₄₀₉₅ } are grouped as follows for each 64 bits to which the 64/65 single parity code is applied.

{{B ₀ , b ₁ , b ₂ ,. ． ． , B ₆₃ }, {b ₆₄ , b ₆₅ ,. ． ． , B ₁₂₇ } ,. ． ． , {B ₄₀₃₂ , b ₄₀₃₃ ,. ． ． , B ₄₀₉₅ }} Name these groups as follows.

{Group0, group1 ,. ． ． , Group63} In other words, the grouping is as follows.

Group0 = {b ₀ , b ₁ ,. ． ． , B ₆₃ } Group1 = {b ₆₄ , b ₆₅ ,. ． ． , B ₁₂₇ }: Group63 = {b ₄₀₃₂ , b ₄₀₃₃ ,. ． ． , B
₄₀₉₅ } At this time, temporary rearrangement is performed as follows.

The index a ₂ indicating whether the index a ₁ to indicate whether a ₀ is sorted in Group63 throat of the block from Group0 is sorted in Group63 throat of the block from Group0 is sorted into blocks of Group63 throat from Group0 Index indicating which: a Index indicating which block of Group 0 to Group 63 is rearranged by ₄₀₉₅ Furthermore, the above 64/65 single parity code is applied to each block.

Subsequently, the interleaver 10 shown in FIG.
The operation of will be described.

When the 64/65 single parity code is applied to one block, only 1-bit parity data is actually transmitted. Therefore, it is sufficient to allocate 1-bit memory to one block. Inputting 4096-bit data is input to the allocated blocks using a table indicating which block of 64 blocks should be input. Each memory block MB1
Each of MB64 to MB64 is composed of a 1-bit memory M and an exclusive OR operation circuit EXOR. At this time, in each memory block, the exclusive OR of the data stored immediately before and the newly input data is obtained,
The data is stored again in the 1-bit memory M. With such a configuration, conventionally, it was necessary to have a memory for 4096 bits and a sorting table (12 bits × 4096), but in the present invention, a memory for 64 bits and a sorting table ( It can be realized only with 6 bits × 4096).

Conventionally, a memory was required to hold a sequence obtained by rearranging the input data sequence, but in the present invention, only a memory for holding a code sequence required for transmission is needed, which is wasteful. It has become possible to reduce the circuit cost.

Modification of the Invention In the above-mentioned embodiments, only the coding circuit has been described as an example, but a similar method can be used for the interleaver at the time of decoding.

For example, when a 64/65 single parity code is used, assuming an input data string of 4096 pieces of reliability information and grouping 65 pieces of data into one block, an operation for each block is input. It is possible to construct a block accumulating interleaver by calculating the reliability of the block using the reliability information.

The interleaver 20 in the decoder is shown in FIG.
Shows the configuration of.

The interleaver 20 shown in FIG. 2 includes 64 memory blocks MB1 to MB64 each composed of a memory for storing one reliability information and a circuit for calculating the reliability from the reliability information, and received data. A selector SL for allocating a sequence to a predetermined block and rearrangement data for allocating a received data sequence to a predetermined block are composed of a rearranged table TB.

Although the 64/65 single parity code is used in the above embodiment, the present invention can be applied to any block code.

[0050]

As described above, according to the present invention, it is possible to realize a circuit having the same function with a smaller amount of hardware as compared with the conventional interleaver.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an interleaver in an encoder according to the present invention.

FIG. 2 is a block diagram showing a configuration of an interleaver in a decoder.

FIG. 3 is a block diagram showing a basic configuration of a turbo code encoder.

FIG. 4 is a block diagram showing a basic configuration of a turbo code decoder.

FIG. 5 is a block diagram showing a configuration example of an interleaver and a 64/65 single parity encoding circuit for rearranging a 4096-bit data sequence.

[Explanation of symbols]

10, 20 Interleaver, M memory M, EXOR
Exclusive OR circuit, MB1 to MB64 memory blocks, SL selector, TB rearrangement table

Claims (6)

[Claims] 1. A data symbol sequence or a data bit sequence before interleaving, wherein a partial sequence obtained by dividing an input data symbol sequence or a data bit sequence into a predetermined number of symbols or a predetermined number of bits is used as a block. An interleaving processing method is characterized in that by substituting an interleaving operation with respect to an input sequence by performing an operation of allocating to a predetermined block. 2. When allocating a data symbol sequence or a data bit sequence before interleaving to a predetermined block, it is carried out in block units with the data assigned to the block in the past and the data to be currently assigned as arguments. The interleave processing method according to claim 1, wherein a predetermined calculation is performed. 3. A block code used in a turbo code or a code similar thereto, wherein the code length of the block code is the block, and a constraint condition of the block code is assigned to the block. 1. The interleave processing method described in 1. 4. A data symbol sequence or data bit sequence before interleaving, which is a partial sequence obtained by dividing an input data symbol sequence or data bit sequence into a predetermined number of symbols or a predetermined number of bits as a block. And a selector for allocating a data symbol sequence or a data bit sequence before interleaving to a predetermined block according to the rearrangement data given by the rearrangement table. An interleave processing device comprising: a plurality of memory blocks to which the data symbol sequence or the data bit sequence is assigned via the selector. 5. The plurality of memory blocks, when allocating a data symbol sequence or a data bit sequence before interleaving to a predetermined block, the data assigned to the block in the past and the data to be currently assigned are arguments. 5. The interleave processing apparatus according to claim 4, further comprising arithmetic means for performing a predetermined arithmetic operation performed in block units. 6. A block code used in a turbo code or code similar thereto, wherein the code length of the block code is the block, and the constraint condition of the block code is assigned to the block by the calculating means. The interleave processing apparatus according to claim 5, which is characterized in that.