KR20100098978A - Internal voltage generating circuit for semiconductor memory apparatus - Google Patents

Abstract

PURPOSE: An internal voltage generating circuit is provided to secure the stability of a substrate bias voltage by controlling the abnormal increase of the substrate bias voltage. CONSTITUTION: A high voltage detector(110) outputs a high voltage enable signal according to a high voltage level. A driving controller outputs a driving control signal according to a substrate bias voltage level. A high voltage oscillator(120) determines a driving state according to the driving control signal. A high voltage pump(130) generates a high voltage in response to the pulse signal of the high voltage oscillator. The driving controller comprises a level detecting part which outputs a comparison signal according to the substrate bias voltage level and a determining part which enables the driving control signal according the comparison signal and the high voltage enable signal.

Description

Internal Voltage Generating Circuit for Semiconductor Memory Apparatus

The present invention relates to a semiconductor memory device, and more particularly to an internal voltage generation circuit of a semiconductor memory device.

Semiconductor memory devices use various levels of power, and power can be divided into external power and internal power.

That is, the external power source is a power source supplied from a device on which the semiconductor memory device is mounted, and the internal power source is a power source generated by converting the external power source internally. At this time, the levels of each power supply are shown in the order of high voltage (hereinafter, VPP), external supply voltage (hereinafter, VDD), external ground voltage (hereafter, VSS), and substrate bias voltage (hereafter, VBB). As a bias voltage, the absolute value is larger than VSS.

The VPP is a power source essentially used for a word line driver, a data output driver, and the like, for preventing data loss of a memory cell, and is generated by boosting the VDD.

In addition, VBB is used to minimize the threshold voltage change caused by the body effect on the cell transistor.

The internal power supply described above greatly affects the reliability and current consumption included in the performance criteria of semiconductor circuits.

Therefore, it is one of the important elements of the semiconductor memory device design to control the internal power supply so that it is stably supplied without departing from a predetermined range.

1 is a block diagram illustrating an internal voltage generation circuit of a general semiconductor memory device, and illustrates a VPP generation circuit A and a VBB generation circuit B. As shown in FIG.

First, the VPP generation circuit A includes a VPP detection unit 10, a VPP oscillator (hereinafter, VPP OSC) 11, and a VPP pump 12. The VPP detection unit 10 detects that the VPP level is less than or equal to the set value VREF_VPP and outputs a VPP pumping enable signal VPP_EN for driving the VPP pump.

The VPP OSC 11 generates a pulse signal OSC_VPP when the VPP pumping enable signal VPP_EN is enabled. The VPP pump 12 performs a pumping operation of boosting VDD using the pulse OSC_VPP output from the VPP OSC 11.

On the other hand, the VBB generation circuit B includes a VBB detection unit 13, a VBB oscillator (hereinafter referred to as VBB OSC) 14, and a VBB pump 15.

The VBB detection unit 13 detects that the VBB level is equal to or higher than a corresponding set value VREF_VBB and outputs a VBB pumping enable signal VBB_EN for driving the VBB pump 15.

The VBB OSC 14 generates a pulse OSC_VBB when the VBB pumping enable signal VBB_EN output from the VBB detection unit 13 is enabled.

The VBB pump 15 performs a pumping operation of dropping VDD using the pulse signal OSC_VBB output from the VBB OSC 14. That is, since VBB is reverse biased, the pumping operation is performed to increase in the negative direction.

However, in the semiconductor circuit according to the related art, coupling noise exists due to a parasitic capacitor between VPP and VBB.

As a result, the relatively low level of VBB rises with the rise of the high level power supply (VPP) and greatly deviates from the target value, thereby making the internal voltage unstable.

In addition, if VBB momentarily rises above the external ground power supply (VSS) level, it may cause a latchup failure.

In particular, at the beginning of the power-up, the VPP may rise sharply, and thus the VBB may rise above the VSS level. In this case, problems such as malfunction of the semiconductor memory device are further exacerbated.

Accordingly, an object of the present invention is to provide an internal voltage generation circuit of a semiconductor memory device capable of controlling the operation of high potential voltage pumping according to a substrate bias voltage level at power up.

The internal voltage generation circuit of the semiconductor memory device of the present invention for achieving the above object is a high voltage detector for outputting a high voltage enable signal according to a high voltage level, the high voltage enable signal is applied, and the drive control according to the substrate bias voltage level And a high voltage oscillator generating a high voltage in response to a pulse signal of the high voltage oscillator.

According to the present invention, it is possible to control the high voltage level rising rate at the time of power-up to suppress the abnormal increase in the substrate bias voltage. As a result, the safety of the substrate bias voltage can be ensured and the latch-up phenomenon can be prevented.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Hereinafter, an internal voltage generation circuit for generating a high voltage (VPP) among the internal voltages will be described.

2 is a block diagram illustrating an internal voltage generation circuit of a semiconductor memory device according to an embodiment of the present invention.

The internal voltage generation circuit 250 increases the VPP level when the VPP level falls below the preset value VREF_VPP, and decreases the VPP level when the increased VPP level reaches the preset value VREF_VPP. 100) and a driving controller 200 to determine whether to drive the VPP generator 100 according to the VBB level.

That is, the present invention stabilizes the level of VBB by slowing down the VPP pumping speed according to the level of VBB in order to prevent abnormally rising VBB due to the influence of parasitic capacitors when VPP rises during power-up.

More specifically, the VPP generation unit 100 detects that the VPP level is less than or equal to the set value VREF_VPP, and outputs the VPP detection unit 110 and the drive control unit 200 to output the VPP pumping enable signal VPP_EN. As the driving control signal DRV is enabled, the VPP oscillator (VPP OSC) 120 outputting the pulse signal OSC_VPP and the pulse signal OSC_VPP output from the VPP oscillator (VPP OSC) 120 are used. And a VPP pump 130 for boosting and outputting the VDD level.

Next, the driving controller 200 compares the level of the preset reference voltage VREF_VBB with the level of VBB to output the comparison signal VBB_DET, and outputs a VPP pumping enable signal output from the VPP detection unit 110. The determination unit 220 outputs a driving control signal DRV for determining whether to drive the VPP oscillator VPP OSC 120 in response to the VPP_EN and the comparison signal VBB_DET output from the level detector 210. It includes. In a preferred embodiment of the present invention, the level of the reference voltage VREF_VBB may be set to an external ground voltage VSS level.

3 is a circuit diagram illustrating a level sensing unit in accordance with an embodiment of the present invention.

As shown in FIG. 3, the level detector 210 includes a comparator 210a and a driver 210b.

The comparator 210a receives an external supply power supply VDD to a source terminal, a first transistor P1 having a common connection between a gate terminal and a drain terminal, an external supply power supply VDD to a source terminal, and a gate terminal of the comparator 210a. The second transistor P2 is commonly connected to the gate terminal of the first transistor P1 and the drain terminal is connected to the node a, the substrate bias voltage VBB is applied to the gate terminal, and the drain terminal is the drain of the first transistor P1. Third transistor N1 connected to the stage, reference voltage VREF_VBB is applied to the gate terminal, and the fourth transistor N2 and the third transistor N1 having the drain terminal connected to the drain terminal of the second transistor P2. And a fifth transistor N3 having a drain terminal commonly connected to the source terminal of the fourth transistor N2, a bias voltage Vbias applied to the gate terminal, and a source terminal connected to the ground terminal VSS.

The driver unit 210b includes a sixth transistor P3 and a seventh transistor P4 connected in series between the external power supply terminal VDD and the node c, and an eighth transistor connected in series between the node c and the ground terminal VSS. N4) and a ninth transistor N5.

The ground power supply VSS is applied to the gate terminal of the sixth transistor P3, and the external supply power supply VDD is applied to the gate terminal of the ninth transistor N5.

The gate terminals of the seventh and eighth transistors P4 and N4 are commonly connected to the node a of the comparator 210a.

In addition, the driver unit 210b may further include an inverter INV1 for inverting the potential of the node c to output the comparison signal VBB_DET.

Referring to the operation of the level detection unit of the present invention configured as described above in detail.

When the substrate bias voltage VBB applied to the gate of the third transistor N1 of the comparator 210a is equal to or greater than the reference voltage VREF_VBB applied to the gate of the fourth transistor N2, the second transistor P2 is When turned on, a high level potential is applied to the node a, and the potential applied to the node a is applied to the node b of the driver unit 210b.

Accordingly, the seventh transistor P4 is turned off and the low level potential applied to the node c is inverted by the inverter INV1 and output as a high level signal.

If the substrate bias voltage VBB applied to the gate of the third transistor N1 of the comparator 210b is lower than the reference voltage VREF_VBB applied to the gate of the fourth transistor N2, the fourth transistor ( N2) is turned on to apply a low level potential to node b. Therefore, the seventh transistor P4 is turned on and the high level potential applied to the node c is inverted by the inverter INV1 and output as a low level signal.

4 is a detailed circuit diagram of the determination unit illustrated in FIG. 2.

As shown in FIG. 4, when the VPP pumping enable signal VPP_EN is enabled, the determination unit 220 generates a driving control signal DRV in which whether to enable or not is determined according to the comparison signal VBB_DET. . To this end, the determination unit 220 receives the VPP pumping enable signal VPP_EN, which is the output signal of the VPP detection unit 110, and the comparison signal VBB_DET, which is inverted and delayed through the inverter INV2, and receives the driving control signal DRV. ), And a logic gate AND.

The driving of the VPP oscillator (VPP OSC) 120 is determined according to whether the driving control signal DRV output from the logic gate AND is enabled.

When the substrate bias voltage VBB is greater than or equal to the reference voltage VREF_VBB, for example, VSS, the comparison signal VBB_DET becomes high, thereby disabling the driving control signal DRV so that the VPP oscillator VPP OSC 120 ). In addition, when the substrate bias voltage VBB is lower than the reference voltage VREF_VBB, the comparison signal VBB_DET is at a low level. As a result, the driving control signal DRV is enabled to thereby enable the VPP oscillator (VPP OSC) 120. Outputs a pulse signal OSC_VPP.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

1 is a block diagram illustrating an internal voltage generation circuit of a general semiconductor memory device;

2 is a block diagram illustrating an internal voltage generation circuit of a semiconductor memory device according to an embodiment of the present invention;

3 is a circuit diagram of a level sensing unit according to an embodiment of the present invention; and

4 is a detailed circuit diagram of the determination unit illustrated in FIG. 2.

<Detailed description of the major symbols in the drawings>

110: VPP detection unit 120: VPP OSC

130: VPP pump 210: level detector

220: judgment unit

Claims (6)

A high voltage detector for outputting a high voltage enable signal according to a high voltage level; A driving controller receiving the high voltage enable signal and outputting a driving control signal according to a substrate bias voltage level; And a high voltage oscillator configured to determine whether to drive according to the driving control signal, and a high voltage pump configured to generate a high voltage in response to a pulse signal of the high voltage oscillator. The method of claim 1, The driving controller may include a level detector configured to detect a substrate bias voltage level and output a comparison signal; And And a determiner configured to enable the driving control signal in response to the comparison signal and the high voltage enable signal. The method of claim 2, And the level detecting unit outputs a comparison signal by comparing the substrate bias voltage with a reference voltage level. The method of claim 2, The determination unit, An inverter unit for delaying the phase inversion of the comparison signal; And And an AND gate configured to AND the output signal of the inverter unit and the high voltage enable signal. The method of claim 3, wherein And the reference voltage is a voltage for measuring whether or not the substrate bias voltage exceeds a reference level. The method of claim 3, wherein And the reference voltage is a ground voltage.

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