KR20100079779A - Method for designing semiconductor device - Google Patents

Method for designing semiconductor device Download PDF

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Publication number
KR20100079779A
KR20100079779A KR1020080138350A KR20080138350A KR20100079779A KR 20100079779 A KR20100079779 A KR 20100079779A KR 1020080138350 A KR1020080138350 A KR 1020080138350A KR 20080138350 A KR20080138350 A KR 20080138350A KR 20100079779 A KR20100079779 A KR 20100079779A
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KR
South Korea
Prior art keywords
metal layer
layer
contact
optical proximity
proximity correction
Prior art date
Application number
KR1020080138350A
Other languages
Korean (ko)
Inventor
김영미
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080138350A priority Critical patent/KR20100079779A/en
Publication of KR20100079779A publication Critical patent/KR20100079779A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The present invention provides a method of designing a semiconductor device. The method includes the steps of: placing a library, connecting a library of metal layers, applying optical proximity correction to the metal layer, and expanding patterns for increasing the oralab margin of the contact layer to the metal layer to which the optical proximity correction has been applied. Producing and merging. It is possible to reduce the error of optical proximity correction (OPC) due to the jog pattern, that is, the pinch or bridge occurrence rate, and to ensure the overlap margin between the metal layer and the contact and / or via holes, and to prevent the OPC run time delay caused by the jog. This can reduce the run time.

Description

Method for designing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a semiconductor device, and more particularly, to a method of designing a semiconductor device including the design of a metal layer and contacts and / or vias.

Hereinafter, a general method of designing a semiconductor device will be described with reference to the accompanying drawings.

1A to 1C are diagrams for describing a method of designing a general semiconductor device.

As shown in FIG. 1A, a metal line 10 is first designed.

According to the general method of designing the metal layer, in order to improve the overlap margin of the contact and / or vias, a predetermined length of a portion of the contact and / or via hole pattern 20 as shown in FIG. Metal pads 30 are used to wrap the contacts and / or vias. Thereafter, the metal pad 30 is inserted as shown in FIG. 1C. Here, the contact serves to connect the lower structure of the semiconductor device, for example, the gates of the transistor to the metal layer, and the via serves to connect the metal layers to each other.

FIG. 2 is an enlarged view of the drawing shown in FIG. 1C. Reference numeral 40 is a real photograph showing the phenomenon of 42.

However, the metal pad 30 generated as described above is combined with the previously designed metal line 10 to produce a jog pattern. Here, the jog pattern is a small edge, and OPC is excessively performed when OPC (Optical Proximity Correction) is performed on an area that is not defined due to the characteristics of the photo process. In general, this area does not perform OPC. Jog size is divided into edges that are configured to be smaller than the minimum fragment size. The jog pattern has a problem of causing pinch, bridge, etc. in performing OPC.

As a result, in the design of the metal layer, a method generally used to secure overlap margin of the metal layer and the contact and / or via hole has been to extract the hole pattern region to add the metal pad 30. However, this method has a problem that in performing OPC of the metal layer, excessive OPC or incorrect OPC due to a jog pattern is performed, which adversely affects runtime and accuracy.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of designing a semiconductor device including optical proximity correction of a metal layer capable of reducing an error rate of optical proximity correction and improving an overlap margin between the metal layer and a contact and / or via hole pattern. have.

According to an aspect of the present invention, there is provided a method of designing a semiconductor device, comprising: arranging a library, connecting a library of the metal layer, applying an optical proximity correction to the metal layer, and applying the optical proximity correction. It is preferable that the step of generating and merging the expansion pattern for increasing the oraab margin of the contact layer in the metal layer.

The method of designing a semiconductor device according to the present invention can reduce errors in optical proximity correction (OPC) due to a jog pattern, that is, pinch or bridge occurrence rate, and ensure an overlap margin between a metal layer and a contact and / or via hole. Therefore, the delay of the OPC run time due to the jog can be prevented, thereby reducing the run time.

Hereinafter, a method of designing a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

3 is a flowchart illustrating a method of designing a semiconductor device according to an embodiment of the present invention.

First, in designing a metal layer, the metal layer and a contact (layer) and / or via holes overlap. In this process, in arranging the contact and / or via hole in the center of the metal line, steps 50 to 130 are performed as follows. Hereinafter, only the contact is described, but the same design method as the contact can be applied to the via hole.

4A to 4D are design diagrams showing the results performed in each step shown in FIG. 3. That is, these drawings illustrate a method of designing a semiconductor device according to the present invention for preventing an optical proximity correction (OPC) error due to a jog and securing a contact overlap margin.

As shown in FIG. 4A, steps 50 and 70 are performed to design the metal layer. Here, reference numeral 60 denotes a contact layer and 61 denotes a metal line.

That is, the necessary contact layer is arranged simultaneously with the poly layer (step 50).

After the 50th step, a library of the poly layer, the contact layer, and the metal layer is disposed (step 70).

After operation 70, the library of metal layers is connected (operation 90).

After operation 90, optical proximity correction is applied to the metal layer (operation 110).

FIG. 5 is a flowchart for describing an embodiment 110A of the present invention with respect to step 110 illustrated in FIG. 3.

Referring to FIG. 5, the design and construction method of step 110 shown in FIG. 3 is as follows.

First, steps 112 through 118 are performed to perform OPC on the metal layer. The result of performing step 118 is as shown in FIG. 4B. Reference numeral 119 shown in FIG. 4B indicates a state of being OPC.

After operation 90, an automatic routing (Placement & Rout) is performed to connect the metal layers (operation 112).

After step 112, a contact layer for wiring connection of the metal layer is disposed (step 114). At this time, according to the present invention, the extraction of the contact layer for improving the overlap margin between the metal layer and the contact layer is not performed.

After step 114, a contact coverage check is performed on the wiring of the metal layer, and when the contact layer is not completely covered by the metal layer, a portion of the contact layer that is not completely covered is stored as a temp layer. (Step 116).

After operation 116, the optical proximity correction of operation 114 is performed (operation 118). That is, the optical proximity correction for the arrangement of the contact layer is performed. Here, if the optical proximity correction is not properly performed, the optical proximity correction is performed again.

However, if the optical proximity correction is properly performed, as shown in FIG. 4C, steps 120 are performed to check the contact layer and proceed with sizing for the contact layer that is not completely covered. Looking at portions 121 and 123 shown in FIG. 4C, one can see contact layer 160 not completely covered by a metal layer. Reference numeral 162 is a metal layer around the contact layer 160.

That is, after step 116, the stored portion of the contact layer, that is, the temporal layers, is inserted into the metal layer where the optical proximity correction is completed (step 120). At this time, the metal layer and the portion of the stored contact layer are inserted into the same layer.

In operation 120, the overlapping margin of the contact layer may be sized and inserted in consideration of the process overlap margin. In addition, the sizing rule is process dependent.

After step 120, the merged layer is output as shown in FIG. 4D (step 122). Looking at portions 121 and 123 shown in FIG. 4D, it can be seen that contact layer 160 is not completely covered by a metal layer. Reference numeral 162 is a metal layer around the contact layer 160.

On the other hand, after step 110, an extension pattern for increasing the margin of contact of the contact layer is generated and merged in the metal layer to which the optical proximity correction is applied (step 130).

Finally, referring to FIG. 3, according to the method of designing a semiconductor device according to the present invention, it can be seen that when the design of the metal layer and the OPC are performed, extraction of the metal layer of the contact overlap portion is performed after the OPC.

6 is a view showing the results simulated by the method for designing a semiconductor device according to the present invention.

Referring to FIG. 6, a target 200 and a simulation result 202 of a method of designing a semiconductor device according to the present invention can be seen. It can be seen that the simulation results 202 are very good when compared with the general semiconductor device design method shown in FIG. 2.

As a result, in the above-described method of designing a semiconductor device according to the present invention, after performing OPC without making a jog pattern, an overlap margin is extended by extending a metal layer in a portion overlapping with a contact hole and / or a via hole. It can be secured. Therefore, according to the manufacturing method of a general semiconductor device, it is possible to prevent an OPC error that has arisen and to secure an intended design in the process.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1A to 1C are diagrams for describing a method of designing a general semiconductor device.

FIG. 2 is an enlarged view of the drawing shown in FIG. 1C.

3 is a flowchart illustrating a method of designing a semiconductor device according to an embodiment of the present invention.

4A to 4D are design diagrams showing the results performed in each step shown in FIG. 3.

FIG. 5 is a flowchart for describing an exemplary embodiment of the present invention with respect to step 110 illustrated in FIG. 3.

6 is a view showing the results simulated by the method for designing a semiconductor device according to the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

60: contact 61: metal line

119: OPC has been performed

Claims (3)

Arranging the necessary contact layers simultaneously with the poly layer and disposing the library of the poly layer, the contact layer and the metal layer; Connecting the library of metal layers; Applying optical proximity correction to the metal layer; And And generating and merging an extension pattern for increasing the oraab margin of the contact layer on the metal layer to which the optical proximity correction is applied. The method of claim 1, wherein applying optical proximity correction to the metal layer Performing automatic routing to connect the metal layers; Disposing the contact layer for wire connection of the metal layer; Performing a contact coverage check on the wiring of the metal layer to store a portion of the contact layer that is not completely covered by the metal layer; Performing optical proximity correction on the placement of the contact layer; And And inserting the stored portions of the contact layer into the metal layer where the optical proximity correction is completed. The method of designing a semiconductor device as claimed in claim 2, wherein said size is inserted while said parts are inserted into said metal layer while said process margin is taken into consideration, and said rules of said size are dependent on the process.
KR1020080138350A 2008-12-31 2008-12-31 Method for designing semiconductor device KR20100079779A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014019544A1 (en) * 2012-08-03 2014-02-06 无锡华润上华半导体有限公司 Optical proximity correction method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014019544A1 (en) * 2012-08-03 2014-02-06 无锡华润上华半导体有限公司 Optical proximity correction method
CN103576443A (en) * 2012-08-03 2014-02-12 无锡华润上华半导体有限公司 Optical proximity correction method

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