KR20100078534A

KR20100078534A - Method for manufacturing complementary metal-oxide semiconductor image sensor

Info

Publication number: KR20100078534A
Application number: KR1020080136819A
Authority: KR
Inventors: 박정수
Original assignee: 주식회사 동부하이텍
Priority date: 2008-12-30
Filing date: 2008-12-30
Publication date: 2010-07-08

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a technique for manufacturing a CMOS (Complementary Metal-Oxide Semiconductor) image sensor (CIS). In the existing CMOS image sensor manufacturing technology, the distance between the upper metal wires is designed to be considerably wider than the peripheral circuit area, and as a result, the upper metal wires after the process tend to increase in size at the bottom thereof. This is the main reason for the increased resistance. Accordingly, in the present invention, a plurality of metal wires are connected to each via on a semiconductor substrate, and the upper vias formed under the metal wires in the multi-layered metal wires are formed to be larger than the size of the upper metal wire by a predetermined ratio. It is characterized by. As a result, the present invention can lower the resistance of the circuit and realize stable high speed without burdening a large cost.

Description

METHOD FOR MANUFACTURING COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR IMAGE SENSOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a CMOS (Complementary Metal-Oxide Semiconductor) image sensor, and more particularly, to a method for manufacturing a CMOS image sensor suitable for high-speed video by effectively lowering a resistance of a circuit.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. In a dual charge coupled device (CCD), individual metal-oxide-silicon (MOS) capacitors are very different from each other. A device in which charge carriers are stored and transported in a capacitor while in close proximity. Moreover, CMOS (Complementary Metal-Oxide Semiconductor) image sensors use CMOS technology that uses control circuits and signal processing circuits as peripheral circuits to make MOS transistors by the number of pixels and use them. And a switching method of sequentially detecting outputs.

In the manufacture of such various image sensors, efforts are being made to increase the photo sensitivity of the image sensor, one of which is a condensing technology. For example, the CMOS image sensor is composed of a light sensing element portion for detecting light and a CMOS logic circuit portion for processing the detected light into an electrical signal to make data. In order to increase the light sensitivity, efforts have been made to increase the ratio of the area of the light sensing element portion to the total image sensor area (commonly called 'Fill Factor'), but since the logic circuit portion cannot be essentially removed, the limited area is Under these efforts, there are limits.

In the conventional CMOS image sensor manufacturing process, a metal pad is formed in a logic circuit region, and a resultant device film is deposited on the resultant to protect the device from external moisture and scratches, and then, an etching process is performed to open the metal pad. The color filter array is formed in the region.

Meanwhile, in the CMOS image sensor having a stack structure, a photodiode is formed on the uppermost layer. FIG. 1 illustrates a cross-sectional view of a process after the metal wiring is formed during the manufacturing process of the CMOS image sensor having such a photodiode.

Hereinafter, a metal wire forming process including a manufacturing process of the CMOS image sensor will be described with reference to FIG. 1.

As shown in FIG. 1, first, an active region and a non-active region of a device are distinguished by a device isolation process such as shallow trench isolation (STI) on a silicon substrate as the semiconductor substrate 10. An isolation film (not shown) is formed.

Thereafter, after the gate oxide film is formed on the upper surface of the semiconductor substrate 10 of the device isolation film, the gate electrode 12 made of a conductive material, for example, doped polysilicon is formed thereon. In this case, the silicon oxide film SiO 2 may be grown to a predetermined thickness, for example, about 20 kPa to about 50 kPa as an insulating thin film serving as a buffer on the upper surface of the gate electrode 12.

Then, the conductive dopant is ion implanted at low concentration to form a light doped drain (LDD) region (not shown) that is self-aligned at the edge of the gate electrode 12, and an insulating material Is formed over the entire substrate and then etched by a dry etching process to form spacers 14 on the sidewalls of the gate electrode 12.

Subsequently, the same dopant as the LDD region is ion-implanted on the entire surface of the resultant to form a source / drain region (not shown) which is self-aligned to the spacer 14.

Thereafter, a dopant is injected between the device isolation layers to form the photodiode 16, and the multi-layered metal wires are formed to be connected layer by layer through vias. In Fig. 1, reference numeral 18 denotes the (most) upper via, and reference numeral 20 denotes the (most) upper metal wiring, respectively.

At this time, the CMOS image sensor should be designed such that there is no metal wiring on the photodiode 16 due to the characteristic that the signal must be generated by light, and focuses on minimizing the metal wiring for signal transmission.

After this series of processes, the micro lens 22 is finally formed to complete the manufacturing process of the CMOS image sensor.

In the conventional CMOS image sensor manufacturing process, the uppermost metal wiring 20 in the pixel area B occupies a relatively small area in order to minimize path blocking of light.

Accordingly, the distance between the uppermost metal wires is designed to be considerably wider than the peripheral circuit area A. As a result, after the process such as metal sputtering, patterning, etching, etc., The upper metal wiring has a cross section as shown in FIG. 2. That is, in the case of the upper metal interconnection 20 in the pixel region B, the lower end tends to be larger than the originally designed size, that is, the trapezoidal result is displayed.

In this case, only a method of increasing the thickness of the metal wiring to reduce the resistance may be considered as a method of increasing the signal processing speed to implement the video.

However, there is a limit in lowering the overall resistance because the resistances of vias and contacts connecting the lower metal wirings or the metal wirings remain the same.

Therefore, in view of the tendency of the lower end of the upper metal wiring in the pixel region to be large, the present invention can realize a high speed by reducing the resistance of the CMOS image sensor by forming a large via directly under the upper metal wiring of the CMOS image sensor in advance. The company aims to develop CMOS image sensor manufacturing technology.

To this end, the present invention is characterized in that the upper via is formed to a size in consideration of the increase in the size of the bottom of the upper metal wiring in the pixel area.

To this end, the present invention is characterized in that the upper via is formed a predetermined ratio, for example, 20% larger than the size of the upper metallization.

According to an embodiment of the present invention, a process of connecting multiple layers of metal wires to respective vias on a semiconductor substrate on which a photodiode is formed, and forming a lower portion of an upper metal wire in the multilayer metal wires It provides a method for manufacturing a CMOS image sensor comprising the step of forming the upper via to be larger than the size of the upper metal wiring by a predetermined ratio.

According to another embodiment of the present invention, a process of forming an isolation layer on a semiconductor substrate, a process of forming a gate electrode on an upper surface of the semiconductor substrate of the isolation layer, and a low concentration of the conductive dopant Forming a LDD region by implanting in a silicon oxide, forming a spacer on sidewalls of the gate electrode, ion implanting the conductive dopant to form a source / drain region, and forming a photodiode between the device isolation layers. And forming the lower metal wiring and the upper metal wiring so as to be connected to each layer through the via, and forming the upper via formed in the lower portion of the upper metal wiring to be larger than a predetermined ratio by the size of the upper metal wiring. It provides a method for manufacturing a CMOS image sensor.

According to the present invention, it is possible to minimize the RC delay of the CMOS image sensor having a video function requiring high-speed signal processing by lowering the resistance of the top via connected to the top metal wiring. That is, in the conventional CMOS image sensor design, the size of the upper via is generally the same as or smaller than that of the upper metal interconnection. However, in the present invention, the size of the upper via in the pixel region is determined in consideration of an increase in the size of the lower end of the upper metal interconnection in the pixel region. By forming larger than the metal wiring, it is possible to lower the resistance of the circuit and realize stable high speed without burdening a large cost.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a process plan view specifically illustrating a CMOS image sensor manufacturing process according to the present embodiment.

As illustrated in FIG. 3, in the CMOS image sensor process according to the present embodiment, in forming the upper via 180 that is preceded by the formation of the upper metal wiring 200, the same size as or larger than the size of the existing upper metal wiring. In contrast to forming smaller, the upper via 180 is formed larger than the upper metal wiring 200.

That is, the upper metal wiring 200 in the pixel region may become large after the series of processes such as metal sputtering, patterning, etching, etc., but in the present embodiment, In consideration of an increase in the size of the lower end of the upper metal wire 200, the upper via 180 directly under the upper metal wire 200 may be formed in advance.

Specifically, the size of the upper via 180 may be a size in consideration of an increase in the size of the lower end of the upper metal line 200 in the pixel area.

More specifically, the size of the upper via 180 may be a predetermined ratio, for example, 20% larger than the size of the upper metal wiring 200.

This feature of the invention will be more clearly understood in the process cross section of FIG. 4.

As illustrated in the cross-sectional view of FIG. 4, the left exemplary view is a conventional upper via 18 and an upper metal wiring 20, and the right exemplary view is an upper via 180 and an upper metal wiring 200 according to the present embodiment. ).

Compared with the prior art, it can be seen that the upper via 180 is large in size in consideration of an increase in the bottom size of the upper metal wiring 200.

Hereinafter, a series of processes in which the CMOS image sensor is manufactured according to the present exemplary embodiment will be described with reference to FIGS. 3 and 4.

As already mentioned above, the present embodiment is characterized for the upper vias and the upper metallizations, and the same reference numerals and descriptions in FIG. 1 are cited for the remaining components required to explain the CMOS image sensor manufacturing process. Let's do it.

First, a device isolation layer (not shown) that separates an active region and a non-active region of a device by a device isolation process such as shallow trench isolation (STI) on a silicon substrate as the semiconductor substrate 10. To form.

Thereafter, a dopant is injected between the device isolation layers to form the photodiode 16, and the multi-layered metal wires are formed to be connected layer by layer through vias.

In this embodiment, as illustrated in FIGS. 3 and 4, the uppermost via of the vias connecting the multi-layered metal wires, that is, the via 180 formed under the uppermost metal wire 200, is disposed in the via 180. On the other hand, instead of forming vias 18 that are the same as or smaller than the top metal wiring 20 as before, the top metal wiring in the pixel region, that is, after a series of processes such as metal sputtering, patterning, and etching, etc. The top via 180 is formed to have a large size in consideration of the size of the bottom of the top metal wiring.

Specifically, the top via 180 in the present embodiment has a predetermined ratio, for example, a size increased by 10 to 20%, more specifically, a size increased by 20% than the size of the upper metal wire 200. do.

As such, when the size of the top via 180 is increased, the resistance of the circuit connected to the top may be lowered.

Usually, the resistance of a single via having 0.2 μm CD (Critical Dimension) appears to be about 12 ohm / ea. When the size is increased by 10% with 0.22 μm CD, it decreases to about 6 ohm / ea.

As described above, in the present embodiment, in consideration of the tendency of the lower end of the upper metal interconnection in the pixel region to be large, the embodiment of the present invention is implemented so as to form a via immediately below the upper metal interconnection of the CMOS image sensor in advance.

The foregoing embodiments are intended to illustrate, not limit, the invention, and those skilled in the art should note that many other embodiments can be designed without departing from the scope of the invention as defined by the appended claims. do. In the claims, any reference signs placed between parentheses shall not be construed to limit the invention. The expression “comprising”, “comprising” and the like does not exclude the presence of elements or steps other than those listed in all the claims or the specification as a whole. The singular references of components do not exclude a plurality of references of such components, and vice versa. The simple fact that certain means are described in different dependent claims does not indicate that a combination of these means cannot be used.

1 is a cross-sectional view illustrating a conventional CMOS image sensor manufacturing process;

2 is an exemplary diagram of an upper via and an upper metallization shown in a conventional CMOS image sensor manufacturing process;

3 is a process plan view illustrating a CMOS image sensor manufacturing process according to an embodiment of the present invention;

4 is a view illustrating a comparison between upper vias and upper metal wirings of a conventional CMOS image sensor manufacturing process, and upper vias and upper metal wirings of a CMOS image sensor manufacturing process according to the present embodiment.

Claims

Connecting the multilayer metal wires to the respective vias on the semiconductor substrate on which the photodiode is formed;

A process of forming an upper via formed at a lower portion of the upper metal wiring in the multi-layered metal wirings by a predetermined ratio larger than the size of the upper metal wiring;

CMOS image sensor manufacturing method comprising a.

Forming a device isolation film on the semiconductor substrate,

Forming a gate electrode on an upper surface of the semiconductor substrate of the device isolation layer;

Implanting the conductive dopant at low concentration to form an LDD region;

Forming spacers on sidewalls of the gate electrode and ion implanting the conductive dopant to form source / drain regions;

Forming a photodiode between the device isolation layers and forming a lower metal wiring and an upper metal wiring so as to be connected layer by layer through vias;

Forming an upper via formed in the lower portion of the upper metal wiring by a predetermined ratio larger than the size of the upper metal wiring;

CMOS image sensor manufacturing method comprising a.

The method according to claim 1 or 2,

The predetermined ratio is a ratio larger than the size of the lower end of the upper metal wiring in the pixel area of the CMOS image sensor.

The method according to claim 1 or 2,

The predetermined ratio is a CMOS image sensor manufacturing method of 10 to 20% of the size of the upper metal wiring.