JP2008053366A - Solid state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the deterioration of sensitivity characteristics and of a saturation signal amount that might be caused as pixels are made fine, in a stacked and amplified MOS sensor. <P>SOLUTION: For example, in a unit sell 6<SB>11</SB>of a MOS sensor, there are provided an n conductivity type charge storage 24 becoming a photodiode, and a p-conductivity well region 25 of a scanning transistor on the surface of a p-conductivity epitaxial layer 21a on a p-conductivity silicon substrate 21. Above the epitaxial layer 21a, an n-conductivity photoelectric conversion layer 39 is laminated via interlayer films 31, 33, 35 and a nitride film 38. On the photoelectric conversion layer 39 there is connected an n-conductivity contact layer 40 leading to the charge storage 24 and penetrating the nitride film 38 and the interlayer films 31, 33, 35. The photoelectric conversion layer 39 is separated by a separation layer 41 for every pixel. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly, to a stacked amplification type solid-state imaging device including stacked photoelectric conversion layers used in a CMOS (Complementary Metal Oxide Semiconductor) sensor camera.

  In recent years, in MOS type solid-state imaging devices, the problem that sensitivity characteristics and saturation signal amount deteriorate due to the reduction in the area of the embedded photodiode, which is a photoelectric conversion unit, with the miniaturization of pixels (unit cells) has become apparent. ing. Further, miniaturization increases the amount of signal leakage between pixels, and there is a problem that color reproducibility is deteriorated due to an increase in color mixture.

  That is, in the case of a MOS type solid-state imaging device, the pixel size per pixel has come to be less than 2 μm with the recent increase in the number of pixels and the reduction in pixel size. If the pixel size is further reduced, the size of the embedded photodiode will be less than the light diffraction limit. Therefore, it is impossible to maintain the pixel characteristics no matter what layout is used.

Recently, in order to increase the aperture ratio of a pixel, a technique of forming a photoelectric conversion film on a scanning transistor (so-called stacked amplification type solid-state imaging device) is also seen, but the problem of afterimage and signal leakage between pixels is It is not solved (for example, refer to Patent Document 1).
JP 2001-144279 A

  The present invention has been made to solve the above problems, and provides a solid-state imaging device capable of suppressing deterioration of sensitivity characteristics and saturation signal amount due to pixel miniaturization and preventing increase in color mixture. The purpose is to do.

  According to one aspect of the present invention, there is provided a solid-state imaging device including an imaging region formed by two-dimensionally arranging a plurality of unit cells including a photoelectric conversion unit and a signal scanning circuit unit in a matrix direction on a semiconductor substrate. The photoelectric conversion unit is formed by stacking a charge storage layer formed on a surface region of the semiconductor substrate, an interlayer film above the charge storage layer, and separately for each unit cell. There is provided a solid-state imaging device including a photoelectric conversion layer.

  Further, according to one aspect of the present invention, a plurality of signal scanning circuit units formed in a surface region of the semiconductor substrate and a surface region of the semiconductor substrate provided in the vicinity of the plurality of signal scanning circuit units, respectively. A plurality of photoelectric conversion units including an embedded charge storage layer and a photoelectric conversion layer stacked above the charge storage layer via an interlayer film, and the photoelectric conversion layer are separated into pixel units. A solid-state imaging device is provided.

  With the above configuration, it is possible to provide a solid-state imaging device that can suppress deterioration of sensitivity characteristics and saturation signal amount due to pixel miniaturization and can prevent increase in color mixture.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, it should be noted that the drawings are schematic, and the dimensions and ratios of the drawings are different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

[First Embodiment]
FIG. 1 shows a basic configuration of a solid-state imaging device according to the first embodiment of the present invention. Here, a MOS sensor (laminated amplification type solid-state imaging device) including a photoelectric conversion layer having a laminated structure used for a CMOS sensor camera or the like will be described as an example.

As shown in FIG. 1, this MOS sensor includes photodiodes (charge storage units) 1 ₁₁ , 1 ₁₂ , 1 ₁₃ , 1 ₂₁ , 1 ₂₂ , 1 ₂₃ , 1 ₃₁ , 1 ₃₂ , 1 ₃₃ , and each photodiode. 1 _11, 1 _12, 1 _13, 1 _21, 1 _22, 1 _23, 1 _31, 1 _32, 1 ₃₃ of the signal read transistor 2 ₁₁ for reading a signal, 2 _12, 2 _13, 2 _21, 2 _22, 2 ₂₃ , 2 _31, 2 _32, and 2 _33, amplification for amplifying the respective photodiodes 1 _11, 1 _12, 1 _13, 1 _21, 1 _22, 1 _23, 1 _31, 1 _32, signals read out from 1 ₃₃ Transistors 3 ₁₁ , 3 ₁₂ , 3 ₁₃ , 3 ₂₁ , 3 ₂₂ , 3 ₂₃ , 3 ₃₁ , 3 ₃₂ , 3 ₃₃ and vertical selection transistors (address transistors) 4 ₁₁ , 4 ₁₂ , 4 for selecting a line from which a signal is read _13, 4 _21, 4 _22, 4 _23, 4 _31, 4 _32, 4 _33, a reset transistor for resetting the signal charge _11, 5 _12, 5 _13, 5 _21, 5 _22, 5 _23, 5 _31, 5 _32, 5 ₃₃ a plurality of unit cells consisting of (pixel) 6 _11, 6 _12, 6 _13, 6 _21, 6 _22, 6 ₂₃ , 6 ₃₁ , 6 ₃₂ , and 6 ₃₃ are arranged in a two-dimensional form of 3 (row direction) × 3 (column direction). Note that although 3 × 3 is used here, more unit cells are arranged in an actual MOS sensor.

The horizontal address lines 8 ₁ , 8 ₂ , 8 ₃ wired in the horizontal direction from the vertical shift register 7 are connected to the vertical selection transistors 4 ₁₁ , 4 ₁₂ , 4 ₁₃ , 4 ₂₁ , 4 ₂₂ , 4 ₂₃ , 4 _31,. It is connected to the gates of 4 ₃₂ and 4 ₃₃ and used for determining a line from which a signal is read. Reset line 9 _1, 9 _2, 9 ₃ is connected to the gate of the reset transistor 5 _11, 5 _12, 5 _13, 5 _21, 5 _22, 5 _23, 5 _31, 5 _32, 5 _33.

The sources of the amplifying transistors 3 ₁₁ , 3 ₁₂ , 3 ₁₃ , 3 ₂₁ , 3 ₂₂ , 3 ₂₃ , 3 ₃₁ , 3 ₃₂ and 3 ₃₃ are connected to the vertical signal lines 10 ₁ , 10 ₂ and 10 _3. The drains of the load transistors 11 ₁ , 11 ₂ , 11 ₃ are connected to one end. Each gate of the load transistors 11 ₁ , 11 ₂ , 11 ₃ is connected to the signal line 12, and each source is connected to the signal line 13. The other ends of the vertical signal lines 10 ₁ , 10 ₂ , 10 ₃ are connected to the horizontal signal line 16 via horizontal selection transistors 15 ₁ , 15 ₂ , 15 ₃ selected by a horizontal selection pulse supplied from the horizontal shift register 14. It is connected to.

  1 is a pixel region (imaging region), and 18 is a peripheral circuit region (drive circuit region) including registers 7 and 14 for scanning the pixel region 17.

The operation of the MOS sensor configured as described above is as follows. First, the vertical selection pulse from the vertical shift register 7 is sequentially applied to the horizontal address lines 8 ₁ , 8 ₂ , and 8 ₃ , and only the vertical selection transistors of the line are turned on. Then, a source follower circuit is configured by the amplification transistor and the load transistor of the selected line, and a gate voltage of the amplification transistor, that is, a voltage substantially equal to the voltage of the photodiode appears on the vertical signal line. Next, a horizontal selection pulse from the horizontal shift register 14 is sequentially applied to the horizontal selection transistors 15 ₁ , 15 ₂ , and 15 _3, and signals for one line are sequentially extracted from the horizontal signal line 16. By continuing this operation sequentially to the next line and further to the next line, all two-dimensional signals can be read out.

FIG. 2 simply shows a unit cell configuration of the MOS sensor shown in FIG. In addition, the figure (a) is a top view which permeate | transmits and shows a part, The figure (b) is sectional drawing which follows the IIb-IIb line | wire of figure (a). Also, here it is described a unit cell 6 ₁₁ Example The same applies to other cells.

In FIG. 2, for example, an activation region 23 is defined by a device isolation region 22 in a surface region (P conductivity type epitaxial layer) 21 a of a P conductivity type (second conductivity type) silicon substrate 21 which is a semiconductor substrate. Yes. Its activation region 23, the photodiode 1 ₁₁ become N conductivity type (first conductivity type) charge accumulation portion 24, and, scan transistor section (signal scanning circuit) P conductivity type well region 25 for Is provided. In the case of the present embodiment, the well region 25 is formed such that a part (one end) thereof extends to the lower part of the element isolation region 22.

Corresponding to the activated region 23, on the surface of the P conductivity type epitaxial layer 21a, a gate insulating film over each of the gate electrodes 26 of the signal read transistor 2 _11, the reset transistor motor 5 ₁₁ gate electrode 27 of the vertical the gate electrode 28 of the selection transistor 4 _11, and a gate electrode 29. the amplification transistor 3 ₁₁ is disposed. On the surface region of the well region 25 adjacent to the gate electrodes 26, 27, 28, and 29, the N conductivity type diffusion layer region serving as the source or drain of each of the transistors 2 ₁₁ , 3 ₁₁ , 4 ₁₁ , and 5 ₁₁ , respectively. 30 is formed. Note that the charge storage section 24 functions as a drain of the signal readout transistor 2 _11.

  A lower wiring layer 32 made of, for example, aluminum (Al) is provided on the surface of the P-conductivity type silicon substrate 21 via an interlayer film 31. An upper wiring layer 34 made of, for example, Al is provided above the lower wiring layer 32 via an interlayer film 33. An interlayer film 35 is provided on the interlayer film 33 so as to cover the periphery of the upper wiring layer 34. The interlayer films 31 and 33 are formed with a plurality of gate contacts 36 and diffusion layer contacts 37 connected to the wiring layers 32 and 34 in this cross section or other cross sections.

  On the interlayer film 35, an N conductivity type photoelectric conversion layer 39 is laminated via a nitride film 38. The photoelectric conversion layer 39 is, for example, a photo-CVD (Chemical Vapor Deposition) film made of amorphous silicon having a high hydrogen content such as N-doped polysilicon. The photoelectric conversion layer 39 is connected to an N conductivity type contact layer 40 that penetrates the nitride film 38 and the interlayer films 31, 33, and 35 and is connected to the charge storage portion 24. The charge storage portion 24 and the photoelectric conversion layer 39 including the contact layer 40 constitute a photoelectric conversion portion.

A separation layer 41 for separating the photoelectric conversion layer 39 for each pixel is provided on the periphery of the photoelectric conversion layer 39. The isolation layer 41 is disposed substantially corresponding to the element isolation region 22 excluding the activation region 23. That is, in the unit cells 6 ₁₁ , 6 ₁₂ , 6 ₁₃ , 6 ₂₁ , 6 ₂₂ , 6 ₂₃ , 6 ₃₁ , 6 ₃₂ , and ₆₃₃ , the photoelectric conversion layers 39 are separated from each other by the separation layer 41. As a result, for all the pixels, the photoelectric conversion layer is formed as a single layer, and the adjacent pixels are compared to those in which the pixels are separated by the electric field between the electrode drawn from the charge storage portion and the transparent electrode. It is possible to reduce the charge mixture between the two. Therefore, even if the pixels are miniaturized, it is possible to ensure good sensitivity characteristics and saturation signal amount, and to prevent color mixing. Note that the separation layer 41 has a smaller hydrogen content (lower light transmittance) than the photoelectric conversion layer 39, for example, a TEOS (Tetra Ethoxy Silane) film.

  A transparent electrode 42, a color filter 43, and a microlens 44 are laminated in order on at least the upper surface of the photoelectric conversion layer 39.

In such a stacked amplification type MOS sensor (unit cell 6 ₁₁ ), the light condensed by the microlens 44 is incident on the photoelectric conversion layer 39 via the color filter 43 and the transparent electrode 42. Is converted into a signal charge. This signal charge is drawn from the photoelectric conversion layer 39 to the charge storage unit 24 via the contact layer 40 due to the potential relationship (potential difference) between the photoelectric conversion layer 39 and the charge storage unit 24 and stored therein. The

  Next, a method for manufacturing the MOS sensor having the above structure will be briefly described with an example. In addition, each process drawing shown here is sectional drawing corresponding to FIG.2 (b) (along IIb-IIb line | wire of Fig.2 (a)).

First, as shown in FIG. 3, for example, element isolation regions 22 are selectively formed in the surface region of the P conductivity type epitaxial layer 21a on the P conductivity type silicon substrate 21. For example, the impurity concentration of the P conductivity type silicon substrate 21 is 1E18 to 1E20 cm ⁻³ , and the impurity concentration of the P conductivity type epitaxial layer 21 a is 1E14 to 1E16 cm ⁻³ .

  Next, for example, as shown in FIG. 4, the charge storage portion 24 and the well region 25 are formed in the activation region 23 defined by the element isolation region 22. The formation of the charge storage unit 24 may be performed after the gate electrode is arranged.

Then, as shown in FIG. 5, on the surface of the P conductivity type epitaxial layer 21a, a gate insulating film over each of the gate electrodes 26 of the signal read transistor 2 _11, the reset transistor motor 5 ₁₁ gate electrode 27 of the vertical the gate electrode 28 of the selection transistor 4 _11, and to form a gate electrode 29 of the amplification transistor 3 _11.

Then, as shown in FIG. 6, respectively adjacent to the gate electrode 26, 27, 28 and 29, the surface region of the well region 25, the source or drain of each transistor 2 _11, 3 _11, 4 _11, 5 ₁₁ A diffusion layer region 30 is formed.

  Next, for example, as shown in FIG. 7, after an interlayer film 31 is formed on the surface of the P-conductivity type silicon substrate 21, the interlayer film 31 is connected to the gate electrodes 26, 27, 28, 29 and the diffusion layer region 30. A gate contact 36 and a diffusion layer contact 37 are formed. Further, a lower wiring layer 32 connected to the gate contact 36 or the diffusion layer contact 37 is formed on the interlayer film 31. Further, when wiring is also provided on the upper layer of the lower wiring layer 32, after forming the interlayer film 33, an upper wiring layer 34 connected to a contact (not shown) is formed on the interlayer film 33. . An interlayer film 35 is formed on the interlayer film 33 so as to embed an upper wiring layer 34. At this time, the wiring layers 32 and 34 are arranged as a light shielding layer in the gap between the photoelectric conversion layers 39 formed later, which is effective in preventing color mixture and signal leakage between pixels.

  Next, for example, as shown in FIG. 8, a nitride film 38 serving as an etching stopper for the photoelectric conversion layer 39 to be formed later is formed on the interlayer film 35. Then, for example, a TEOS film, which becomes the separation layer 41, is formed thereon. Thereafter, the TEOS film is selectively etched to form the separation layer 41, and at the same time, the recess 39a for forming the photoelectric conversion layer 39 is opened. Further, a contact hole 40a that penetrates part of the nitride film 38 and the interlayer films 31, 33, and 35 and reaches the charge storage section 24 is opened at the bottom of the recess 39a.

  Next, a photo-CVD film such as amorphous silicon is embedded in the recess 39a and the contact hole 40a, and the photoelectric conversion layer 39 and the contact layer 40 are formed simultaneously. As a process for forming the photoelectric conversion layer 39 and the contact layer 40, a process of planarizing the upper surface by CMP (Chemical Mechanical Polishing) after embedding the photo-CVD film is effective. Further, the separation layer 41 may be formed after the photoelectric conversion layer 39 and the contact layer 40 are formed.

Thereafter, as shown in FIG. 9, for example, a transparent electrode 42 such as ITO (Indium Tin Oxide) is formed on the photoelectric conversion layer 39 of all pixels. Further, on the transparent electrode 42, respectively, by performing the formation of the color filter 43 and the microlens 44, MOS sensor is completed with a unit cell 6 ₁₁ having the sectional structure shown in FIG.

  As described above, in a MOS sensor having a structure in which photoelectric conversion is performed by a photoelectric conversion layer, which is different from a photodiode, the photoelectric conversion layer is separated for each pixel by a separation layer. In other words, a stacked amplification type in which photoelectric conversion is performed by a photoelectric conversion layer stacked above a photodiode and a scanning transistor unit (signal readout transistor, amplification transistor, reset transistor, and address transistor) integrated on the same silicon substrate. According to the MOS sensor, the sensitivity characteristic can be increased and the saturation signal amount can be increased. Therefore, even if the pixel is miniaturized and the area of the photodiode is reduced, the size of the pixel becomes the diffraction of light. The pixel characteristics can be maintained until the limit is exceeded, and the ratio of light shot noise to the S / N ratio can be suppressed, and the photoelectric conversion layer is separated for each pixel by the separation layer. As a result, the amount of signal leakage between pixels due to pixel miniaturization and application to single-plate cameras Reduction of color mixing is possible if.

[Second Embodiment]
FIG. 10 shows a configuration example of a unit cell of a MOS sensor (multilayer amplification type solid-state imaging device) including a photoelectric conversion layer having a multilayer structure according to the second embodiment of the present invention. Here, the same parts as those of the MOS sensor (unit cell 6 ₁₁ ) shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

The MOS sensor (unit cell 6 ₁₁ ′) of this embodiment includes a P-conductivity type semiconductor layer (second cell) as shown in FIG. 10 connected to the charge storage unit 24 and the photoelectric conversion layer 39 and the contact layer 40 connecting them. This is different from the MOS sensor shown in the first embodiment in that a conductive type region 51 is provided. The P-conductivity type semiconductor layer 51 can be depleted of electric charges by setting its impurity concentration to, for example, 1E18 to 1E20 cm ⁻³ .

  That is, in the case of the MOS sensor shown in the second embodiment, for example, P conductivity is continuously provided on the surface portion of the charge storage unit 24, the bottom surface portion of the photoelectric conversion layer 39, and the side surface portion of the contact layer 40. A type semiconductor layer 51 is formed. Even with the MOS sensor having such a configuration, the sensitivity characteristic and the amount of saturation signal can be increased, and in addition, the afterimage that causes a problem in the photoelectric conversion layer 39 can be reduced by the capacitive coupling by the PN junction. Become.

  Here, the semiconductor layer 51 is formed by, for example, forming a P-conductivity type layer to be the semiconductor layer 51 in advance on the surface portion (interface) after forming the charge storage layer 24. Then, before embedding the photo-CVD film for forming the photoelectric conversion layer 39 and the contact layer 40, a P conductivity type layer is embedded in the recess 39a and the contact hole 40a. Etching is performed again so that the buried P-conductivity type layer remains only on the bottom surface of the recess 39a and the side surface of the contact hole 40a, and the contact hole for forming the contact layer 40 is reopened. The film may be embedded. The P-conductivity type layer at the contact surface between the contact layer 40 and the charge storage layer 24 can be easily removed by overetching when opening the contact hole 40a or overetching when opening the contact hole again.

Further, as an M0S sensor (unit cell 6 ₁₁ ′) configured by providing a P conductivity type semiconductor layer 51, for example, as shown in FIG. 11, a similar P conductivity type semiconductor layer 52 is also formed on the transparent electrode 42 side. May be provided. In such a configuration, the area of capacitive coupling is expanded, and the saturation signal amount can be further increased.

  In the above-described embodiment, the case where the wiring layer is made of Al has been described as an example. However, the present invention is not limited to this, and for example, a wiring layer made of copper (Cu) may be used. When Cu is used, the wiring layer is formed with a buried (damascene) structure.

  In addition, although the case where the number of wiring layers is two upper and lower layers has been described as an example, two or more wiring layers may be used in consideration of mixed mounting of logic circuits. Of course, only the logic circuit portion can be formed in multiple layers, and the pixel region portion can be formed with a small number of wiring layers from one to three layers. In that case, the photoelectric conversion layer may be embedded.

  Further, the present invention is not limited to a single plate type camera in which a color filter and a microlens are formed for each pixel, and can be applied to other types of cameras.

  Further, the present invention is not limited to the one-pixel / one-cell structure MOS sensor but can be similarly applied to, for example, a two-pixel / one-cell structure MOS sensor.

  In addition, the photoelectric conversion layer is not limited to amorphous silicon, and a photo-CVD film such as amorphous selenium can also be used.

  In addition, the present invention is not limited to the above (each) embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above (each) embodiment includes various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if several constituent requirements are deleted from all the constituent requirements shown in the (each) embodiment, the problem (at least one) described in the column of the problem to be solved by the invention can be solved. When the effect (at least one of the effects) described in the “Effect” column is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.

1 is a circuit block diagram showing a configuration example of a MOS sensor (multilayer amplification type solid-state imaging device) according to a first embodiment of the present invention. The block diagram which shows an example of the unit cell of the MOS sensor according to 1st Embodiment. Process sectional drawing shown in order to demonstrate the manufacturing method of the MOS sensor according to 1st Embodiment. Process sectional drawing shown in order to demonstrate the manufacturing method of the MOS sensor according to 1st Embodiment. Process sectional drawing shown in order to demonstrate the manufacturing method of the MOS sensor according to 1st Embodiment. Process sectional drawing shown in order to demonstrate the manufacturing method of the MOS sensor according to 1st Embodiment. Process sectional drawing shown in order to demonstrate the manufacturing method of the MOS sensor according to 1st Embodiment. Process sectional drawing shown in order to demonstrate the manufacturing method of the MOS sensor according to 1st Embodiment. Process sectional drawing shown in order to demonstrate the manufacturing method of the MOS sensor according to 1st Embodiment. Sectional drawing which shows the structural example of the unit cell of the MOS sensor (laminated amplification type solid-state imaging device) according to 2nd Embodiment of this invention. Sectional drawing which shows the other structural example of a unit cell of the MOS sensor according to 2nd Embodiment.

Explanation of symbols

6 ₁₁ , 6 ₁₁ ′... Unit cell, 21... P conductivity type silicon substrate, 21 a... P conductivity type epitaxial layer, 24... N conductivity type charge storage section, 25. , 29... Gate electrode, 31, 33, 35... Interlayer film, 39... N conductivity type photoelectric conversion layer, 40... N conductivity type contact layer, 41. ... microlens, 51, 52 ... P conductive type semiconductor layer.

Claims (5)

A solid-state imaging device including an imaging region formed by two-dimensionally arranging a plurality of unit cells including a photoelectric conversion unit and a signal scanning circuit unit in a matrix direction on a semiconductor substrate,
The photoelectric conversion unit is
A charge storage layer formed in a surface region of the semiconductor substrate;
A solid-state imaging device, comprising: a photoelectric conversion layer that is stacked above the charge storage layer with an interlayer film interposed therebetween and formed separately for each unit cell. A plurality of signal scanning circuit portions formed in the surface region of the semiconductor substrate;
A charge storage layer embedded in a surface region of the semiconductor substrate, provided near each of the plurality of signal scanning circuit units, and a photoelectric conversion layer stacked above the charge storage layer via an interlayer film Including a plurality of photoelectric conversion units;
A solid-state imaging device comprising: a separation layer for separating the photoelectric conversion layers from each other in units of pixels.   The solid-state imaging device according to claim 1, wherein the separation layer is a film having a light transmittance lower than that of the photoelectric conversion layer. The charge storage layer and the photoelectric conversion layer of the photoelectric conversion unit are connected to each other through a contact layer,
The solid-state imaging device according to claim 1, wherein the charge storage layer, the photoelectric conversion layer, and the contact layer are formed of the same first conductivity type region.   5. The charge storage layer, the photoelectric conversion layer, and the contact layer are further provided with a second conductivity type region having a conductivity type different from that of the first conductivity type region. Solid-state imaging device.

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