KR20060020400A - Fabricating method of cmos image sensor with reduced loss of light - Google Patents

Abstract

The present invention relates to a method for manufacturing a CMOS image sensor, and more particularly, to reduce an optical loss generated at an edge portion of a pixel array by embedding an oxide film having a relatively low refractive index in a peripheral portion of a pixel array to a depth of a second metal wiring. to be. According to the present invention, a method for manufacturing a CMOS image sensor having a pixel array region and a logic region includes: forming up to a second metal wiring in the pixel array region and the logic region, and then forming a fourth metal wiring in the logic region. Forming an interlayer insulating film in the pixel array region; Etching the interlayer insulating layer to form a trench having a depth of the second metal wiring at an interface between the pixel array region and the logic region; And filling the inside of the trench with an oxide film having a lower refractive index than the interlayer insulating film.

CMOS image sensor, refractive index, total reflection, pixel array, light loss

Description

Manufacturing method of CMOS image sensor with reduced light loss {FABRICATING METHOD OF CMOS IMAGE SENSOR WITH REDUCED LOSS OF LIGHT}             

1A is a circuit diagram showing a unit pixel of a conventional CMOS image sensor;

Figure 1b is a view showing a schematic structure of a CMOS image sensor chip according to the prior art,

Figure 1c is a cross-sectional view showing a cross-sectional view of the pixel array portion and the logic region in the CMOS image sensor according to the prior art,

2A to 2C are cross-sectional views illustrating a manufacturing process of a CMOS image sensor according to an embodiment of the present invention;

Figure 2d is a plan view showing a state of the CMOS image sensor chip according to an embodiment of the present invention,

3 is a cross-sectional view showing a case where the technical idea of the present invention is applied to a unit pixel;

* Description of the symbols for the main parts of the drawings *

30 substrate 31 gate

32 spacer 33 interlayer insulating film                 

34: M1 contact 35: first metal wiring (M1)

36: VIA 1 37, 39, 42: interlayer insulating film

38: second metal wiring (M2) 40: VIA 2

41: third metal wiring (M3) 43: VIA3

44: fourth metal wiring (M4) 45: mask

46: trench 47: oxide film

50 substrate 51 photodiode

52: gate 53: spacer

54: interlayer insulating film 55, 56: metal interlayer insulating film

57: oxide film

The present invention relates to a method for manufacturing a CMOS image sensor, and in particular, by filling an oxide film in the edge region between a pixel array and a logic circuit to a depth of a second metal wiring, the light reflected by the oxide film is totally received by the pixel array Invention is reduced the loss of light.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and representative image sensor devices include a charge coupled device (CCD) and a CMOS image sensor.

Among them, the charge-coupled device is a device in which charge carriers are stored and transported in the capacitor while individual metal-oxide-silicon (MOS) capacitors are located very close to each other, and the CMOS image sensor is a control circuit and a signal processing circuit. It is a device that adopts a switching method that uses a CMOS technology that uses a signal processing circuit as a peripheral circuit to make MOS transistors by the number of pixels and sequentially detects the output using the same.

FIG. 1A is a circuit diagram showing a unit pixel composed of one photodiode (PD) and four MOS transistors in a conventional CMOS image sensor, and includes a photodiode 100 for generating photocharges by receiving light. A transfer transistor 101 for transporting the photocharges collected from the photodiode 100 to the floating diffusion region 102, and resets the floating diffusion region 102 by setting a potential of the floating diffusion region to a desired value and discharging electric charge. A reset transistor 103 for supplying voltage, a drive transistor 104 serving as a source follower buffer amplifier by applying a voltage of a floating diffusion region to a gate, and an addressing role as a switching role. It consists of a select transistor 105 that performs the following. Outside the unit pixel, a load transistor 106 is formed to read an output signal.

FIG. 1B is a plan view schematically illustrating a CMOS image sensor chip including a pixel array including tens to millions of such unit pixels, a logic circuit unit for processing image data, and the like. Referring to this, it can be seen that the logic circuit unit is disposed around the pixel array receiving the light.

FIG. 1C is a cross-sectional view illustrating a cross section of a pixel array and a logic circuit unit. In particular, FIG. 1C illustrates a boundary of the pixel array and a logic circuit unit. Referring to FIG.

First, in FIG. 1C, a pixel array region and a logic region are shown together. A pixel array region is a region in which a light receiving unit formed of a photodiode or the like is formed, and a logic region is a portion in which a general logic circuit for signal processing is mainly formed. to be.

That is, the gate electrode 12 having the spacers 13 is formed on the semiconductor substrate 11, and the interlayer insulating film 14 for insulation is formed on the substrate including the gate electrode. A metal contact 15 (M1 contact) is formed on the gate electrode 12 to connect the gate electrode 12 and the first metal wiring 16 through the interlayer insulating layer 14.

In addition, a first metal wiring 16 is patterned on the interlayer insulating film 14, and second to fourth metal wirings 18, 20, and 22 are stacked on top of each other, and metal wiring is formed between the metal wirings. Each metal interlayer insulating film (not shown) is provided for insulating them. Here, it can be seen that the metal interlayer insulating film has a structure in which an FSG film and a TEOS oxide film are stacked in a typical manner. In addition, FIG. 1C shows VIA 1 to VIA 3 for electrically connecting each metal wiring.

Referring to FIG. 1C, it can be seen that in the conventional CMOS image sensor, the pixel array region is formed only up to the second metal wiring M2 18, and the logic region is formed up to the fourth metal wiring 22.

That is, in the pixel array region formed only up to the second metal wirings M2 and 18, two layers of the oxide film-based FGS film and the TEOS oxide film are formed, so as to match the height of the fourth metal wiring of the logic region.

In the conventional image sensor having such a structure, the fourth metal wiring 22 of the logic region is formed of a shielding metal to surround the pixel array region, which indicates a boundary between the pixel array region and the logic region and at the same time the pixel array. It was also intended to reduce the loss of light incident on the edge of the area.

However, according to the related art, the shielding metal using the fourth metal wire does not collect incident light incident to the edge toward the pixel array, and has a disadvantage in that it is almost lost due to the imaginary part dielectric constant of the metal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for manufacturing a CMOS image sensor which reduces light loss at the edge portion of the pixel array and further reduces the difference in light sensitivity between the center portion and the edge portion of the pixel array. .

The present invention for achieving the above object, in the method for manufacturing a CMOS image sensor having a pixel array region and a logic region, after forming up to a second metal wiring in the pixel array region and the logic region, the logic region Forming up to a fourth metal wiring on the substrate and forming an interlayer dielectric in the pixel array region; Etching the interlayer insulating layer to form a trench having a depth of the second metal wiring at an interface between the pixel array region and the logic region; And filling the inside of the trench with an oxide film having a lower refractive index than the interlayer insulating film.

In the present invention, the oxide-based film is buried at the interface between the pixel array and the logic region to the depth of the second metal wiring, and the incident light is totally reflected by the oxide-based film to be incident toward the pixel array, thereby preventing light loss and preventing the pixel array. It was possible to improve the light sensitivity of the edge portion of the.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

2A through 2C are cross-sectional views illustrating a manufacturing process of a CMOS image sensor according to an exemplary embodiment of the present invention, with reference to this description.

First, the process up to forming the fourth metal wiring 44 is the same as in the prior art.

Referring to this, first, an isolation layer defining an active region and a field region is formed on a semiconductor substrate having a pixel array region and a logic region. This device isolation film is not shown in Fig. 2A.

Next, a photodiode is formed in the pixel array region. The photodiode is also not shown in FIG. 2A. Next, a gate electrode 31 having a spacer 32 is formed on the semiconductor substrate, and a source / drain region (not shown) is formed.

Next, after the interlayer insulating film 33 is formed on the substrate 30 including the gate electrode 31, a portion of the interlayer insulating film 33 is removed and a conductive material is embedded to fill the gate electrode 31 and the first metal. A metal contact 34 connecting the wiring 35 is formed.

Subsequently, after the first interlayer dielectric layer 37 is formed on the first metal interconnection 35, the first interlayer dielectric layer 37 penetrates the first metal interconnection and the second metal interconnection. Vias VIA 1 36 are formed.

Next, the second metal wiring 38 is patterned on the first metal interlayer insulating film 37.

This process is the same in both the pixel array region and the logic region, but subsequent processes are performed differently in the pixel array region and the logic region.

That is, in the logic region, a process of sequentially stacking the third metal wiring 41 and the fourth metal wiring 44 proceeds, whereas in the pixel array region, only the interlayer insulating films 39 and 42 are sequentially stacked and no more metal is stacked. Wiring is not used.

In FIG. 2A, reference numerals 40 and 43 represent VIA 2 and VIA 3, respectively.

After the fourth metal wiring 44 is formed as described above, the trench 46 is formed on the interface between the pixel array region and the logic region using the mask 45. At this time, the depth of the trench is up to the second metal wiring 38, the depth of the trench in the 0.18㎛ class CMOS image sensor is preferably about 16000Å.

Next, as shown in Fig. 2B, an oxide film 47 is deposited on the entire structure to fill the trench.

Here, the oxide film 47 has a low refractive index of about 1.41, and has a relatively low refractive index than the interlayer insulating film on the pixel array side. Thus, in one embodiment of the present invention it was possible to reduce the light loss at the interface through the total reflection using the oxide film 47.

After depositing the oxide film 47 in this manner, as shown in FIG. 2C, an etchbeck process is performed on the oxide film 47 until the surface of the fourth metal wire 44 is exposed. An oxide film remains in the form of a spacer, and the trench is filled with an oxide film. At this time, the thickness of the fourth metal wiring is about 6500 kW.

Thereafter, although not shown in FIG. 2C, the CMOS image sensor is completed by performing a conventional process such as a passivation film, a color filter, and microlens formation.

As a result, since an oxide film having a low refractive index is buried in the periphery of the pixel array, light incident on the interface between the pixel array region and the logic region is totally reflected by the oxide film and reincident to the pixel array region.

In the present invention, the light sensitivity at the edge portion of the pixel array can be improved by using this point, and the difference in light sensitivity between the center portion and the edge portion of the pixel array can be reduced.                     

FIG. 2D is a plan view illustrating a CMOS image sensor chip formed according to an exemplary embodiment of the present invention, and it can be seen that an oxide film 47 having a low refractive index is buried along an edge of a pixel array.

3 is a cross-sectional view showing a state in which the technical idea of the present invention is applied to a unit pixel. That is, FIG. 3 is a diagram illustrating a cross section of one unit pixel, and will be described with reference to the drawing.

First, it is the same as the first embodiment of the present invention until the second metal wiring M2 is formed. That is, the photodiode 51 which receives light and converts it into an electrical signal is formed in the semiconductor substrate 50, and the gate electrode 52 provided with the spacer 53 is formed.

In addition, an interlayer insulating film 54 is formed on the semiconductor substrate 50 including the gate electrode, and the first metal wiring M1 and the second metal wiring laid out so as not to block a path of light incident on the photodiode on the interlayer insulating film. M2 is formed.

Reference numerals 54 and 55 are metal interlayer insulating films.

After the second metal wiring M2 is formed in this manner, a process of covering the upper portion with the metal interlayer insulating film 56 is performed. Thereafter, the metal interlayer insulating layer 56 is etched to form a trench, but the trench is formed at a position corresponding to the circumference of the photodiode.

Next, when the trench is filled with the oxide film 57 having a low refractive index, the buried oxide film 57 serves to induce total reflection to prevent loss of light incident to the photodiode.                     

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

When the present invention is applied to the CMOS image sensor, it is possible not only to reduce the light loss generated at the edge portion of the pixel array, but also to reduce the light sensitivity difference between the center portion and the edge portion of the pixel array.

Claims (3)

In the method of manufacturing a CMOS image sensor having a pixel array region and a logic region, Forming a second metal wiring in the pixel array region and the logic region, and then forming a fourth metal wiring in the logic region and forming an interlayer insulating layer in the pixel array region; Etching the interlayer insulating layer to form a trench having a depth of the second metal wiring at an interface between the pixel array region and the logic region; And Filling the inside of the trench with an oxide film having a lower refractive index than the interlayer insulating film Method of manufacturing a CMOS image sensor comprising a. The method of claim 1, Filling the inside of the trench with an oxide film having a lower refractive index than the interlayer insulating film; Stacking an interlayer insulating film including the trench and an oxide film having a lower refractive index than the interlayer insulating film on the fourth metal wiring; And Performing an etchbeck process until the fourth metal wiring is exposed; Method of manufacturing a CMOS image sensor comprising a. The method of claim 1, Filling the inside of the trench with an oxide film having a lower refractive index than the interlayer insulating film; The refractive index of the oxide film is a manufacturing method of the CMOS image sensor, characterized in that.

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