KR20100078210A - Image sensor and method for manufacturing the same - Google Patents

Abstract

PURPOSE: An image sensor and a manufacturing method thereof are provided to improve a fill factor by vertically integrating a readout circuit with a photo diode. CONSTITUTION: A substrate includes an electric junction region, a transistor, and a wiring. The wiring connects an electric junction region or transistor. A photo diode(200) is formed on the substrate. A via hole passes through a photo diode and exposes the part of the wiring. An ion implantation layer(250) is formed on the sidewall of the via hole. A metal contact(260) is formed inside the via hole and connects the wiring layer with the impurity region of the photo diode. An ion implantation layer is formed on the upper side of the photo diode and the sidewall of the via hole.

Description

Image sensor and method for manufacturing the same

This embodiment discloses an image sensor and a method of manufacturing the same.

The CMOS image sensor according to the related art has a structure in which a photodiode is disposed horizontally with a transistor.

Of course, although the disadvantages of the CCD image sensor have been solved by the horizontal CMOS image sensor according to the prior art, there are still problems with the horizontal CMOS image sensor according to the prior art.

That is, according to the horizontal CMOS image sensor of the prior art, a photodiode and a transistor are manufactured to be adjacent to each other horizontally on a substrate. Accordingly, an additional area for the photodiode is required, thereby reducing the fill factor area and also limiting the possibility of resolution.

In addition, according to the horizontal CMOS image sensor according to the prior art there is a problem that it is very difficult to achieve the optimization for the process of manufacturing a photodiode and a transistor at the same time. That is, in a fast transistor process, a shallow junction is required for low sheet resistance, but such a shallow junction may not be appropriate for a photodiode.

In addition, according to the horizontal CMOS image sensor according to the prior art, the size of the unit pixel is increased to maintain the sensitivity of the image sensor as additional on-chip functions are added to the image sensor, or The area for the photodiode must be reduced to maintain the pixel size.

However, when the pixel size is increased, the resolution of the image sensor is reduced, and when the area of the photodiode is reduced, the sensitivity of the image sensor is reduced.

An embodiment of the present invention is to provide an image sensor and a method of manufacturing the same that can provide a new integration of the circuit (circuitry) and photodiode.

An embodiment of the present invention is a logic chip consisting of an image chip for forming a color filter array and a micro lens after forming a photodiode using two chips, a driver IC for driving the same, and a logic array for providing additional functions. The present invention is to provide an image sensor and a method of manufacturing the same that can be three-dimensional integration of the image chip and logic chip using a single pad.

In addition, an image sensor and a manufacturing method thereof capable of reducing dark current by improving a dangling bond that may be generated due to etching of a photodiode are proposed.

An image sensor according to the present embodiment includes a substrate having an electrical junction region and a transistor, and a wiring connecting the electrical junction region or the transistor; A photodiode formed on the substrate; A via hole penetrating the photodiode and exposing a portion of the wiring; An ion implantation layer formed on sidewalls of the via hole; And a metal contact formed in the via hole and connecting the wiring layer and an impurity region of the photodiode.

In addition, the manufacturing method of the image sensor according to the present embodiment includes the steps of forming a circuit including a wiring on a semiconductor substrate; Forming an interlayer insulating layer on the substrate; Forming a photodiode on the interlayer insulating layer and forming a via hole in the photodiode to expose a portion of the wiring; Forming an ion implantation layer by implanting impurities into the via hole or the top surface of the photodiode; And forming a metal contact connected to the wire in the via hole.

According to the image sensor of the present embodiment and a method of manufacturing the same, a vertical integration of the readout circuit and the photodiode can be achieved, thereby improving the fill factor.

In addition, there is an advantage that can be bonded to the interlayer insulating layer on which the photodiode is formed to improve the physical bonding strength of the bonding surface.

In addition, since the ion implantation layer is formed on the sidewall of the via hole through which the photodiode is exposed, the dangling bond that may be formed on the sidewall of the via hole may be reduced, thereby improving dark current characteristics. .

Hereinafter, with reference to the accompanying drawings for the present embodiment will be described in detail. However, the scope of the idea of the present invention may be determined from the matters disclosed by the present embodiment, and the idea of the invention of the present embodiment may be performed by adding, deleting, or modifying components to the proposed embodiment. It will be said to include variations.

In the following description, the word 'comprising' does not exclude the presence of other elements or steps than those listed. In addition, in the accompanying drawings, the thickness thereof is enlarged in order to clearly express various layers and regions. In addition, the same reference numerals are used for similar parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only being another part "on top" but also having another part in the middle.

First, an image sensor configuration of an embodiment will be described with reference to FIGS. 1 and 9.

For reference, FIG. 9 illustrates the interlayer insulating layer 160 and the third metal 153 illustrated in FIG. 1, and circuits 120 and wirings provided under the interlayer insulating layer 160. Etc. are omitted, so it is necessary to refer to this point.

1 and 9, an image sensor of an embodiment includes a semiconductor substrate 100 including a circuit 120, a wiring 150 and an interlayer insulating layer 160 connected to the circuit 120. And a photodiode 200 formed on the interlayer insulating layer 160 and having an ohmic contact layer 230, a first doped layer 210, and a second doped layer 220 stacked thereon, and the photodiode ( Vias 245 (see FIG. 8) exposing the wiring 150 through the interlayer insulating layer 160 and the interlayer insulating layer 160, and ions formed on an upper surface of the photodiode 200 and sidewalls of the via holes 245. The metal contact 260 and the via hole 245 formed in the via hole 245 so that the injection layer 250 and the ohmic contact layer 230 or the first doped layer 210 are connected to the wiring 150. ) Includes a protective layer 270 formed on the metal contact 260 to gap fill the gaps.

The ion implantation layer 250 may be formed of hydrogen ions (H ₂ ). The ion implantation layer 250 is to reduce the detection of the photodiode that may be generated during the etching process of the photodiode 200 for forming the metal contact 260, and hydrogen (H ₂ ) ion Implanted area. Due to the ion implantation layer 250, it is possible to reduce the occurrence of dangling bonds of the photodiode 200 formed on both sides or below the ion implantation layer 250.

The metal contact 260 may be formed in the via hole 245 to be electrically connected to the ohmic contact layer (N +) 230 or the first doped layer (N−) 210. That is, the metal contact 260 is separated from the second doped layer 220 so as not to be electrically connected to each other, and thus, the photoelectric charge generated by the photodiode 200 is connected to the metal contact 260 and the wiring ( 150 may be transferred to the circuit 120.

The protective layer 270 is formed to gap-fill the via hole 245 corresponding to the upper portion of the metal contact 260. The protective layer 270 may be formed on the upper surfaces of the metal contact 260 and the photodiode 200 to protect the device. In addition, the protective layer 270 may be formed on the metal contact 260 to physically or electrically separate the metal contact 260 and the second doped layer 220. For example, the pore layer 270 may be formed of an insulating film such as an oxide film or a nitride film.

The pixel isolation layer 280 is formed inside the photodiode 200 corresponding to the metal contacts 260 so that the photodiode 200 is separated by unit pixels. The pixel isolation layer 280 may be formed of an insulating film such as an oxide film or a nitride film to separate the photodiode 200 for each pixel.

Unexplained reference numerals among the reference numerals of FIGS. 1 and 9 will be described in the following manufacturing method.

Hereinafter, a method of manufacturing an image sensor according to an embodiment will be described with reference to FIGS. 1 to 9.

First, referring to FIG. 1, the wiring 150 and the interlayer insulating layer 160 are formed on the semiconductor substrate 100 including the circuit 120.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. An isolation layer 110 is formed on the semiconductor substrate 100 to define an active region. A circuit 120 including transistors for each unit pixel is formed in the active region.

The circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. Meanwhile, the readout circuit 120 may be applied to a 3Tr or 5Tr structure.

The forming of the circuit 120 on the semiconductor substrate 100 may include forming an electrical junction region 140 on the semiconductor substrate 100, and forming the wiring 150 on the electrical junction region 140. The method may include forming a first conductive connection region 147 to be connected.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical bonding region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 1, but is not limited thereto. In addition, the semiconductor substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a potential difference between the source and the drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, by forming an electrical junction region 140 in the semiconductor substrate 100 on which the readout circuit 120 is formed, there is a voltage difference between the source / drain across the transfer transistor (Tx) 121 so as to completely dump the photocharge. This can be made possible.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail with reference to FIGS. 1 and 2.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 200 are moved to the PNP caption 140, and when the transfer transistor Tx 121 is turned on, the electrons are transferred to the FD 131 node and converted into voltages.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the node FD 131 becomes Vdd-Rx Vth, as shown in FIG. 2, the potential difference between both ends of the Tx 131 is shown. Due to this, electrons generated from the photodiode on the chip may be completely dumped to the FD 131 node without charge sharing.

That is, in the embodiment, the reason why the P0 / N- / Pwell junction is formed instead of the N + / Pwell junction in the silicon sub (Si-Sub) of the semiconductor substrate 100 is the reason for the 4-Tr APS Reset operation. In P0 / N- / Pwell junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and Pwell (141), so P0 / N- / Pwell is above a certain voltage. Double junction causes pinch-off as in BJT structure. This is called a pinning voltage. Therefore, a voltage difference occurs between the source / drain at both ends of the Tx 121, and thus, photocharge is fully dumped from the N-well to the FD through the Tx at the N-well, thereby preventing charge sharing.

Therefore, unlike the case where the photodiode is simply connected with N + junction in the general technology, problems such as degradation of saturation and degradation of sensitivity may be avoided according to the embodiment.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the circuit 120 to make a smooth moving path of the photo charge, thereby minimizing the dark current source and saturation. It is possible to prevent degradation of saturation and degradation of sensitivity.

To this end, the embodiment may form an N + doped region as the first conductivity type connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized.

To this end, the embodiment may proceed with a plug implant after etching the second metal contact 151a, but is not limited thereto. For example, an ion implantation pattern (not shown) may be formed and the first conductive connection region 147 may be formed using the ion implantation mask as an ion implantation mask.

That is, the reason for N + doping locally only in the contact forming part as in the embodiment is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

3 shows another structure for the circuit. As shown in FIG. 3, a first conductive connection region 148 may be formed on one side of the electrical junction region 140.

Referring to FIG. 3, an N + connection region 148 for ohmic contact may be formed in the P0 / N− / P− junction 140, where the N + connection region 148 and the M1C contact 151a are formed. The formation process may be a leakage source. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. Crystal defects that occur during the contact formation process in the electric field become a liquid source.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-Field by the N + / P0 junction (148/145) is added. Can be a Leakage Source.

That is, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with the P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is presented.

Then, the E-Field of the surface of the semiconductor substrate 100 does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

Referring back to FIG. 1, an interlayer insulating layer 160 and a wiring 150 may be formed on the semiconductor substrate 100. The wiring 150 may include a second metal contact 151a, a first metal 151, a second metal 152, and a third metal 153, but is not limited thereto. In an embodiment, after forming the third metal 153, an insulating film may be deposited so that the third metal 153 is not exposed, and then a planarization process may be performed to form the interlayer insulating layer 160. Therefore, the surface of the interlayer insulating layer 160 having a uniform surface profile may be exposed on the semiconductor substrate 100.

Next, referring to FIG. 4, a photodiode 200 is formed on the interlayer insulating layer 160. The photodiode 200 may have a PN junction photodiode structure including a first doped layer 210 and a second doped layer 220.

In addition, the photodiode 200 may include an ohmic contact layer 230 formed under the first doped layer 210. For reference, the third metal 153 and the interlayer insulating layer 160 of the wiring 150 illustrated in FIG. 4 represent a part of the wiring and the interlayer insulating layer 160 illustrated in FIG. 1. Some of the circuit 120 and the wiring 150 are omitted.

The photodiode 200 is sequentially implanted with P-type impurities (P +) and N-type impurities (N−) into a carrier substrate (not shown), which is a silicon wafer having a crystalline structure, on the second doped layer 220. The first doped layer 210 may be formed in a stacked structure. In addition, an ohmic contact layer 230 may be formed by ion implanting a high concentration of N-type impurities (N +) into a shallow region of the carrier substrate so as to contact the first doped layer 210. The ohmic contact layer 230 may lower the contact resistance between the photodiode 200 and the wiring 150.

In an embodiment, the first doped layer 210 may be formed to have a wider area than the second doped layer 220. The depletion region can then be expanded to increase the production of photoelectrons.

The ohmic contact layer 230 of the carrier substrate is positioned to face the upper surface of the interlayer insulating layer 160, and then the bonding process is performed to bond the semiconductor substrate 100 to the carrier substrate. Accordingly, the photodiode 200 may have a structure in which an ohmic contact layer 230, a first doped layer 210, and a second doped layer 220 are stacked on the interlayer insulating layer 160. Thereafter, the carrier substrate on which the hydrogen layer (not shown) is formed to expose the photodiode 200 bonded on the interlayer insulating layer 160 is removed by heat treatment or mechanical impact, so as to expose the second doped layer 220. To expose the surface.

Accordingly, the photodiode 200 may be formed on the readout circuit 120 to prevent a defect of the photodiode 200 while increasing a fill factor. In addition, since the photodiode 200 is bonded on the interlayer insulating layer 160 having a uniform surface profile, physical bonding force may be improved.

Meanwhile, in the embodiment, the photodiode 200 is formed to have a PN junction, but the photodiode 200 may be formed to have a PIN junction.

Next, referring to FIG. 5, a hard mask 240 is formed on the photodiode 200. The hard mask 240 may selectively expose the surface of the photodiode 200 corresponding to the third metal 153.

For example, the hard mask 240 may be formed in a triple structure of an oxide film-nitride film-oxide film. The hard mask 240 is used because the photodiode 200 formed on the silicon wafer is difficult to etch with a general photosensitive material. In particular, since the ONO structure hard mask 240 has a high etching selectivity with a silicon wafer, the photodiode 200 may be selectively etched.

The hard mask 240 may form a hard mask layer (not shown) of the ONO structure on the photodiode 200 and then selectively expose the surface of the photodiode 200 by photolithography and etching. .

A via hole 245 is formed through the photodiode 200 and the interlayer insulating layer 160 to expose the third metal 153. The via hole 245 may be formed by performing an etching process using the hard mask 240 as an etching mask. For example, the via hole 245 may be formed through a dry or wet etching process. Defects are generated on surfaces of the first doped layer 210, the second doped layer 220, and the ohmic contact layer 230 exposed by the via hole 245 during the etching process for forming the via hole 245. Can be. Since such defects may cause dangling bonds and later cause dark currents, improvement of defects in the sidewalls of the via holes 245 may be required.

Thereafter, the hard mask 240 may be removed.

Next, referring to FIG. 6, a hydrogen ion implantation process is performed on the entire surface of the photodiode 200 including the via hole 245, where the hydrogen ion implantation process is a dangling bond due to defects in the photodiode. This is to reduce the.

That is, a process of injecting hydrogen (H ₂ ) impurities into the photodiode 200 having the via hole 245 is performed to inject hydrogen impurities on the etched portion of the photodiode and the photodiode by a predetermined thickness. Be sure to

After performing the hydrogen impurity implantation process, the annealing process may be further performed.

In this case, by implanting hydrogen impurity ions, Si atoms constituting the surface of the photodiode 200 and hydrogen (H ₂ ) atoms may be combined to improve defects on the sidewalls of the via hole 245.

Next, referring to FIG. 7, an ion implantation layer 250 is formed on the photodiode 200 on the sidewall of the via hole 245 and the upper surface of the photodiode 200 by the hydrogen impurity implantation process.

As described above, since the ion implantation layer 250 is formed on the upper surface of the photodiode 200 and the sidewalls of the via holes 245, the dark current characteristics due to the dangling bond may be improved.

Although not shown, the ion implantation layer 250 may be formed by ion implanting hydrogen (H ₂ ) ions into the sidewall of the via hole 245.

Next, referring to FIG. 8, a metal contact 260 is formed in the via hole 245. The metal contact 260 may be formed in the via hole 245 to electrically connect the photodiode 200 and the circuit 120. The metal contact 260 is formed inside the via hole 245 only up to the height of the ohmic contact layer 230 or the first doped layer 210 of the photodiode 200 and is different from the second doped layer 220. To be separated.

For example, the metal contact 260 may include tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta) titanium (Ti), titanium nitride (TiN), Ti / TiN, and copper (Cu). It may be formed of any one of a metal material such as.

The metal contact 260 deposits a metal layer (not shown) into the via hole 245 and then performs an etching process so that the metal layer does not remain inside the via hole 245 corresponding to the second doped layer 220. It can be formed to proceed.

Accordingly, the ohmic contact layer 230 or the first doped layer 210 may be electrically connected to the third metal 153 by the metal contact 260. In addition, the metal contact 260 may be electrically and physically separated from the second doped layer 220.

Next, referring to FIG. 9, a protective layer 270 is formed on the metal contact 260. The protective layer 270 may be formed by depositing an insulating film, such as an oxide film or a nitride film, on the photodiode 200 so as to gap fill the via hole 245 in which the metal contact 260 is formed. The protective layer 270 may be formed until the via hole 245 is gapfilled. Alternatively, the protective layer 270 may be formed so that the upper surface of the photodiode 200 is not exposed.

Since the passivation layer 270 is formed in the via hole 245 formed on the metal contact 260, the second doped layer 220 of the metal contact 260 and the photodiode 200 is formed. It can be electrically or physically separated.

Accordingly, the metal contact 260 for transferring the photocharge generated by the photodiode 200 to the circuit 120 may be physically or electrically only in the ohmic contact layer 230 or the first doped layer 210. Since the image sensor is in contact, the image sensor can output a normal signal.

This prevents the photodiode from being shorted because the metal contact 260 is physically separated by the second doping layer 220 and the protective layer 270 and is only connected to the first doping layer 210. Because it can.

Next, a pixel separation layer 280 is formed to separate the photodiode 200 for each unit pixel. The pixel separation layer 280 may be formed by an STI or an ion implantation process. For example, the pixel isolation layer 280 penetrates through the passivation layer 270 and the photodiode 200 corresponding to the metal contact 260, and then forms an trench to gap fill the trench. It may be formed by gap filling an insulating material such as a nitride film.

Although not shown, an upper electrode, a color filter, and a micro lens may be formed on the photodiode 200.

In example embodiments, a photodiode may be formed on the semiconductor substrate on which the readout circuit is formed to increase the fill factor.

In addition, since the photodiode is bonded on the interlayer insulating layer having a flat profile, physical bonding force may be improved.

In addition, an ion implantation layer is formed on a sidewall of the via hole through which the wiring is exposed to pass through the photodiode, thereby improving dark current characteristics by removing the dangling bond formed on the sidewall of the via hole.

In addition, the metal contact formed inside the via hole may be electrically connected only to the ohmic contact layer of the photodiode, so that the photocharge signal input and output generated by the photodiode may be efficiently performed.

The above-described embodiments are not limited to the above-described embodiments and drawings, and it is common in the technical field to which the present embodiments belong that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be apparent to those who have

1 to 9 are views for explaining the configuration of the image sensor and the manufacturing method thereof according to the present embodiment.

Claims (11)

A substrate having an electrical junction region and a transistor, and wirings connecting the electrical junction region or the transistor; A photodiode formed on the substrate; A via hole penetrating the photodiode and exposing a portion of the wiring; An ion implantation layer formed on sidewalls of the via hole; And And a metal contact formed in the via hole and connecting the wiring layer and an impurity region of the photodiode. The method of claim 1, The ion implantation layer is formed on the sidewall of the via hole and the top surface of the photodiode. The method according to claim 1 or 2, The ion implantation layer is an image sensor implanted with hydrogen impurities. The method of claim 1, The photodiode includes an ohmic contact layer connected to the metal contact, and a first doping layer and a second doping layer formed on the ohmic contact layer. The method of claim 1, The protective layer is gap-filled in the via hole formed with the metal contact. The method of claim 5, The protective layer is an image sensor consisting of an oxide film. Forming a circuit including wiring on the semiconductor substrate; Forming an interlayer insulating layer on the substrate; Forming a photodiode on the interlayer insulating layer and forming a via hole in the photodiode to expose a portion of the wiring; Forming an ion implantation layer by implanting impurities into the via hole or the top surface of the photodiode; And And forming a metal contact connected to the wire in the via hole. The method of claim 7, wherein Forming the ion implantation layer, And forming an ion implantation layer on the sidewalls of the via holes and on the photodiodes by implanting hydrogen impurities into the via holes and the photodiode top surface. The method of claim 7, wherein The photodiode includes an ohmic contact layer connected to the metal contact, a first doped layer formed on the ohmic contact layer, and a second doped layer formed on the first doped layer, Forming the metal contact, And forming the metal contact by partially removing a metal formed on one side of the second doped layer among the metals gapped in the via hole. The method of claim 7, wherein After forming the metal contact, And forming a protective layer in the via hole so that the via hole is gap-filled. The method of claim 10, Forming the protective layer, Forming a protective layer by gap-filling an oxide film in the via hole and then planarizing an upper portion of the oxide film.

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