KR20100012646A - Image sensor and method for manufacturing thereof - Google Patents

Abstract

PURPOSE: An image sensor and a method for manufacturing thereof are provided to prevent the decline of sensitivity and saturation by making a path for a photo charge through a charge connection area. CONSTITUTION: A readout circuit(120) and an interlayer dielectric layer(160) are formed in a first substrate(100). A wiring is formed an interlayer dielectric layer and is electrically connected to the readout circuit. An image sensing device(210) is formed on the bottom electrode(205). The image sensing device comprises a first conductive layer, an intrinsic layer, and a second conductive layer. A pixel dielectric isolation layer(207) is formed on the image sensing device as much as the height of the first conductive layer.

Description

Image sensor and method for manufacturing

Embodiments relate to an image sensor and a manufacturing method thereof.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is divided into a charge coupled device (CCD) and a CMOS image sensor (CIS). do.

In the prior art, a photodiode is formed on a substrate by ion implantation. However, as the size of the photodiode gradually decreases for the purpose of increasing the number of pixels without increasing the chip size, the image quality decreases due to the reduction of the area of the light receiver.

In addition, since the stack height is not reduced as much as the area of the light receiving unit is reduced, the number of photons incident on the light receiving unit is also decreased due to diffraction of light called an airy disk.

One alternative to overcome this is to deposit photodiodes with amorphous Si, or read-out circuitry using wafer-to-wafer bonding such as silicon substrates. And photodiodes are formed on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and lead-out circuit are connected via a metal line.

On the other hand, according to the prior art there is a problem that the interference phenomenon between the photodiode occurs.

In addition, according to the related art, since both the source and the drain of both ends of the transfer transistor are doped with a high concentration of N-type, charge sharing occurs. When charge sharing occurs, the sensitivity of the output image is lowered and image errors may occur.

In addition, according to the related art, a dark current is generated between the photodiode and the lead-out circuit and the photocharge is not smoothly moved, and saturation and sensitivity are decreased.

Embodiments provide an image sensor and a method of manufacturing the same that can prevent an image from being distorted by photodiode interference around one photodiode while increasing the fill factor.

In addition, the embodiment is to provide an image sensor and a method of manufacturing the same that can increase the charge factor (Charge Sharing) does not occur.

In addition, the embodiment of the present invention provides an image sensor capable of minimizing dark current sources and preventing saturation and degradation of sensitivity by creating a smooth movement path of photo charge between the photodiode and the lead-out circuit. To provide a manufacturing method.

The image sensor according to the embodiment includes a readout circuitry formed on the first substrate; An interlayer insulating layer formed on the first substrate; A wiring formed on the interlayer insulating layer and electrically connected to the lead-out circuit; A lower electrode formed on the wiring; A pixel isolation insulating layer formed on both sides of the lower electrode; And an image sensing unit formed on the lower electrode.

In addition, the manufacturing method of the image sensor according to the embodiment comprises the steps of forming a readout circuitry (Readout Circuitry) on the first substrate; Forming an interlayer insulating layer on the first substrate; Forming a wire electrically connected to the lead-out circuit in the interlayer insulating layer; Forming a lower electrode on the wiring; Forming a first insulating layer on the lower electrode; Partially etching the first insulating layer to form a pixel isolation insulating layer on both sides of the lower electrode; And forming an image sensing unit on the lower electrode.

According to the image sensor and the method of manufacturing the same according to the embodiment, it is possible to prevent the generation of the interference by preventing the electrons generated between the pixels by forming a pixel isolation insulating layer between the pixels.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. It can prevent.

Hereinafter, an image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

The present invention is not limited to the CMOS image sensor, and may be applied to an image sensor requiring a photodiode.

(First embodiment)

1 is a cross-sectional view of an image sensor according to a first embodiment.

The image sensor according to the first embodiment includes a readout circuitry 120 formed on the first substrate 100; An interlayer insulating layer 160 formed on the first substrate 100; A wiring 150 formed in the interlayer insulating layer 160 to be electrically connected to the lead-out circuit 120; A lower electrode 205 formed on the wiring 150; A pixel isolation insulating layer 207 formed on both sides of the lower electrode 205; And an image sensing unit 210 formed on the lower electrode 205.

The image sensing unit 210 may be a photodiode, but is not limited thereto and may be a photogate, a combination of a photodiode and a photogate, and the like. On the other hand, the embodiment is not limited to this example, but the photodiode is formed of amorphous silicon.

Unexplained reference numerals among the reference numerals of FIG. 1 will be described in the following manufacturing method.

Hereinafter, a manufacturing method of an image sensor according to an exemplary embodiment will be described with reference to FIGS. 2 to 9.

FIG. 2 is a schematic diagram illustrating a wiring 150, a reset wiring 155, and a bonding pad 157 formed on the first substrate 100, and FIG. 3 illustrates the wiring 150, the lead-out circuit 120, and the electrical junction region ( 140). A description with reference to FIG. 3 is as follows.

First, as shown in FIG. 3, the first substrate 100 on which the wiring 150 and the readout circuit 120 are formed is prepared. For example, the isolation layer 110 is formed on the second conductive first substrate 100 to define an active region, and a readout circuit 120 including a transistor is formed in the active region. For example, the readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. can do. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. In addition, according to the embodiment, the noise can be improved by adding a noise removing circuit (not shown).

The forming of the lead-out circuit 120 on the first substrate 100 may include forming an electrical junction region 140 on the first substrate 100 and forming an interconnection on the electrical junction region 140. And forming a first conductivity type connection region 147 connected to 150.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 2, but is not limited thereto. The first substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a voltage difference between the source / drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, the embodiment forms the electrical junction region 140 on the first substrate 100 on which the readout circuit 120 is formed as shown in FIG. 3 so that there is a voltage difference between the source / drain across the transfer transistor (Tx) 121. This allows full dumping of the photocharge.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 210 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on to be converted into a voltage.

Since the maximum voltage value of the P0 / N- / P- section 140 becomes the pinning voltage and the maximum voltage value of the FD (131) node becomes Vdd-Rx Vth, the charge sharing is performed due to the potential difference between both ends of the Tx (131). Electrons generated from the photodiode 210 above the chip may be fully dumped to the FD 131 node.

That is, in the embodiment, the reason why the P0 / N- / P-well junction, not the N + / P-well junction, is formed in the silicon sub, which is the first substrate 100, is P0 during the 4-Tr APS Reset operation. In / N- / P-well junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and P-well (141), so P0 / N- / P-well Double above a certain voltage Junction is Pinch-Off as in BJT structure. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, and thus the photocharge is completely dumped from the N-well to the FD through the Tx at the Tx On / Off operation to prevent the charge sharing phenomenon.

Therefore, unlike the case where the photodiode is simply connected by N + junction as in the prior art, the embodiment can avoid problems such as degradation of saturation and degradation of sensitivity.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit to make a smooth movement path of the photo charge, thereby minimizing the dark current source and saturation ( Saturation) can be prevented and degradation of sensitivity.

To this end, the first embodiment may form an n + doped region as the first conductive connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized. To this end, the embodiment may proceed with a plug implant after etching the first metal contact 151a, but is not limited thereto. For example, as another example, an ion implantation pattern (not shown) may be formed and the first conductive connection region 147 may be formed using the ion implantation mask as an ion implantation mask.

That is, as in the first embodiment, the reason for locally N + doping only to the contact forming part is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

Next, the interlayer insulating layer 160 may be formed on the first substrate 100, and the wiring 150 may be formed. The wiring 150 may include a first metal contact 151a, a first metal 151, a second metal 152, a third metal 153, and a fourth metal contact 154a, but is not limited thereto. It is not.

Next, as shown in FIG. 4, a lower electrode 205 is formed on the wiring 150.

For example, a metal layer (not shown) may be formed on the wiring 150 and the interlayer insulating layer 160, and the lower electrode 205 may be formed by etching the metal layer leaving portions corresponding to the wiring 150. Can be. For example, at least one metal of Cr, Ti, TiN, Ta, TaN, Al, and W is deposited on the wiring 150 and the interlayer insulating layer 160 by about 50 to 2,000 microseconds.

Thereafter, the photolithography process may be performed, and the lower electrode 205 may be formed by etching the metal layer leaving a portion corresponding to the wiring 150. For example, the lower electrode may be formed by dry etching based on Cl ₂ and O ₂ , but is not limited thereto.

Thereafter, first insulating layers 207a are formed on both sides of the lower electrode 205. For example, an oxide film can be deposited to about 100 to 5,000 mW.

Next, as shown in FIG. 6, the pixel isolation insulating layer 207 is formed by performing a photo process and an etching process on the first insulating layer 207a, thereby preventing crosstalk between pixels. The pixel isolation insulating layer 207 of the embodiment may be formed up to the height of the first conductivity type conductive layer 212 of the image sensing unit, thereby preventing inter-pixel interference by preventing photoelectrons from being generated at the pixel boundary.

Next, as illustrated in FIG. 7, the image sensing unit 210 may be formed on the lower electrode 205. The image sensing unit 210 may include a first conductive type conductive layer 212, an intrinsic layer 214, and a second conductive type conductive layer 216 sequentially formed. For example, an amorphous silicon photodiode including the P layer 216, the I layer 214, and the N layer 212 may be formed, and the transparent upper electrode 220 may be formed on the image sensing unit 210. have.

Then, a dark metal (not shown) connecting the upper electrode 220 and the reset line 155 on the image sensing unit of the outermost pixel by performing a photo process and an etching process to form a reset line is performed. ) Can be formed. For example, after the TiN-AlCu-TiNTi layer is deposited to about 100 to 10,000 Å, the photo process may be performed to remove the TiN-AlCu-TiNTi film other than the reset line 155.

Thereafter, the top metal of the bonding pad 157 is opened through a photo process, and then a second insulating film (for example, an oxide film) is deposited for about 100 to 10,000 Å, and the color filter is deposited thereon. (Color filter) (not shown) The formation process proceeds sequentially.

Next, a negative PR film is deposited for planarization, a photo-develop-hot plate process is performed, and then a top of the top pad of the bonding pad is opened to open the bonding pad 157. 2 The insulating film may be removed by a blank etch to complete the final image sensor.

(2nd Example)

8 is a cross-sectional view of the image sensor according to the second embodiment, which is a detailed view of a first substrate on which a lead-out circuit 120, an electrical junction region 140, and a wiring 150 are formed.

The image sensor according to the second embodiment may include a readout circuitry 120 formed on the first substrate 100; An interlayer insulating layer 160 formed on the first substrate 100; A wiring 150 formed in the interlayer insulating layer 160 to be electrically connected to the lead-out circuit 120; A lower electrode 205 formed on the wiring 150; A pixel isolation insulating layer 207 formed on both sides of the lower electrode 205; And an image sensing device 210 formed on the lower electrode 205 and the pixel isolation insulating layer 207.

The second embodiment can employ the technical features of the first embodiment.

Meanwhile, unlike the first embodiment, the second embodiment is an example in which the first conductive connection region 148 is formed on one side of the electrical bonding region 140.

According to an embodiment, an N + connection region 148 for ohmic contacts may be formed in the P0 / N− / P− junction 140, in which case the N + connection region 148 and the M1C contact 151a are formed in the process. A source may occur. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. The crystal defects generated during the contact forming process in the electric field become a liquid source.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-field by the N + / P0 junction 148/145 is added, which may also be a leakage source. .

Accordingly, in the second embodiment, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with a P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is provided. present.

According to the second embodiment, the E-Field of the Si surface does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a sectional view of an image sensor according to a first embodiment;

2 to 7 are process cross-sectional views of a method of manufacturing the image sensor according to the first embodiment.

8 is a sectional view of an image sensor according to a second embodiment;

Claims (13)

A readout circuitry formed on the first substrate; An interlayer insulating layer formed on the first substrate; A wiring formed on the interlayer insulating layer and electrically connected to the lead-out circuit; A lower electrode formed on the wiring; A pixel isolation insulating layer formed on both sides of the lower electrode; And And an image sensing unit formed on the lower electrode. According to claim 1, The image detection unit, It comprises a first conductive conductive layer, an intrinsic layer and a second conductive conductive layer formed sequentially, The pixel isolation insulating layer is formed to the height of the first conductive type conductive layer of the image sensing unit. According to claim 1, And an electrical junction region formed on the first substrate to be electrically connected to the lead-out circuit. The method of claim 3, wherein The lead out circuit is An image sensor comprising a potential difference between a source and a drain of two sides of a transistor. The method of claim 3, wherein And a first conductivity type connection region formed between the electrical junction region and the wiring. The method of claim 5, The first conductivity type connection region And a first conductivity type connection region formed on the electrical junction region and electrically connected to the wiring. The method of claim 5, The first conductivity type connection region And a first conductivity type connection region formed on one side of the electrical junction region to be electrically connected to the wiring. Forming a readout circuitry on the first substrate; Forming an interlayer insulating layer on the first substrate; Forming a wire on the interlayer insulating layer, the wiring being electrically connected to the lead-out circuit; Forming a lower electrode on the wiring; Forming a first insulating layer on the lower electrode; Partially etching the first insulating layer to form a pixel isolation insulating layer on both sides of the lower electrode; And And forming an image sensing device on the lower electrode. The method of claim 8, Forming the image detection unit, Forming a first conductivity type conductive layer, forming an intrinsic layer, and forming a second conductivity type conductive layer, The pixel isolation insulating layer is formed to the height of the first conductive type conductive layer of the image sensing unit. The method of claim 8, And forming an electrical junction region electrically connected to the lead-out circuit on the first substrate. The method of claim 10, And forming a first conductive connection region between the electrical junction region and the wiring. The method of claim 11, wherein The first conductivity type connection region And an electrical connection with the wirings formed on the electrical junction region. The method of claim 11, wherein The first conductivity type connection region The method of manufacturing an image sensor, characterized in that formed on the one side of the electrical junction region is electrically connected to the wiring.

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