KR20100072560A - Image sensor and method for manufacturing thereof - Google Patents

Abstract

PURPOSE: An image sensor and a manufacturing method thereof are provided to improve fill factor by forming the vertical type integrated of an image sensing unit and readout circuit. CONSTITUTION: A readout circuit is formed on a semiconductor substrate. A wiring and interlayer dielectric layer(160) are formed on the outcome. An image sensing unit(200) with a first and second dope layer laminated is formed on the interlayer dielectric layer. A via hole exposing the wiring through the image sensing unit and interlayer dielectric layer is formed. An ion implantation layer(250) is formed on the top surface of the image sensing unit and sidewall of the via hole. A metal contact(260) is formed inside the via hole. A protective layer(270) is formed on the metal contact so that the via hole be gap filled.

Description

Image Sensor and Method for Manufacturing Thereof}

Embodiments relate to an image sensor.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is classified into a charge coupled device (CCD) image sensor and a complementary metal oxide silicon (CMOS) image sensor (CIS). do.

The CMOS image sensor is a structure in which a photo diode area for receiving a light signal and converting it into an electric signal and a transistor area for processing the electric signal are horizontally disposed.

The horizontal image sensor as described above has a limitation in that the photodiode region and the transistor region are horizontally disposed on the semiconductor substrate so as to expand the light sensing portion (commonly referred to as "Fill Factor") under a limited area.

As an alternative to overcome this problem, circuitry is formed on a silicon substrate by depositing a photodiode with amorphous silicon or by using wafer-to-wafer bonding. Attempts have been made to form photodiodes above the circuit area (hereinafter referred to as "three-dimensional image sensor"). The photodiode and the circuit area are connected through a metal line.

However, in the case of wafer-to-wafer bonding, the bonding force of the wafer is not uniform, and thus the bonding force may be lowered. This is because the wiring for connecting the photodiode and the circuit region is exposed to the surface of the interlayer insulating film, so that the interlayer insulating film has a non-uniform surface profile, thereby causing a problem that the bonding force with the photodiode formed on the interlayer insulating film is degraded. do.

Meanwhile, in order to connect the photodiode and the circuit region, a deep via may be formed on the wafer on which the photodiode is formed, and then a metal layer may be formed to be connected to the wiring. However, during the etching process for forming the deep via, the exposed surface of the photodiode may be damaged to generate a dangling bond. When a dangling bond occurs in the photodiode, electrons generated in the photodiode are captured and dark current occurs.

The embodiment provides an image sensor excellent in physical and electrical contact force between a photodiode and a substrate on which a readout circuit is formed while employing a vertical image sensing unit, and a method of manufacturing the same.

The present invention also provides an image sensor and a method of manufacturing the same, which can prevent a dark current by improving a dangling bond generated by etching of the image sensing unit.

An image sensor according to an embodiment includes a semiconductor substrate including a readout circuit; A wiring and an interlayer insulating layer formed on the semiconductor substrate so as to be connected to the readout circuit; An image sensing unit formed on the interlayer insulating layer and having an ohmic contact layer, a first doped layer, and a second doped layer stacked thereon; A via hole exposing the wire through the image sensing unit and the interlayer insulating layer; An ion implantation layer formed on an upper surface of the image sensing unit and a sidewall of the via hole; A metal contact formed in the via hole such that the ohmic contact layer or the first doped layer is connected to the wiring; And a protective layer formed on the metal contact such that the via hole is gap filled.

In another aspect, a method of manufacturing an image sensor includes: forming a readout circuit on a semiconductor substrate; Forming a wiring and an interlayer insulating layer on the semiconductor substrate so as to be connected to the readout circuit; Forming an image sensing unit on which the ohmic contact layer, the first doping layer, and the second doping layer are stacked on the interlayer insulating layer; Forming a via hole through the image sensing unit and the interlayer insulating layer to expose the wiring; Forming an ion implantation layer on an upper surface of the image sensing unit and a sidewall of the via hole; Forming a metal contact inside the via hole such that the ohmic contact layer or the first doped layer is connected to the wiring; And forming a protective layer on the metal contact such that the via hole is gap-filled.

According to the image sensor and the manufacturing method thereof according to the embodiment, it is possible to improve the fill factor by the vertical integration of the readout circuit and the image sensing unit.

In addition, the image sensing unit may be bonded to the flat interlayer insulating layer to improve the physical bonding force of the bonding surface.

In addition, an ion implantation layer is formed on a sidewall of the via hole through which the wiring is exposed through the image sensing unit, thereby improving dark current characteristics by removing the dangling bond formed on the sidewall of the via hole.

An image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

The embodiment is not limited to the CMOS image sensor, and may be applied to all image sensors requiring a photodiode such as a CCD image sensor.

10 is a cross-sectional view illustrating an image sensor according to an embodiment.

The image sensor according to the embodiment may include a semiconductor substrate 100 including a readout circuit 120, wirings 150 and interlayer insulation formed on the semiconductor substrate 100 to be connected to the readout circuit 120. An image sensing unit 200 formed on the layer 160, the interlayer insulating layer 160, and the ohmic contact layer 230, the first doped layer 210, and the second doped layer 220 stacked thereon. A via hole 245 penetrating the image sensing unit 200 and the interlayer insulating layer 160 to expose the wiring 150, an upper surface of the image sensing unit 200, and sidewalls of the via hole 245. The metal contact 260 and the via hole formed in the via hole 245 so that the ion implantation layer 250 and the ohmic contact layer 230 or the first doped layer 210 are connected to the wiring 150. A protective layer 270 is formed on the metal contact 260 so that the gap 245 is gap filled.

The ion implantation layer 250 may be formed of hydrogen ions (H ₂ ). The ion implantation layer 250 may be formed of hydrogen (H ₂ ) ions to improve the defect of the image sensing unit 200, thereby preventing dangling bonds.

The metal contact 260 may be formed in the via hole 245 to be electrically connected to the ohmic contact layer (N +) 230 or the first doped layer (N−) 210. That is, since the metal contact 260 is formed to be separated from the second doped layer 220, the photoelectric charge generated by the image sensing unit 200 is formed through the metal contact 260 and the wiring 150. To the out circuit 120.

The passivation layer 270 is formed to gap-fill an inside of the via hole 245 corresponding to the upper portion of the metal contact 260. The protective layer 270 may be formed on the upper surfaces of the metal contact 260 and the image sensing unit 200 to protect the device. In addition, the protective layer 270 may be formed on the metal contact 260 to physically and electrically separate the metal contact 260 and the second doped layer 220. For example, the pore layer 270 may be formed of an insulating film such as an oxide film or a nitride film.

The pixel separation layer 280 is formed inside the image sensing unit 200 corresponding to the metal contacts 260 so that the image sensing unit 200 is separated by unit pixels. The pixel isolation layer 280 may be formed of an insulating film such as an oxide film or a nitride film to separate the image detection unit 200 for each pixel.

Unexplained reference numerals among the reference numerals of FIG. 10 will be described below in the manufacturing method.

Hereinafter, a method of manufacturing an image sensor according to an embodiment will be described with reference to FIGS. 1 to 10.

Referring to FIG. 1, a wiring 150 and an interlayer insulating layer 160 are formed on a semiconductor substrate 100 including a readout circuit 120.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. An isolation layer 110 is formed on the semiconductor substrate 100 to define an active region. A readout circuit 120 including transistors for each unit pixel is formed in the active region.

The readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. . Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. Meanwhile, the readout circuit 120 may be applied to a 3Tr or 5Tr structure.

The forming of the lead-out circuit 120 on the semiconductor substrate 100 may include forming an electrical junction region 140 on the semiconductor substrate 100 and the wiring 150 on the electrical junction region 140. ) May include forming a first conductivity type connection region 147.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 1, but is not limited thereto. In addition, the semiconductor substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a voltage difference between the source / drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, by forming an electrical junction region 140 in the semiconductor substrate 100 on which the readout circuit 120 is formed, there is a voltage difference between the source / drain across the transfer transistor (Tx) 121 so as to completely dump the photocharge. This can be made possible.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail with reference to FIGS. 1 and 2.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 205 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on and converted into voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the node FD 131 becomes Vdd-Rx Vth, as shown in FIG. 2, the potential difference between both ends of the Tx 131 is shown. Due to this, electrons generated from the photodiode on the chip may be completely dumped to the FD 131 node without charge sharing.

That is, in the embodiment, the reason why the P0 / N- / Pwell junction is formed instead of the N + / Pwell junction in the silicon sub (Si-Sub) of the semiconductor substrate 100 is the reason for the 4-Tr APS Reset operation. In P0 / N- / Pwell junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and Pwell (141), so P0 / N- / Pwell is above a certain voltage. Double junction causes pinch-off as in BJT structure. This is called a pinning voltage. Therefore, a voltage difference occurs between the source / drain at both ends of the Tx 121, and thus, photocharge is fully dumped from the N-well to the FD through the Tx at the N-well, thereby preventing charge sharing.

Therefore, unlike the case where the photodiode is simply connected with N + junction in the general technology, problems such as degradation of saturation and degradation of sensitivity may be avoided according to the embodiment.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit 120 to minimize the dark current source by creating a smooth movement path of the photo charge. Deterioration of saturation and degradation of sensitivity can be prevented.

To this end, the embodiment may form an N + doped region as the first conductive connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized.

To this end, the embodiment may proceed with a plug implant after etching the second metal contact 151a, but is not limited thereto. For example, the first conductive connection region 147 may be formed by forming an ion implantation pattern (not shown) and using the ion implantation mask as an ion implantation mask.

That is, the reason for N + doping locally only in the contact forming part as in the embodiment is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

3 shows another structure for the readout circuit. As shown in FIG. 3, a first conductive connection region 148 may be formed on one side of the electrical junction region 140.

Referring to FIG. 3, an N + connection region 148 for ohmic contact may be formed in the P0 / N− / P− junction 140, where the N + connection region 148 and the M1C contact 151a are formed. The formation process may be a leakage source. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. Crystal defects that occur during the contact formation process in the electric field become a liquid source.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-Field by the N + / P0 junction (148/145) is added. Can be a Leakage Source.

That is, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with the P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is presented.

Then, the E-Field of the surface of the semiconductor substrate 100 does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

Referring back to FIG. 1, an interlayer insulating layer 160 and a wiring 150 may be formed on the semiconductor substrate 100. The wiring 150 may include a second metal contact 151a, a first metal 151, a second metal 152, and a third metal 153, but is not limited thereto. In an embodiment, after forming the third metal 153, an insulating film may be deposited to prevent the third metal 153 from being exposed, and then an interlayer insulating layer 160 may be formed by performing a planarization process. Therefore, the surface of the interlayer insulating layer 160 having a uniform surface profile may be exposed on the semiconductor substrate 100.

Referring to FIG. 4, an image sensing unit 200 is formed on the interlayer insulating layer 160. The image sensing unit 200 may have a PN junction photodiode structure including a first doped layer 210 and a second doped layer 220. In addition, the image sensing unit 200 may include an ohmic contact layer 230 formed under the first doped layer 210. For reference, the third metal 153 and the interlayer insulating layer 160 of the wiring 150 illustrated in FIG. 4 represent a part of the wiring and the interlayer insulating layer 160 illustrated in FIG. 1. Some of the lead-out circuit 120 and the wiring 150 are omitted.

For example, the image sensing unit 200 sequentially implants P-type impurities (P +) and N-type impurities (N−) into a carrier substrate (not shown), which is a silicon wafer having a crystalline structure, to sequentially form a second doped layer. The first doped layer 210 may be stacked on the 220. In addition, the ohmic contact layer 230 may be formed by ion implanting a high concentration of N-type impurities (N +) into a shallow region of the carrier substrate so as to contact the first doped layer 210. The ohmic contact layer 230 may lower the contact resistance between the image sensing unit 200 and the wiring 150.

In an embodiment, the first doped layer 210 may be formed to have a wider area than the second doped layer 220. The depletion region can then be expanded to increase the production of photoelectrons.

Next, the ohmic contact layer 230 of the carrier substrate is positioned to face the upper surface of the interlayer insulating layer 160, and then the bonding process is performed to bond the semiconductor substrate 100 and the carrier substrate. Accordingly, the image sensing unit 200 may have a structure in which an ohmic contact layer 230, a first doped layer 210, and a second doped layer 220 are stacked on the interlayer insulating layer 160. Thereafter, the carrier substrate on which the hydrogen layer (not shown) is formed to expose the image sensing unit 200 bonded on the interlayer insulating layer 160 is removed by heat treatment or mechanical impact, and the like, so that the second doping layer 220 is removed. ) Surface.

Accordingly, the image detector 200 may be formed on the readout circuit 120 to prevent defects of the image detector 200 while increasing the fill factor. In addition, since the image sensing unit 200 is bonded on the interlayer insulating layer 160 having a uniform surface profile, physical bonding force may be improved.

Meanwhile, in the embodiment, the image sensing unit 200 is formed to have a PN junction, but the image sensing unit 200 may be formed to have a PIN junction.

Referring to FIG. 5, a hard mask 240 is formed on the image detector 200. The hard mask 240 may selectively expose the surface of the image sensing unit 200 corresponding to the third metal 153. For example, the hard mask 240 may be formed in a triple structure of an oxide film-nitride film-oxide film. The hard mask 240 is used because the image sensing unit 200 formed on the silicon wafer is difficult to etch with a general photosensitive material. In particular, since the ONO structure hard mask 240 has a high etching selectivity with a silicon wafer, the image detection unit 200 may be selectively etched.

The hard mask 240 forms a hard mask layer (not shown) of the ONO structure on the image sensing unit 200 and then selectively exposes the surface of the image sensing unit 200 by a photo and etching process. Can be.

Next, a via hole 245 is formed through the image sensing unit 200 and the interlayer insulating layer 160 to expose the third metal 153. The via hole 245 may be formed by performing an etching process using the hard mask 240 as an etching mask. For example, the via hole 245 may be formed through a dry or wet etching process. Defects are generated on surfaces of the first doped layer 210, the second doped layer 220, and the ohmic contact layer 230 exposed by the via hole 245 during the etching process for forming the via hole 245. Can be. Since such defects may cause dangling bonds and later cause dark currents, improvement of defects in the sidewalls of the via holes 245 may be required.

Thereafter, the hard mask 240 may be removed.

6 and 7, a hydrogen annealing process is performed on the image sensing unit 200 including the via hole 245.

6 and 7 form hydrogen (H ₂ ) atmosphere by supplying hydrogen (H ₂ ) gas to the image sensing unit 200 in which the via hole 245 is formed, and then annealing in the hydrogen atmosphere. Proceed to (Anneal process).

By combining Si atoms and hydrogen (H ₂ ) atoms, which are surfaces of the image sensing unit 200 exposed by the hydrogen anneal process, the defects on the sidewalls of the via holes 245 may be improved. have.

Specifically, the annealing process may be performed for 30 to 90 minutes at a temperature of 380 ~ 430 ℃ in a hydrogen (H ₂ ) atmosphere. Accordingly, the hydrogen (H ₂ ) ion and the silicon atom of the image sensing unit 200 exposed by the via hole 245 may be combined to remove the dangling bone.

As shown in FIG. 8, an ion implantation layer 250 may be formed on the upper surface of the image sensing unit 200 and the sidewalls of the via holes 245 by the hydrogen annealing process.

As described above, the ion implantation layer 250 is formed on the upper surface of the image sensing unit 200 and the sidewalls of the via hole 245, thereby improving dark current characteristics due to the dangling bond.

Although not shown, the ion implantation layer 250 may be formed by ion implanting hydrogen (H ₂ ) ions into the sidewall of the via hole 245.

9, a metal contact 260 is formed in the via hole 245. The metal contact 260 may be formed in the via hole 245 to electrically connect the image sensing unit 200 and the readout circuit 120. The metal contact 260 is formed inside the via hole 245 only to the height of the ohmic contact layer 230 or the first doped layer 210 of the image sensing unit 200 and the second doped layer 220. Can be separated.

For example, the metal contact 260 may include tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta) titanium (Ti), titanium nitride (TiN), Ti / TiN, and copper (Cu). It may be formed of any one of a metal material such as.

The metal contact 260 deposits a metal layer (not shown) into the via hole 245 and then performs an etching process so that the metal layer does not remain inside the via hole 245 corresponding to the second doped layer 220. It can be formed to proceed.

Therefore, the ohmic contact layer 230 or the first doped layer 210 may be electrically connected to the third metal 153 by the metal contact 260. In addition, the metal contact 260 may be electrically and physically separated from the second doped layer 220.

Referring to FIG. 10, a protective layer 270 is formed on the metal contact 260. The protective layer 270 may be formed by depositing an insulating film such as an oxide film or a nitride film on the image sensing unit 200 so that the via hole 245 in which the metal contact 260 is formed is gap filled. The protective layer 270 may be formed until the via hole 245 is gapfilled. Alternatively, the protective layer 270 may be formed so that the upper surface of the image sensing unit 200 is not exposed.

The protective layer 270 is formed in the via hole 245 corresponding to the upper portion of the metal contact 260 so that the metal contact 260 and the second doping layer 220 of the image sensing unit 200 are electrically connected. It can be physically separated.

Therefore, the metal contact 260 for transferring the photocharge generated by the image sensing unit 200 to the readout circuit 120 may be physically formed only in the ohmic contact layer 230 or the first doped layer 210. Since the electrical contact is made, the image sensor can signal out put a normal signal. This is because the metal contact 260 is physically separated by the second doping layer 220 and the protective layer 270 and is connected only to the first doping layer 210, thereby preventing the image sensing unit from being shorted. Because it can.

Next, a pixel separation layer 280 is formed to separate the image sensing unit 200 for each unit pixel. The pixel separation layer 280 may be formed by an STI or an ion implantation process. For example, the pixel isolation layer 280 penetrates through the passivation layer 270 and the image sensing unit 200 corresponding to the metal contact 260, and then forms an trench to gap fill the trench. Alternatively, it may be formed by gap filling an insulating material such as a nitride film.

Although not shown, an upper electrode, a color filter, and a micro lens may be formed on the image sensing unit 200.

In example embodiments, an image sensing unit may be formed on a semiconductor substrate on which a readout circuit is formed to increase the fill factor.

In addition, since the image sensing unit is bonded on the interlayer insulating layer having a flat profile, physical bonding force may be improved.

In addition, an ion implantation layer is formed on a sidewall of the via hole through which the wiring is exposed through the image sensing unit, thereby improving dark current characteristics by removing the dangling bond formed on the sidewall of the via hole.

In addition, the metal contact formed inside the via hole may be electrically connected only to the ohmic contact layer of the image sensing unit, so that the photocharge signal input / output generated by the image sensing unit may be efficiently performed.

The above-described embodiments are not limited to the above-described embodiments and drawings, and it is common in the technical field to which the present embodiments belong that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be apparent to those who have

1 to 10 are cross-sectional views illustrating a manufacturing process of an image sensor according to an embodiment.

Claims (10)

A semiconductor substrate including a readout circuit; A wiring and an interlayer insulating layer formed on the semiconductor substrate so as to be connected to the readout circuit; An image sensing unit formed on the interlayer insulating layer and having an ohmic contact layer, a first doped layer, and a second doped layer stacked thereon; A via hole exposing the wire through the image sensing unit and the interlayer insulating layer; An ion implantation layer formed on an upper surface of the image sensing unit and a sidewall of the via hole; A metal contact formed in the via hole such that the ohmic contact layer or the first doped layer is connected to the wiring; And And a protective layer formed on the metal contact such that the via hole is gap filled. The method of claim 1, The ion implantation layer is an image sensor, characterized in that formed with hydrogen ions. The method of claim 1, The protective layer is an image sensor, characterized in that formed of an oxide film. The method of claim 1, And a pixel separation layer formed inside the image detection unit corresponding to the metal contacts so that the image detection unit is separated for each unit pixel. Forming a readout circuit on the semiconductor substrate; Forming a wiring and an interlayer insulating layer on the semiconductor substrate so as to be connected to the readout circuit; Forming an image sensing unit on which the ohmic contact layer, the first doping layer, and the second doping layer are stacked on the interlayer insulating layer; Forming a via hole through the image sensing unit and the interlayer insulating layer to expose the wiring; Forming an ion implantation layer on an upper surface of the image sensing unit and a sidewall of the via hole; Forming a metal contact inside the via hole such that the ohmic contact layer or the first doped layer is connected to the wiring; And And forming a protective layer on the metal contact such that the via hole is gap-filled. The method of claim 5, And forming a pixel separation layer penetrating the image sensing unit between the metal contacts so that the image sensing unit is separated by unit pixels after forming the passivation layer. The method of claim 5, The ion implantation layer is a manufacturing method of an image sensor, characterized in that formed with hydrogen (H ₂ ) ions. The method of claim 5, The ion implantation layer is a method of manufacturing an image sensor, characterized in that formed by performing an annealing process in a hydrogen (H ₂ ) gas atmosphere. The method of claim 5, The ion implantation layer is a method of manufacturing an image sensor, characterized in that formed by the ion implantation process by hydrogen (H ₂ ) ions. The method of claim 5, The protective layer is a method of manufacturing an image sensor, characterized in that formed by the CMP process after depositing an oxide film so that the via hole formed with the metal contact is gap-filled.

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