KR20100076608A - Method for forming contact hole in semiconductor device - Google Patents

Method for forming contact hole in semiconductor device Download PDF

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Publication number
KR20100076608A
KR20100076608A KR1020080134716A KR20080134716A KR20100076608A KR 20100076608 A KR20100076608 A KR 20100076608A KR 1020080134716 A KR1020080134716 A KR 1020080134716A KR 20080134716 A KR20080134716 A KR 20080134716A KR 20100076608 A KR20100076608 A KR 20100076608A
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KR
South Korea
Prior art keywords
forming
layer
hard mask
pattern
spacer
Prior art date
Application number
KR1020080134716A
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Korean (ko)
Inventor
조성윤
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080134716A priority Critical patent/KR20100076608A/en
Publication of KR20100076608A publication Critical patent/KR20100076608A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Abstract

PURPOSE: A contact hole forming method of a semiconductor device is provided to form a contact hole in a uniform line width of 30nm or less by forming a first spacer in a stacked layer in which an oxide layer and a nitride layer are stacked. CONSTITUTION: A hard mask layer is formed on an etched layer(12). The hard mask layer is selectively etched to define a plurality of contact holes, wherein the hard mask pattern(13A) comprises an opening. A spacer(18) is formed on the hard mask pattern sidewall and at the same time, an insulating layer(19B) insulating between the contact holes is formed. The etched layer is etched using the hard mask pattern, and the spacer and the insulating layer as an etching barrier.

Description

TECHNICAL FOR FORMING CONTACT HOLE IN SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device capable of stably forming a contact hole having a line width of 30 nm or less.

As the degree of integration of semiconductor devices increases, the contact hole line width also decreases continuously. Accordingly, in recent years, contact holes having a line width of 30 nm or less are required in semiconductor devices.

Contact holes with a line width of less than 30nm are virtually impossible to implement with a single mask using photolithography. Therefore, recently, contact holes having a line width of 30 nm or less have been implemented by using a technology such as SPT (Spacer Patterning Technology), DPT (Double Patterning Technology) or PSL (Photo Sidewall Layer) formation.

However, the above-described techniques such as SPT, DPT, or PSL have a problem in that the difficulty of patterning is very high and the productivity is complicated. In addition, there is a problem that it is very difficult to form a contact hole having a uniform shape in the low substrate due to the overlay problem.

Accordingly, in forming contact holes having a line width of 30 nm or less, a process scheme for forming contact holes more stably than the above-described techniques such as SPT, DPT, or PSL is required.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for forming a contact hole in a semiconductor device capable of stably forming a contact hole having a line width of 30 nm or less.

According to an aspect of the present invention, there is provided a method of forming a contact hole, including: forming a hard mask layer on an etched layer; Selectively etching the hard mask layer to define a plurality of contact holes, and forming a hard mask pattern having a single opening; And forming a spacer on the sidewall of the hard mask pattern and separating the contact hole, and etching the etched layer using the hard mask pattern, the spacer, and the separator as an etch barrier.

The hard mask pattern may be formed as a line type pattern arranged in a line or zigzag so that a plurality of patterns of any one type selected from the group consisting of circles, squares, and polygons are partially overlapped.

According to another aspect of the present invention, there is provided a method of forming a contact hole, the method comprising: sequentially forming a hard mask layer and a sacrificial layer on an etched layer; Defining a plurality of contact holes on the sacrificial layer, and forming a photoresist pattern having a single opening; Etching the sacrificial layer using the photoresist pattern as an etch barrier to form a sacrificial pattern; Forming a first spacer on sidewalls of the sacrificial pattern; Forming a hard mask pattern by etching the hard mask layer using the sacrificial pattern and the first spacer as an etch barrier; Forming a second spacer on the sidewall of the hard mask pattern and separating the contact hole, and etching the etched layer using the hard mask pattern, the second spacer and the separator as an etch barrier. It includes.

The photoresist pattern may be formed as a line type pattern arranged in a line or zigzag such that a plurality of patterns of any one type selected from the group consisting of circles, squares, and polygons partially overlap each other.

The sacrificial film may be formed of a silicon film, and the first spacer may be formed of a laminated film in which an oxide film and a nitride film are stacked.

The present invention based on the above-mentioned means for solving the problem is a technique, such as the formation of SPT (Spacer Patterning Technology), DPT (Double Patterning Technology) or PSL (Photo Sidewall Layer), which are complicated in the process and have high process difficulty It is effective to stably form a contact hole having a line width of 30 nm or less without using A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention described below is complicated to the process process, the process difficulty is high and less than 30nm without using a low productivity SPT (Spacer Patterning Technology), DPT (Double Patterning Technology) or PSL (Photo Sidewall Layer) formation, etc. Provided is a method of forming a contact hole in a semiconductor device capable of stably forming a contact hole having a line width.

1A to 1D are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 1A, an etched layer 12 is formed on a substrate 11 on which a predetermined structure is formed. In this case, the etched layer 12 may be formed of an insulating film, for example, an oxide.

Next, the hard mask layer 13 and the sacrificial layer 14 are sequentially formed on the etched layer 12. The hard mask layer 13 may be formed of an etched layer 12, for example, an amorphous carbon layer (ACL) having a large etching selectivity with respect to an oxide layer.

The sacrificial film 14 may be formed of a silicon film having a large etching selectivity with respect to the photoresist (PR), for example, a polysilicon film (poly-Si). This is to transfer the subsequent inter-resist photoresist pattern to the sacrificial layer 14 without pattern deformation.

Next, a plurality of contact holes are defined on the sacrificial layer 14, and the photoresist pattern 15 having a single opening 15A is formed. In this case, the line width of the opening 15A of the photoresist pattern 15 defines a plurality of contact holes, but is patterned to have a single opening 15A, so that the line width of the contact hole to be formed in the etched layer 12 through the subsequent process is larger than the line width of the contact hole 15A. Can be formed. Therefore, process difficulty of photolithography (Pjoth Lithography) for forming the photoresist pattern 15 can be reduced.

The photoresist pattern 15 may be formed in a line type pattern arranged in a row or zigzag so that a plurality of patterns of any one type selected from the group consisting of circles, squares, and polygons are partially overlapped. For example, the photoresist pattern 15 according to the exemplary embodiment of the present invention has been exemplified in the case where the plurality of circular patterns are formed in a line type pattern arranged in a line so as to partially overlap.

As illustrated in FIG. 1B, the sacrificial layer 14 is etched using the photoresist pattern 15 as an etch barrier to form the sacrificial pattern 14A. In this case, an etching process for forming the sacrificial pattern 14A may be performed by using a dry etch method. Here, in order to transfer the shape of the photoresist pattern 15 to the sacrificial pattern 14A without deformation as much as possible, it is preferable to use a chemical dry etching (CDE) as a dry etching method during the etching process.

Here, the chemical dry etching method is an etching method capable of simultaneously performing chemical etching and physical etching, and transfers the shape of the photoresist pattern 15 to the sacrificial pattern 14A without modifying the pattern by adjusting chemical and physical etching characteristics. You can. For example, in the process of forming the sacrificial pattern 14A, when etching is performed using a process condition in which chemical etching is superior to physical etching, the shape of the photoresist pattern 15 is transferred to the first hard mask pattern 14A without pattern deformation. You can.

Next, after the remaining photoresist pattern 15 is removed, the first spacer 18 is formed on the sidewalls of the sacrificial pattern 14A. In this case, the first spacer 18 is preferably formed of a laminated film in which the oxide film 16 and the nitride film 17 are sequentially stacked. Here, a silicon oxide film (SiO 2 ) may be used as the oxide film 16, and a silicon nitride film (Si 3 N 4 ) may be used as the nitride film 17.

The first spacer 18 serves to reduce the opening line width of the sacrificial pattern 14A in order to form a contact hole having a line width of 30 nm or less, and at the same time, to the circular, square and polygon transferred from the photoresist pattern 15. A plurality of patterns of any one type selected from the group consisting of serves to facilitate the formation of a separator to separate the adjacent patterns by reducing the interval of some overlapping regions.

Here, the first spacer 18 may not be formed as a laminated film in which the oxide film 16 and the nitride film 17 are laminated, but may be formed as a single film made of the oxide film 16 or the nitride film 17. However, when the first spacer 18 is formed of a single layer composed of the oxide film 16 or the nitride film 17, loss of the first spacer 18 occurs during subsequent processes, thereby causing the loss of the sacrificial pattern 14A. Since the shape may be deformed, the first spacer 18 is preferably formed of a laminated film in which the oxide film 16 and the nitride film 17 are laminated.

As shown in FIG. 1C, the hard mask layer 13 is etched using the sacrificial pattern 14A and the first spacer 18 as an etch barrier to form the hard mask pattern 13A, and then the sacrificial pattern 14A is formed. And the first spacer 18 is removed.

Next, a second spacer 19A is formed on the sidewall of the hard mask pattern 13A, and a separator 19B is formed to separate the adjacent patterns. In this case, the second spacer 19A serves to reduce the line width of the opening of the hard mask pattern 13A to form a contact hole having a line width of 30 nm or less and at the same time serves as an etch barrier during the subsequent etching process of the etching target layer 12. Works. The separator 19B is a region in which a plurality of patterns of any one type selected from a group consisting of circles, squares, and polygons are overlapped to define a plurality of contact holes from the photoresist pattern 15 having the first single opening 15A. Fills the gap to separate adjacent patterns.

As illustrated in FIG. 1D, the etching target layer 12 is etched using the hard mask pattern 13A, the second spacer 19A, and the separator 19B as an etch barrier, and a plurality of contact holes 20 having a line width of 30 nm or less. ).

Next, the hard mask pattern 13A, the spacer 19A, and the separator 19B are removed.

Next, although not shown, a conductive material may be deposited inside the contact hole 20 to form a structure such as a contact plug or a storage node.

As described above, the present invention is 30 nm or less without using a technology such as SPT (Spacer Patterning Technology), DPT (Double Patterning Technology) or PSL (Photo Sidewall Layer), which is complicated in the process and has high process difficulty. It is possible to stably form a contact hole having a line width of.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A to 1D are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

11 substrate 12 etched layer

13: hard mask film 13A: hard mask pattern

14: sacrificial film 14A: sacrificial pattern

15 photoresist pattern 15A opening

16 oxide film 17 nitride film

18: first spacer 19A: second spacer

19B: Membrane 20: Contact Hole

Claims (6)

Forming a hard mask film on the etched layer; Selectively etching the hard mask layer to define a plurality of contact holes, and forming a hard mask pattern having a single opening; Forming a spacer on the sidewall of the hard mask pattern and at the same time separating the contact hole; And Etching the etched layer using the hard mask pattern, the spacer and the separator as an etch barrier Contact hole forming method of a semiconductor device comprising a. The method of claim 1, The hard mask pattern, A method of forming a contact hole in a semiconductor device, the method comprising: forming a plurality of patterns of any shape selected from the group consisting of circles, squares, and polygons in a line-type pattern arranged in a line or zigzag so as to partially overlap. Sequentially forming a hard mask layer and a sacrificial layer on the etched layer; Defining a plurality of contact holes on the sacrificial layer, and forming a photoresist pattern having a single opening; Etching the sacrificial layer using the photoresist pattern as an etch barrier to form a sacrificial pattern; Forming a first spacer on sidewalls of the sacrificial pattern; Forming a hard mask pattern by etching the hard mask layer using the sacrificial pattern and the first spacer as an etch barrier; Forming a separation layer for forming a second spacer on sidewalls of the hard mask pattern and separating the contact holes; And Etching the etched layer using the hard mask pattern, the second spacer, and the separator as an etch barrier. Contact hole forming method of a semiconductor device comprising a. The method of claim 3, The photoresist pattern, A method of forming a contact hole in a semiconductor device, the method comprising: forming a plurality of patterns of any shape selected from the group consisting of circles, squares, and polygons in a line-type pattern arranged in a line or zigzag so as to partially overlap each other. The method of claim 3, And the sacrificial layer comprises a silicon layer. The method of claim 3, The first spacer, A method for forming a contact hole in a semiconductor device, which is formed of a laminated film in which an oxide film and a nitride film are laminated.
KR1020080134716A 2008-12-26 2008-12-26 Method for forming contact hole in semiconductor device KR20100076608A (en)

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KR1020080134716A KR20100076608A (en) 2008-12-26 2008-12-26 Method for forming contact hole in semiconductor device

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KR1020080134716A KR20100076608A (en) 2008-12-26 2008-12-26 Method for forming contact hole in semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9704722B2 (en) 2014-12-15 2017-07-11 Samsung Electronics Co., Ltd. Method of forming fine pattern and method of manufacturing integrated circuit device using the method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9704722B2 (en) 2014-12-15 2017-07-11 Samsung Electronics Co., Ltd. Method of forming fine pattern and method of manufacturing integrated circuit device using the method

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