KR20100076255A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
KR20100076255A
KR20100076255A KR1020080134228A KR20080134228A KR20100076255A KR 20100076255 A KR20100076255 A KR 20100076255A KR 1020080134228 A KR1020080134228 A KR 1020080134228A KR 20080134228 A KR20080134228 A KR 20080134228A KR 20100076255 A KR20100076255 A KR 20100076255A
Authority
KR
South Korea
Prior art keywords
interlayer insulating
insulating film
gate
semiconductor substrate
semiconductor device
Prior art date
Application number
KR1020080134228A
Other languages
Korean (ko)
Inventor
문상태
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080134228A priority Critical patent/KR20100076255A/en
Publication of KR20100076255A publication Critical patent/KR20100076255A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention provides a semiconductor device and a method of manufacturing the same, forming a plurality of gate patterns on a semiconductor substrate, and filling a space between the gate patterns on the semiconductor substrate with a first interlayer insulating film of USG material. Depositing a second interlayer insulating film on the first interlayer insulating film and the gate pattern, and depositing a second interlayer insulating film doped with at least one element of phosphorus (P) or boron (B) And planarizing the second interlayer insulating film through a CMP process.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same that can achieve a full gap filling to improve the reliability of the semiconductor device.

In the manufacturing process of semiconductor devices, design rules become smaller and smaller, so that the pre-metal dielectric (PMD) is an interlayer insulating film to insulate the space between the gate patterns on which the MOS devices are formed. In the deposition of the interlayer insulating film, a BPSG film is deposited by adding a reactant containing boron (B) or phosphorus (P) for the purpose of sodium ion gettering.

1 is a cross-sectional view of a semiconductor device formed by a method of manufacturing a dielectric film before metal wiring according to the related art.

The conventional semiconductor device illustrated in FIG. 1 fills a space between the gate electrode 12 and the gate electrode 12 on the semiconductor substrate 10 on which the partition spacers 14 formed on the sidewalls of the gate electrode 12 are formed. The leading film PMD before the metal wiring is formed.

The insulating film (PMD) before the metal wiring is formed by depositing an interlayer insulating film. When depositing the interlayer insulating film, BPSG is added by adding a reactant containing boron (B) or phosphorus (P) for the purpose of sodium ion gettering. Film 30.

However, as the design rule due to the higher integration of the semiconductor device becomes smaller, the gap between the gate electrodes 12 becomes smaller and the gap fill becomes difficult, thereby causing voids 20 in the space between the gate electrodes 12. ) Will occur. When subsequent dielectric wiring (PMD) etching is performed while the voids 20 are formed, an empty space is formed between the adjacent contact hole and the contact hole, and the barrier metal, which is a subsequent process, is formed. Metal component penetrates into the etched empty space during barrier metal and tungsten plug-deposition, causing short circuit between adjacent contact holes and the contact holes, thereby reducing current leakage. There is a problem that by causing it adversely affects the reliability of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device and a method of manufacturing the same, which may improve reliability of a semiconductor device by performing gap filling.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: forming a plurality of gate patterns on a semiconductor substrate, and forming a space between the gate patterns on the semiconductor substrate using a USG material; Buried with a first interlayer insulating film, depositing a second interlayer insulating film on the first interlayer insulating film and the gate pattern, and doped with at least one element of phosphorus (P) or boron (B). Depositing a second interlayer insulating film, and planarizing the second interlayer insulating film through a CMP process.

According to an exemplary embodiment of the present inventive concept, a gate pattern formed on a semiconductor substrate, sidewall spacers formed on sidewalls of the gate pattern, and a space between the gate patterns on the semiconductor substrate may be used. A first interlayer insulating film of a USG material filling the gap, and a second interlayer insulating film doped with at least one of phosphorus (P) and boron (B) formed on the gate pattern and the first interlayer insulating film. It features.

A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention have the following effects.

The space between the gate electrodes is formed of a first interlayer insulating film 130 of USG (Undoped Silicate Glass), a material such as PSG (PhosphoSilicate Glass) doped with phosphorus (P) or boron (B), BoroPhospho Silicate Glass (BPSG), or the like. By sequentially stacking the second interlayer insulating film made of any one, it is possible to prevent the generation of voids between the gate electrodes.

Accordingly, problems such as leakage of current due to void generation can be solved, and metal ions are prevented from being diffused into the transistor due to the second insulating interlayer, thereby maintaining semiconductor characteristics.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

2A to 2D are cross-sectional views illustrating a gap fill method of a semiconductor device according to the present invention.

Referring to FIG. 2A, a gate electrode 112 of a transistor is formed on a semiconductor substrate 100. Although not shown, in order to form the gate electrode 112, a gate interlayer insulating film (not shown) is deposited on the semiconductor substrate 100, and then, the gate electrode 112 is formed using a mask pattern, and the gate electrode ( Sidewall spacers 114 are formed on both sidewalls of 112.

Next, as shown in FIG. 2B, a first interlayer insulating layer 130 of undoped silicate glass (USG) is deposited on the entire surface of the semiconductor substrate 100 on which the gate electrode 112 is formed.

Specifically, a high density plasma (HDP) method is deposited on the entire surface of the semiconductor substrate 100 on which the gate electrode 112 is formed, and the semiconductor substrate 100 is embedded in the space between the gate electrodes 112. When there is a topology on the gate electrode 112 remains in the shape of a triangle.

When the first interlayer insulating layer 130 is deposited with a material doped with phosphorus (P) or boron (B) such as PSG (PhosphoSilicate Glass) and BPSG (BoroPhospho Silicate Glass) as in the related art, the deposition rate during deposition Difficult to adjust, etc., causes voids (20 in FIG. 1) to occur in the space between the gate electrodes 112.

However, USG (Undoped Silicate Glass) is used to fill the gap between the gate electrodes 112 having a high aspect ratio. Here, the aspect ratio refers to the ratio of the height of the pattern to the pattern space width, and in the case of the gate process, the ratio of the height of the gate electrode to the space between the gate electrodes. Therefore, high aspect ratio means that the space between patterns is relatively small compared to the pattern height.

In addition, when the first interlayer insulating layer 130 is deposited by using a deposition method such as a conventional CVD, the space between the gate electrodes 112 having a high aspect ratio is not narrowed and does not become a gap fill. Although voids are generated due to overhang, the high density plasma (HDP) method can be used to deposit a portion of the overhang by plasma. The gapfill is possible in the space between the gate electrodes 112 having a ratio).

The first interlayer insulating layer 130 is about 1/5 to 1/2 of the height of the gate electrode 112. For example, when the gate electrode 112 is formed at a height of 2000 kV, the first interlayer insulating layer 130 is formed. It is formed to a thickness of 400 kPa to 1000 kPa.

Referring to FIG. 2C, a second interlayer insulating layer 140 is deposited on the semiconductor substrate 100 on which the first interlayer insulating layer 130 is formed.

Specifically, PSG (PhosphoSilicate Glass) doped with phosphorus (P) or boron (B) on the insulating film through a deposition method such as chemical vapor deposition (CVD) on the semiconductor substrate 100 on which the first interlayer insulating film 130 is formed. And depositing a second interlayer insulating layer 140 made of any one of materials such as BPSG (BoroPhospho Silicate Glass).

Subsequently, as shown in FIG. 2D, the second interlayer insulating layer 140 is subjected to a chemical mechanical polishing (CMP) process to planarize it.

The second interlayer insulating film 140 is formed to a thickness of 3500 kPa to 6500 kPa.

The second interlayer insulating layer 140 made of any one of a material such as phosphorus (P) or boron (B) doped PhosphoSilicate Glass (PSG) or BoroPhospho Silicate Glass (BPSG) prevents metal ions from diffusing into the transistor to prevent Keep the characteristics. In other words, if metal ions are present in the vicinity of a device, unnecessary electrical paths are formed or parasitic capacitors adversely affect device specificity. This problem can be solved because the ions bind well with metal ions (eg iron, nickel, etc.).

As such, the first interlayer insulating layer 130 of USG (Undoped Silicate Glass) and the phosphorus (P) or boron (B) are doped with the dielectric film PMD before the metal wiring to fill the space between the gate electrodes 112. By sequentially stacking the second interlayer insulating layer 140 made of any one of materials such as PSG (PhosphoSilicate Glass) and BPSG (BoroPhospho Silicate Glass), it is possible to prevent the generation of voids between the gate electrodes 112. Accordingly, problems such as leakage of current due to void generation can be solved, and metal ions are prevented from being diffused into the transistor due to the second interlayer insulating layer 140 to maintain semiconductor characteristics. .

The gap fill method as described above is not limited to the space between the gate electrodes, and is also applicable to the gap fill method between the device isolation layer and the conductive electrode patterns.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view of a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a gap fill method of a semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

110 semiconductor substrate 112 gate electrode

114 sidewall spacer 130 first interlayer insulating film

140: second interlayer insulating film

Claims (7)

Forming a plurality of gate patterns on the semiconductor substrate, Filling a space between the gate patterns on the semiconductor substrate with a first interlayer insulating film of USG material; Depositing a second interlayer insulating film on the first interlayer insulating film and the gate pattern, depositing a second interlayer insulating film doped with at least one element of phosphorus (P) or boron (B); And planarizing the second interlayer insulating film through a CMP process. The method of claim 1, And the first interlayer insulating film is formed to a thickness of 1/5 to 1/2 of the height of the gate pattern. The method of claim 1, And the second interlayer insulating film is formed to a thickness of 3500 kPa to 6500 kPa. The method of claim 1, The first interlayer insulating film is a method of manufacturing a semiconductor device, characterized in that the deposition via the HDP method. Gate patterns formed on the semiconductor substrate, Sidewall spacers formed on the sidewalls of the gate pattern; A first interlayer insulating film of USG material filling a space between the gate patterns on the semiconductor substrate; And a second interlayer insulating layer doped with at least one of phosphorus (P) and boron (B) formed on the gate pattern and the first interlayer insulating layer. The method of claim 5, And the first interlayer insulating film is formed to a thickness of 1/5 to 1/2 of the height of the gate pattern. The method of claim 1, And the second interlayer insulating film is formed to a thickness of 3500 kPa to 6500 kPa.
KR1020080134228A 2008-12-26 2008-12-26 Semiconductor device and method for manufacturing the same KR20100076255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080134228A KR20100076255A (en) 2008-12-26 2008-12-26 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080134228A KR20100076255A (en) 2008-12-26 2008-12-26 Semiconductor device and method for manufacturing the same

Publications (1)

Publication Number Publication Date
KR20100076255A true KR20100076255A (en) 2010-07-06

Family

ID=42637994

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080134228A KR20100076255A (en) 2008-12-26 2008-12-26 Semiconductor device and method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR20100076255A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110148552A (en) * 2019-04-15 2019-08-20 上海华力集成电路制造有限公司 The manufacturing method of level 0 interlayer film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110148552A (en) * 2019-04-15 2019-08-20 上海华力集成电路制造有限公司 The manufacturing method of level 0 interlayer film
CN110148552B (en) * 2019-04-15 2021-10-15 上海华力集成电路制造有限公司 Method for manufacturing zero-layer interlayer film

Similar Documents

Publication Publication Date Title
JP2004193563A (en) Semiconductor device having mim capacitor
KR100691492B1 (en) Method for forming metal line in flash memory device
US20150214234A1 (en) Semiconductor device and method for fabricating the same
KR20080017745A (en) Method for forming intermetal dielectric in semiconductor device
KR100861837B1 (en) Method of forming a metal line in semiconductor device
KR20100076255A (en) Semiconductor device and method for manufacturing the same
KR20100072559A (en) Metal wiring of semiconductor device and method for manufacturing thereof
JP2011228578A (en) Semiconductor device and method of manufacturing the same
KR20080062062A (en) Semiconductor device and method of fabricating the same
KR100784094B1 (en) Method of forming a dielectric layer in semiconductor device
KR100262007B1 (en) A method of fabricating semiconductor device
KR100791707B1 (en) Method for polishing inter-metal dielectric layer of the semiconductor device
KR100875656B1 (en) Semiconductor device and method for manufacturing the same
KR100718794B1 (en) Semiconductor device and method for manufacturing the same
KR100459063B1 (en) Method for manufacturing intermetal dielectric layer of semiconductor device
KR100641488B1 (en) Method for manufacturing contact of the semiconductor device
KR100678021B1 (en) Metal line of the semiconductor device and method for manufacturing the same
KR101023073B1 (en) Method for manufacturing Semiconductor Device
KR101012180B1 (en) Method for forming inter layer dielectrics ofsemiconductor device
KR100922546B1 (en) Semiconductor device and Method for fabricating in thereof
KR100818437B1 (en) Structure and method for manufacturing inter-metal dielectric layer between metal lines of semiconductor device
KR100792433B1 (en) Method for manufacturing a semiconductor device
KR100744070B1 (en) Method for fabricating semiconductor device
KR20060131129A (en) Method for manufacturing a semiconductor device
US20090160056A1 (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination