KR20100076235A - Semiconductor wafer and align appartus uing it - Google Patents

Semiconductor wafer and align appartus uing it Download PDF

Info

Publication number
KR20100076235A
KR20100076235A KR1020080134199A KR20080134199A KR20100076235A KR 20100076235 A KR20100076235 A KR 20100076235A KR 1020080134199 A KR1020080134199 A KR 1020080134199A KR 20080134199 A KR20080134199 A KR 20080134199A KR 20100076235 A KR20100076235 A KR 20100076235A
Authority
KR
South Korea
Prior art keywords
wafer
alignment
color
semiconductor wafer
display unit
Prior art date
Application number
KR1020080134199A
Other languages
Korean (ko)
Inventor
김윤조
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080134199A priority Critical patent/KR20100076235A/en
Publication of KR20100076235A publication Critical patent/KR20100076235A/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67282—Marking devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Multimedia (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE: A semiconductor wafer and an alignment apparatus for the same are provided to prevent damage to a wafer during manufacture of a semiconductor device by coloring the surface of the wafer without physical deformation. CONSTITUTION: An alignment indicator(12) as an align reference point is formed on a surface of a wafer(11). The alignment indicator is formed in specific color such as red, green, blue and their mixture. A sensor(22) senses the wavelength of light which enters the wafer surface and is reflected by the alignment indicator.

Description

반도체 웨이퍼 및 이를 이용한 얼라인 장치{SEMICONDUCTOR WAFER AND ALIGN APPARTUS UING IT}Semiconductor wafer and alignment device using the same {SEMICONDUCTOR WAFER AND ALIGN APPARTUS UING IT}

본 발명은 반도체 웨이퍼 및 반도체 웨이퍼의 얼라인 장치에 관한 것으로, 보다 상세하게는 웨이퍼의 표면에 얼라인 표시부가 형성되고, 이러한 얼라인 표시부를 감지하도록 한 반도체 웨이퍼 및 이를 이용한 얼라인 장치에 관한 것이다.The present invention relates to a semiconductor wafer and an alignment device for semiconductor wafers, and more particularly, to an alignment wafer having an alignment display unit formed on a surface of a wafer and sensing the alignment display unit. .

일반적으로 반도체 소자의 제조시 확산공정, 식각공정, 화학기상증착공정, 세정공정 등 다양한 단위공정을 실시된다. 그리고 식각공정을 비롯한 여러 단위공정을 실시하는 반도체 소자의 제조장치에는 웨이퍼가 로딩 또는 언로딩되는 웨이퍼 스테이지가 마련되는데, 이러한 웨이퍼 스테이지에는 웨이퍼의 에치를 정렬하는 웨이퍼의 노치(notch) 얼라이너(aligner)가 설치된다.In general, various unit processes, such as a diffusion process, an etching process, a chemical vapor deposition process, and a cleaning process, are performed in manufacturing a semiconductor device. In addition, a wafer stage in which a wafer is loaded or unloaded is provided in a semiconductor device manufacturing apparatus that performs various unit processes including an etching process, and such a wafer stage includes a notch aligner of a wafer that aligns the wafer's etch. ) Is installed.

종래에는 도 1에 도시한 바와 같이, 웨이퍼(1)의 가장자리에 노치(2)를 형성하여 이러한 노치(2)의 위치를 감지함으로써 다수의 웨이퍼를 얼라인 시키고 있다.Conventionally, as shown in FIG. 1, a plurality of wafers are aligned by forming a notch 2 at the edge of the wafer 1 to sense the position of the notch 2.

그러나, 종래와 같이 웨이퍼(1)에 형성되는 노치(2)는 1.25mm 가량의 크기로 형성되므로 반도체 제조 공정에 따른 각종 온도 변화 및 외부 충격에 의해 웨이퍼가 파손되거나, 크랙이 발생되는 원인으로 작용되는 문제가 있다However, since the notch 2 formed on the wafer 1 has a size of about 1.25 mm as in the related art, the wafer is broken or cracked due to various temperature changes and external shocks according to the semiconductor manufacturing process. There is a problem

본 발명의 목적은 반도체 웨이퍼의 얼라인을 실시하기 위해 웨이퍼가 변형되어 웨이퍼가 손상되거나 파손되어 발생되는 생산성 저하를 방지하려는 데 있다.An object of the present invention is to prevent a decrease in productivity caused by the deformation of the wafer to damage or break the wafer in order to align the semiconductor wafer.

본 발명에 따른 반도체 웨이퍼는 웨이퍼의 표면에 얼라인 기준점인 얼라인 표시부를 형성한 것을 특징으로 한다.The semiconductor wafer according to the present invention is characterized in that the alignment display portion, which is an alignment reference point, is formed on the surface of the wafer.

상기 얼라인 표시부는 상기 웨이퍼의 표면에 색상의 형태로 형성된 것이 바람직하다.The alignment display unit is preferably formed in the form of color on the surface of the wafer.

상기 색상은 레드(Red), 그린(Green), 블루(Blue)나, 이들이 혼합된 색상중 선택되는 하나의 색상인 것이 바람직하다.The color is preferably red, green, blue, or one color selected from mixed colors thereof.

상기 얼라인 표시부는 상기 웨이퍼의 가장자리 표면에 형성된 것이 바람직하다.The alignment display unit is preferably formed on the edge surface of the wafer.

본 발명에 따른 반도체 웨이퍼의 얼라인 장치는 웨이퍼의 가장자리 표면에 얼라인 표시부가 형성된 웨이퍼와; 상기 웨이퍼를 얼라인하기 위하여 상기 웨이퍼의 얼라인 표시부를 감지하는 센서;를 포함하는 것을 특징으로 한다.An alignment apparatus for a semiconductor wafer according to the present invention comprises: a wafer on which an alignment display portion is formed on an edge surface of the wafer; And a sensor for sensing an alignment display unit of the wafer to align the wafer.

상기 센서는 색감지 센서인 것이 바람직하다.Preferably, the sensor is a color sensor.

이와 같은 본 발명에 따른 반도체 웨이퍼는 웨이퍼의 물리적인 변형을 가하지 않고 표면에 간단한 색상을 도포하여 웨이퍼의 얼라인 표시가 가능하므로 반도 체 제조 공정중에 웨이퍼가 손상되거나, 파손되는 문제점을 해소하게 된다.Such a semiconductor wafer according to the present invention can solve the problem that the wafer is damaged or broken during the semiconductor manufacturing process because it is possible to align the wafer by applying a simple color to the surface without applying a physical deformation of the wafer.

또한, 본 발명에 따른 반도체 웨이퍼 얼라인 장치는 색감지 센서에 의해 웨이퍼의 얼라인 작업을 간편하게 실시할 수 있게 되어 얼라인 작업이 신속하고 간단하게 이루어져 생산성이 향상되는 효과가 있다.In addition, the semiconductor wafer alignment apparatus according to the present invention can easily perform the alignment operation of the wafer by the color sensor, the alignment operation is made quickly and simply has the effect of improving the productivity.

이하, 상기한 바와 같은 본 발명의 바람직한 실시예를 첨부도면에 의거하여 보다 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention as described above will be described in more detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 반도체 웨이퍼의 평면도이고, 도 3은 본 발명에 따른 반도체 웨이퍼의 얼라인 장치의 구성도이다.2 is a plan view of a semiconductor wafer according to the present invention, and FIG. 3 is a configuration diagram of an alignment device of the semiconductor wafer according to the present invention.

도 2 및 도 3을 참조하면, 본 발명의 일 실시예에 따른 반도체 웨이퍼는 얼라인을 갖는 기준점을 웨이퍼(11)의 표면에 얼라인 표시부(12)를 형성하여 구성함을 특징으로 한다.2 and 3, the semiconductor wafer according to the embodiment of the present invention is configured by forming an alignment display unit 12 on the surface of the wafer 11 with a reference point having an alignment.

상기 얼라인 표시부(12)는 웨이퍼의 바디의 가장자리 표면에 색상의 형태로 형성된다. The alignment display unit 12 is formed in the form of color on the edge surface of the body of the wafer.

상기 얼라인 표시부(12)로 형성되는 색상은 다양한 색상을 선택적으로 실시할 수 있다. 바람직하기는 색 감지 센서에 의해 감지되기에 적합한 색상을 사용한다. 예를 들면 레드(Red), 그린(Green), 블루(Blue) 와 같은 색상을 사용할 수 있다. 또는 이들이 혼합된 색상 중 선택되는 하나의 색상이 사용된다.The color formed by the alignment display unit 12 may be selectively implemented in various colors. Preferably a color is used that is suitable for detection by a color detection sensor. For example, you can use colors such as Red, Green, and Blue. Or one color selected from the mixed colors thereof is used.

상기 얼라인 표시부(12)는 상기 웨이퍼(11)의 가장자리 단부에서 1~1.25mm이내의 영역에서 형성되는 것이 바람직하다. The alignment display unit 12 is preferably formed in an area of 1 to 1.25 mm from the edge end of the wafer 11.

이와 같이 본 발명에 따른 반도체 웨이퍼는 웨이퍼(11)의 가장자리 표면에 얼라인 표시부(12)가 형성되므로 웨이퍼에 변형을 가하지 않고도 얼라인의 기준점을 설정할 수 있다. As described above, in the semiconductor wafer according to the present invention, since the alignment display unit 12 is formed on the edge surface of the wafer 11, the reference point of the alignment can be set without modifying the wafer.

본 발명은 이러한 얼라인 기준점으로서 얼라인 표시부(12)가 색상으로 표시된다. 즉, 웨이퍼(11)의 가장자리 표면에 색상이 도포되는 것에 의하여 얼라인 표시부(12)가 형성된다. 따라서 웨이퍼 바디에 변형이 발생되지 않으므로 반도체 제조 공정 도중에 웨이퍼에 크랙이 발생되거나 파손되지 않게 된다.In the present invention, the alignment display unit 12 is displayed in color as the alignment reference point. That is, the alignment display unit 12 is formed by applying color to the edge surface of the wafer 11. Therefore, no deformation occurs in the wafer body, so that cracks do not occur or break in the wafer during the semiconductor manufacturing process.

본 발명의 실시예에서는 얼라인 표시부(12)를 색상으로 표시하는 것에 대하여 설명하였으나, 색상과 등가의 성질을 갖는 표시형태이면 어느 것이든 가능함은 당연하다 할 것이다.In the exemplary embodiment of the present invention, the display of the alignment display unit 12 in color has been described. However, any display form having a property equivalent to the color may be used.

다음에는 본 발명의 일 실시예에 따른 반도체 웨이퍼를 이용하여 웨이퍼를 얼라인 하는 장치에 대하여 설명한다.Next, an apparatus for aligning a wafer using a semiconductor wafer according to an embodiment of the present invention will be described.

본 발명에 따른 반도체 웨이퍼는 웨이퍼(11)의 가장자리 표면에 얼라인 표시부(12)가 형성된다. 따라서 반도체 웨이퍼를 얼라인하기 위한 장치(20)는 상기 얼라인 표시부(12)를 감지하기 위한 센서(22)를 구비하여 구성한다.In the semiconductor wafer according to the present invention, the alignment display portion 12 is formed on the edge surface of the wafer 11. Therefore, the apparatus 20 for aligning the semiconductor wafer includes a sensor 22 for sensing the alignment display unit 12.

본 발명에 따른 반도체 웨이퍼의 얼라인 표시부(12)는 색상이 도포되어 형성되므로 상기 센서(22)는 색감지 센서인 것이 바람직하다.Since the alignment display unit 12 of the semiconductor wafer according to the present invention is formed by applying color, the sensor 22 is preferably a color sensor.

이와 같이 구성되는 본 발명에 따른 반도체 웨이퍼의 얼라인 장치에 의해 반도체 웨이퍼를 얼라인 하는 동작을 설명한다.An operation of aligning the semiconductor wafer by the alignment apparatus of the semiconductor wafer according to the present invention configured as described above will be described.

본 발명에 따른 얼라인 감지 장치(20)는 색감지 센서(22)가 웨이퍼(11)의 가 장자리에 형성된 얼라인 표시부(12)를 감지하게 된다.In the alignment sensing device 20 according to the present invention, the color sensor 22 detects the alignment display unit 12 formed at the edge of the wafer 11.

즉, 상기 색감지 센서(22)에서 발광 되는 빛이 웨이퍼(11)의 표면에 도달하며, 웨이퍼(11)의 표면에서 반사된 빛 중에서 얼라인 표시부(12)에서 반사된 빛의 파장중에서 색감지 센서(22)는 얼라인 표시부(12)에서 반사된 빛의 파장을 감지하게 된다.That is, the light emitted from the color sensor 22 reaches the surface of the wafer 11, and among the light reflected from the surface of the wafer 11, the color is detected in the wavelength of the light reflected from the alignment display unit 12. The sensor 22 detects the wavelength of the light reflected by the alignment display unit 12.

따라서 웨이퍼(11)의 표면에 도포된 색상에 의해 웨이퍼의 얼라인이 이루어지므로 웨이퍼에 노치를 형성하지 않고도 얼라인이 이루어지게 되어 반도체 제조공정에 따른 각가지 조건에 의해 웨이퍼(11)가 손상되거나 파손되지 않게 된다.Therefore, since the alignment of the wafer is made by the color applied to the surface of the wafer 11, the alignment is made without forming a notch on the wafer, and the wafer 11 is damaged or broken by various conditions according to the semiconductor manufacturing process. Will not be.

아울러 웨이퍼의 얼라인 작업이 색감지 센서(22)에 의해서 실시되므로 얼라인 공정도 신속하고 간단하게 이루어지는 이점이 있다.In addition, since the alignment operation of the wafer is performed by the color sensor 22, there is an advantage that the alignment process is also quick and simple.

도 1은 종래 기술에 의한 반도체 웨이퍼의 평면도.1 is a plan view of a semiconductor wafer according to the prior art.

도 2는 본 발명에 따른 반도체 웨이퍼의 평면도.2 is a plan view of a semiconductor wafer according to the present invention;

도 3은 본 발명에 따른 반도체 웨이퍼의 얼라인 장치의 구성도.3 is a configuration diagram of an alignment device for semiconductor wafers according to the present invention;

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

11 ; 웨이퍼11; wafer

12 ; 얼라인 표시부12; Alignment Display

20 ; 웨이퍼 얼라인 장치20; Wafer alignment device

22 ; 색감지 센서22; Color sensor

Claims (6)

웨이퍼의 바디의 표면에 얼라인 기준점인 얼라인 표시부를 형성한 것을 특징으로 하는 반도체 웨이퍼.A semiconductor wafer, wherein an alignment display portion, which is an alignment reference point, is formed on a surface of a body of a wafer. 제 1 항에 있어서,The method of claim 1, 상기 얼라인 표시부는 상기 웨이퍼의 표면에 색상의 형태로 형성된 것을 특징으로 하는 반도체 웨이퍼.The alignment display unit is a semiconductor wafer, characterized in that formed in the form of color on the surface of the wafer. 제 2 항에 있어서,The method of claim 2, 상기 색상은 레드(Red), 그린(Green), 블루(Blue)나, 이들이 혼합된 색상중 선택되는 하나의 색상인 것을 특징으로 하는 반도체 웨이퍼.The color is a semiconductor wafer, characterized in that the color is selected from red, green, blue, or a mixture of these colors. 제 1 항에 있어서,The method of claim 1, 상기 얼라인 표시부는 상기 웨이퍼의 가장자리 표면에 형성된 것을 특징으로 하는 반도체 웨이퍼.And the alignment display unit is formed on an edge surface of the wafer. 웨이퍼의 가장자리 표면에 얼라인 표시부가 형성된 웨이퍼와;A wafer on which an alignment display portion is formed on an edge surface of the wafer; 상기 웨이퍼를 얼라인하기 위하여 상기 웨이퍼의 얼라인 표시부를 감지하는 센서;를 포함하는 반도체 웨이퍼의 얼라인 장치.And a sensor for sensing an alignment display unit of the wafer to align the wafer. 제 5 항에 있어서,The method of claim 5, 상기 센서는 색감지 센서인 것을 특징으로 하는 반도체 웨이퍼의 얼라인 장치.And the sensor is a color sensing sensor.
KR1020080134199A 2008-12-26 2008-12-26 Semiconductor wafer and align appartus uing it KR20100076235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080134199A KR20100076235A (en) 2008-12-26 2008-12-26 Semiconductor wafer and align appartus uing it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080134199A KR20100076235A (en) 2008-12-26 2008-12-26 Semiconductor wafer and align appartus uing it

Publications (1)

Publication Number Publication Date
KR20100076235A true KR20100076235A (en) 2010-07-06

Family

ID=42637976

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080134199A KR20100076235A (en) 2008-12-26 2008-12-26 Semiconductor wafer and align appartus uing it

Country Status (1)

Country Link
KR (1) KR20100076235A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019104158A1 (en) * 2017-11-22 2019-05-31 Gerber Technology Llc Method and apparatus for aligning sheet material

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019104158A1 (en) * 2017-11-22 2019-05-31 Gerber Technology Llc Method and apparatus for aligning sheet material
CN111372737A (en) * 2017-11-22 2020-07-03 格伯技术有限责任公司 Method and apparatus for calibrating sheet material
US10961076B2 (en) 2017-11-22 2021-03-30 Gerber Technology Llc Method and apparatus for aligning sheet material
CN111372737B (en) * 2017-11-22 2022-01-04 格伯技术有限责任公司 Method and apparatus for calibrating sheet material

Similar Documents

Publication Publication Date Title
KR20080054596A (en) Apparatus for inspecting flat panel display and method thereof
US9927719B2 (en) Overlay sampling methodology
US20020141477A1 (en) Thin film thickness monitoring method and substrate temperature measuring method
US6094965A (en) Semiconductor calibration structures and calibration wafers for ascertaining layer alignment during processing and calibrating multiple semiconductor wafer coating systems
KR20190016695A (en) Wafer alignment method and wafer inspection method using the same
US6952255B2 (en) System and method for integrated multi-use optical alignment
KR20100076235A (en) Semiconductor wafer and align appartus uing it
JP2007305952A (en) Substrate alignment method
US9899334B1 (en) Methods and apparatus for alignment marks
US20220310437A1 (en) Semiconductor manufacturing apparatus and method for manufacturing semiconductor device
KR101902603B1 (en) Method of inspecting display cells
CN110491813B (en) Double-sided wafer boat, wafer overturning device and wafer overturning method
KR100893878B1 (en) Method for displaying semiconductor manufacture process
US8045150B2 (en) Semiconductor wafer inspection method
JP5621395B2 (en) Manufacturing method of semiconductor device
TW586181B (en) Method of fabricating shallow trench isolation
KR100709590B1 (en) Cluster-type bevel etch apparatus
KR101561786B1 (en) Method of aligning a wafer image and method of inspecting a wafer
CN107342240B (en) Method for detecting silicon nitride residue on surface of wafer
KR20050011403A (en) Semiconductor etching apparatus having a wafer detecting sensor in a shadow ring, and etching method using the same
TWI271506B (en) Method for inspecting a chip tray
KR20050112361A (en) Apparatus for manufacturing a substrate
JPH06104335A (en) Semiconductor wafer
KR100943496B1 (en) Apparatus for manufacturing semiconductor device having calibration blade and method for measuring center between wafers using the calibration blade
KR100855496B1 (en) Method for detecting end point of plasma etching process

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination