KR20100074625A - Method of forming channel junction for semiconductor device - Google Patents

Method of forming channel junction for semiconductor device Download PDF

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Publication number
KR20100074625A
KR20100074625A KR1020080133113A KR20080133113A KR20100074625A KR 20100074625 A KR20100074625 A KR 20100074625A KR 1020080133113 A KR1020080133113 A KR 1020080133113A KR 20080133113 A KR20080133113 A KR 20080133113A KR 20100074625 A KR20100074625 A KR 20100074625A
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KR
South Korea
Prior art keywords
ion implantation
semiconductor substrate
semiconductor device
channel junction
implantation process
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Application number
KR1020080133113A
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Korean (ko)
Inventor
곽노열
함철영
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주식회사 하이닉스반도체
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Priority to KR1020080133113A priority Critical patent/KR20100074625A/en
Publication of KR20100074625A publication Critical patent/KR20100074625A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention comprises a method of forming a channel junction of a semiconductor device, comprising performing an ion implantation process on a semiconductor substrate using an ion implantation apparatus that injects distilled water and a coolant into the chuck to lower the temperature of the semiconductor substrate. .

Description

Method of forming channel junction of semiconductor device {Method of forming channel junction for semiconductor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming channel junctions in semiconductor devices, and more particularly, to a method for forming channel junctions in semiconductor devices for improving electrical characteristics by performing low temperature ion implantation.

The semiconductor device includes a plurality of devices (eg, gate patterns) formed on the silicon substrate. In order to electrically connect the gate patterns, an ion implantation process of implanting impurities into the semiconductor substrate is performed.

Specifically, a well may be formed in a semiconductor substrate by an ion implantation process, and the threshold voltage distribution of a gate pattern to be subsequently formed may vary according to the dopant, dopant concentration, or energy injected into the well. In particular, the channel junction may be a threshold voltage control region (Vt region). Since the well and channel junction region (Vt region) are formed before forming the elements (eg, the gate patterns) on the semiconductor substrate, the memory cell and gate patterns to be subsequently formed are formed in the well and It is formed within the range of the channel junction region (Vt region).

Meanwhile, as the degree of integration of semiconductor devices increases, the ion implantation process is performed at a higher dose in order to secure electrical characteristics of the gate patterns. In addition, also in the element isolation structure, the LOCOS structure is changed from the LOCOS structure to the STI structure in order to secure a larger area of the element isolation structure. The STI structure is deeper and narrower than the LOCOS structure. That is, the width of the trench is narrower and deeper.

In particular, since the device isolation structure is also formed on the semiconductor substrate in which the well and the channel junction region are formed, the exposed area of the semiconductor substrate may be increased during the etching process for forming the trench, which may damage the trench. May occur.

As such, the stress that the semiconductor device receives increases with the change in the structure and manufacturing process of the semiconductor device due to the increase in the degree of integration of the semiconductor device. In particular, the stress of the channel junction in the semiconductor substrate increases. This stress may grow into a defect during a subsequent heat treatment process, and thus, disturbance may occur. In addition, as the channel length decreases, a large mass dopant (for example, BF 2 ) is injected to implement a channel junction by a shallow junction. However, when a large amount of impurities are injected, the stress on the semiconductor substrate is further increased.

1 is a photograph for explaining a problem of a conventional semiconductor device.

Referring to FIG. 1, a flash device will be described as an example.

In the flash device, an isolation layer 20 is formed on a semiconductor substrate 10, and a gate insulating layer 12 and a floating gate 14 are formed on an active region of the semiconductor substrate 10. At this time, the channel junction region is formed in the active region by an ion implantation process. In particular, when the ion implantation process of injecting a high mass of impurities as described above is performed, defects may be generated while heat is generated due to the collision of impurities with the semiconductor substrate. In particular, when a defect occurs in the active region of the semiconductor substrate 10, electrical characteristics may deteriorate during operation of the semiconductor device, thereby reducing reliability.

The problem to be solved by the present invention can suppress the phenomenon that the temperature of the semiconductor substrate rises by performing a low temperature ion implantation step in the semiconductor channel junction formation step.

In the method of forming a channel junction of a semiconductor device according to an embodiment of the present invention, an ion implantation process is performed on a semiconductor substrate by using an ion implantation apparatus which lowers the temperature of the semiconductor substrate by injecting distilled water and a coolant into the chuck. The channel junction forming method of a semiconductor device comprising a step.

At this time, the coolant uses glycoethyl (glycolethylene).

In a method of forming a channel junction of a semiconductor device according to another embodiment of the present invention, an ion implantation process is performed on a semiconductor substrate by using an ion implantation apparatus that injects N 2 gas into the chuck to lower the temperature of the semiconductor substrate. The channel junction forming method of the semiconductor device comprising a step.

In the present invention, the temperature rise of the semiconductor substrate can be suppressed by performing a low temperature ion implantation step in the channel junction formation step of the semiconductor element. As a result, the yield can be increased during the manufacturing process of the semiconductor device, and the reliability of the semiconductor device can be improved by preventing degradation of electrical characteristics of the semiconductor device.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2A to 2C are cross-sectional views illustrating a method of forming channel junctions in a semiconductor device according to the present invention.

Referring to FIG. 2A, a flash device will be described as an example.

A screen film 202 is formed on the semiconductor substrate 200 to suppress surface damage. The screen film 202 may be formed of an oxide film. The first mask pattern 204 for the first ion implantation process is formed on the screen layer 202. The first mask pattern 204 has a pattern in which openings are formed in the cell region and the peripheral circuit region. When the semiconductor substrate 200 is a P type silicon substrate, the first ion implantation process may inject an N type impurity into the exposed semiconductor substrate 200 according to the first mask pattern 204. Conduct. In the first ion implantation process, triple N wells (TNWs) are formed in the cell region and the peripheral circuit region of the semiconductor substrate, respectively.

Referring to FIG. 2B, after removing the first mask pattern 204 of FIG. 2A, a second mask pattern 206 for the second ion implantation process is formed on the screen layer 202. A second well implanting process is performed according to the second mask pattern 206 to form a P well P inside the triple N well TNW in the cell region and the triple N well TNW in the peripheral circuit region. do. At this time, the P well PW for forming the low voltage NMOS transistor LVN is simultaneously formed in the semiconductor substrate 200 between the triple N well TNW in the cell region and the triple N well TNW in the peripheral circuit region. In addition, the P well PW formed in the peripheral circuit region becomes a P well for forming triple low voltage NMOS (TLVN). The second ion implantation process is preferably performed by implanting P-type impurities into the semiconductor substrate 200. Specifically, the second ion implantation process may use B 11 as a P-type impurity.

Referring to FIG. 2C, the second mask pattern 206 of FIG. 2B is removed. Subsequently, a third mask pattern 208 for the third ion implantation process is formed on the screen layer 202. The third mask pattern 208 is an ion implantation process for forming a channel junction for adjusting the threshold voltage in the cell region.

In the third ion implantation process, it is preferable to inject a dopant having a large mass due to an increase in the degree of integration of the semiconductor device. For example, the third ion implantation process may be performed by injecting BF 2 as a dopant at a concentration of 1 × 10 11 ion / cm 2 to 1 × 10 14 ion / cm 2 , and provides an energy region of 5KeV to 50K. It is preferable to carry out by addition. At this time, it is preferable to perform the tilted ion implantation process in order to maximize the ion collision of impurities. For example, the tilt ion implantation process may be performed by setting the incident angle of the impurity at the time of ion implantation to 3 ° to 45 °.

In particular, since a high mass impurity (eg, BF 2 ) generates heat while colliding with the semiconductor substrate 200, a third ion implantation process is performed to prevent the temperature of the semiconductor substrate 200 from rising. It is preferable to perform silver by a low temperature ion implantation process.

For example, the low temperature ion implantation process can be carried out using ion implantation equipment capable of low temperature control. The ion implantation apparatus capable of low temperature control may lower the temperature of a chuck that loads the semiconductor substrate 200 using N 2 gas. That is, the temperature may be lowered by injecting N 2 gas into the chuck. In this case, the temperature of the semiconductor substrate may be adjusted to be −10 ° C. to 10 ° C. by lowering the temperature of the chuck. Alternatively, in order to lower the temperature of the chuck, distilled water (DI water) and a coolant may be injected into the chuck. The coolant may use glycoethyl.

As such, when the temperature rise of the semiconductor substrate 200 is suppressed in the ion implantation process, the temperature rise that may occur due to the collision of ions (impurities) injected into the semiconductor substrate 200 may be suppressed. As a result, since the temperature rise of the channel junction Vt of the semiconductor substrate 200 can be prevented and defects can be suppressed, the yield of the semiconductor device can be increased, and the reliability is improved due to the improvement of the electrical characteristics. You can.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a photograph for explaining a problem of a conventional semiconductor device.

2A to 2C are cross-sectional views illustrating a method of forming a threshold voltage regulating region of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 200: semiconductor substrate 12: gate insulating film

14 floating gate 20 device isolation film

202: screen film 204: first mask pattern

206: second mask pattern 208: third mask pattern

TNW: Triple N Well PW: P Well

Vt: Threshold Voltage Controlled Area

Claims (3)

A method of forming a channel junction in a semiconductor device, comprising the step of implanting distilled water and a coolant into a chuck to reduce the temperature of the semiconductor substrate. The method of claim 1, The coolant is a method of forming a channel junction of a semiconductor device using glycoethyl (glycolethylene). A method of forming a channel junction in a semiconductor device, comprising the step of performing an ion implantation process on a semiconductor substrate using an ion implantation apparatus that injects N 2 gas into the chuck to lower the temperature of the semiconductor substrate.
KR1020080133113A 2008-12-24 2008-12-24 Method of forming channel junction for semiconductor device KR20100074625A (en)

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KR1020080133113A KR20100074625A (en) 2008-12-24 2008-12-24 Method of forming channel junction for semiconductor device

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KR1020080133113A KR20100074625A (en) 2008-12-24 2008-12-24 Method of forming channel junction for semiconductor device

Publications (1)

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KR20100074625A true KR20100074625A (en) 2010-07-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012061130A2 (en) * 2010-10-25 2012-05-10 Texas Instruments Incorporated Low temperature implant to improve bjt current gain

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012061130A2 (en) * 2010-10-25 2012-05-10 Texas Instruments Incorporated Low temperature implant to improve bjt current gain
WO2012061130A3 (en) * 2010-10-25 2012-06-28 Texas Instruments Incorporated Low temperature implant to improve bjt current gain
CN103180934A (en) * 2010-10-25 2013-06-26 德克萨斯仪器股份有限公司 Low temperature implant to improve BJT current gain
US8772103B2 (en) 2010-10-25 2014-07-08 Texas Instruments Incorporated Low temperature implant scheme to improve BJT current gain

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