KR20100074406A - Apparatus of protecting semiconductor device from the electro static discharge, and method for manufactruing the same - Google Patents

Apparatus of protecting semiconductor device from the electro static discharge, and method for manufactruing the same Download PDF

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Publication number
KR20100074406A
KR20100074406A KR1020080132820A KR20080132820A KR20100074406A KR 20100074406 A KR20100074406 A KR 20100074406A KR 1020080132820 A KR1020080132820 A KR 1020080132820A KR 20080132820 A KR20080132820 A KR 20080132820A KR 20100074406 A KR20100074406 A KR 20100074406A
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KR
South Korea
Prior art keywords
conductivity type
well
conductive
deep well
forming
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Application number
KR1020080132820A
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Korean (ko)
Inventor
송종규
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주식회사 동부하이텍
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Priority to KR1020080132820A priority Critical patent/KR20100074406A/en
Publication of KR20100074406A publication Critical patent/KR20100074406A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

An electrostatic discharge protection device and a method of manufacturing the same are provided. The electrostatic discharge protection device may include a first conductive deep well formed on a substrate in a semiconductor substrate, a first conductive well formed in the first conductive deep well, and spaced apart from the first conductive well. A second conductivity type first well formed; a second conductivity type second well formed in the second conductivity type first well; a first conductivity type emitter region formed in the second conductivity type second well; And a second conductivity type base region formed in the second conductivity type first well, and a first conductivity type collector region formed in the first conductivity type well.

Description

Electrostatic discharge protection device and its manufacturing method {Apparatus of protecting Semiconductor device from the Electro Static Discharge, and method for manufactruing the same}

The present invention relates to a semiconductor device, and more particularly to an electrostatic discharge protection device of the semiconductor device.

Electrostatic discharge (ESD) protection circuits are used to protect integrated circuits from static electricity. High drive voltages are used, and high voltage integrated circuits that operate in environments susceptible to static electricity, such as automobiles, require a higher level of ESD protection than conventional logic integrated circuits.

In general, bipolar junction transistors use NPN or PNP structures, and two PN junctions with a thin middle layer are coupled to each other. When a forward bias is applied to the PN junction, electrons are injected from the first N region to the P region, and holes are injected from the P region to the first N region.

The first N region is called an emitter because it emits electrons, and the P region where injection of minority carriers occurs is called a base. The electrons injected into the base are diffused through the neutral base region with little consumption due to recombination because the thickness of the base is sufficiently smaller than the diffusion length of the electrons. These electrons drift by the electric field and cross the space charge region of the reverse biased PN junction to the second N region. In this case, the second N region is called a collector.

The bipolar may be used as an electrostatic device for protecting an internal IC. When designing the circuit, you must configure the input or output, which must be configured for the internal circuit operating voltage.

1 shows an equivalent circuit of an electrostatic device using a general bipolar. Referring to FIG. 1, in order to use a bipolar as an electrostatic device, a collector 115 is connected to an input / output terminal 110 and an emitter 120 is connected to a ground 105. At this time, the base 125 is connected to the ground terminal 105 through the resistor 130.

The role of the electrostatic element is to remove the applied instantaneous voltage to the ground 105 terminal when the instantaneous voltage is applied to the input and output terminal 110 or more. If bipolar is used as an electrostatic device, when the collector is supplied with an instantaneous voltage, the applied instantaneous voltage must be forced out of the base region past the emitter.

To be used as an electrostatic device, parameters such as triggering voltage, holding voltage, and breakdown voltage must be satisfied.

2 is a graph showing a design range of a general electrostatic device. Referring to FIG. 2, an operating voltage of an electrostatic device is determined according to an operating voltage of an internal circuit to be protected. The triggering voltage Vt1 of the electrostatic element should be lower than the triggering voltage of the internal circuit element connected to the input / output. The holding voltage Vh of the electrostatic element must be higher than the operating voltage of the internal circuit element. In addition, the breakdown voltage Bv2 of the electrostatic element should be between the operating voltage and the triggering voltage of the internal circuit.

In order to develop an electrostatic device that satisfies the above conditions, the bipolar structure or the process conditions must be modified. Changing the bipolar structure may require additional masks and affect the manufacturing cycle depending on the process conditions.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an electrostatic discharge protection device capable of increasing a sustain voltage and a method of manufacturing the same.

An electrostatic discharge protection device according to an embodiment of the present invention for achieving the above object is a first conductivity type deep well formed on a substrate on a semiconductor substrate, a first conductivity type well formed on the first conductive deep well, the first A second conductivity type first well formed in the first conductivity type deep well spaced apart from a first conductivity type well, a second conductivity type second well formed in the second conductivity type first well, and the second conductivity type second well And a first conductivity type emitter region formed in the well, a second conductivity type base region formed in the second conductivity type first well, and a first conductivity type collector region formed in the first conductivity type well.

To form a first conductive buried layer by selectively injecting a first conductivity type impurity into a semiconductor substrate in accordance with an embodiment of the present invention for achieving the above object, selectively forming a first conductivity type impurity on the semiconductor substrate Implanting to form a first conductivity type deep well on the first conductivity type buried layer, forming a first conductivity type well on the first conductivity type deep well, and a second conductivity type first on the first conductivity type deep well Forming a well, forming a second conductive second well having a higher impurity concentration than the second conductive first well in the first conductive deep well, and forming a second well in the second conductive second well. Implanting an impurity region of a first conductivity type to form an emitter region, implanting an impurity of a second conductivity type into the second well type first well, and forming a base region in the first conductivity type well 1 conductivity type impurity By injection and forming a collector region.

The method of forming an electrostatic discharge protection device may include forming a first conductive buried layer in contact with a lower portion of the first conductive deep well, and contacting a side surface of the first conductive deep well so as to surround the first conductive deep well. The method may further include forming a first conductive vertical doping layer vertically from a substrate surface to the first conductive buried layer.

The electrostatic discharge protection device and its manufacturing method according to an embodiment of the present invention is higher than the concentration of the first well in which the base is formed using a well forming process already used in the existing process without adding a new process. A second well having a concentration is formed, and an emitter is formed in the second well thus formed, thereby reducing the efficiency of the emitter, thereby increasing the sustain voltage.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

For better understanding of the present invention, it is assumed that the first conductivity type is n type and the second conductivity type is p type. That is, in the following, an npn bipolar transistor is used as an ESD device. However, the present invention can be applied on the same principle even when the first conductivity type is p type and the second conductivity type is n type.

3 is a cross-sectional view showing an electrostatic discharge protection device 300 according to an embodiment of the present invention. Referring to FIG. 3, the electrostatic discharge protection device 300 includes a semiconductor substrate 301, a first conductive buried layer 305, a first conductive deep well 310, a first conductive well 315, and a second Conductive first well 320, second conductive second well 325, first conductive vertical doping layer 330, isolation layer 340, emitter region 352, base region 354, and Collector region 356 is included.

The first conductivity type buried layer 305 may be formed by selectively implanting first conductivity type impurities into the semiconductor substrate 301. The first conductivity type deep well 310 may be formed in the semiconductor substrate on the first conductivity type buried layer 305 by selectively implanting a first conductivity type impurity into the semiconductor substrate 310.

A first conductivity type well 315, a second conductivity type first well 320, and a second conductivity type second well 325 are formed in the first conductivity type deep well 310. The second conductivity type first well 320 may be formed to be spaced apart from the first conductivity type well 315, and may contact the second conductivity type second well 325.

The first conductivity type vertical doping layer 330 is formed vertically from the surface of the semiconductor substrate 301 to the first conductivity type buried layer 305 so as to surround the first conductivity type deep well 310. In this case, since the first conductivity type deep well 310 is surrounded by the first conductivity type buried layer 305 and the first conductivity type vertical doping layer 330, the electrostatic discharge protection device and the surroundings may be electrically connected to each other. Shielding can be achieved to prevent leakage currents.

In this case, the first conductivity type vertical doping layer 330 has a high concentration on top thereof for ohmic contact, and at least a first conductivity having a concentration higher than that injected during the formation of the first conductivity type vertical doping layer 330. The region 351 into which the impurity is implanted may be formed.

The device isolation layer 340 is formed in the semiconductor substrate for device isolation. The device isolation layer 340 includes a plurality of device isolation structures 340-2 to 340-6.

The emitter region 352 may be formed by implanting a first conductivity type impurity (N +) into the second conductivity type second well 325. The base region 354 may be formed by implanting a second conductivity type impurity P + into the second conductivity type first well 320. The collector region 356 may be formed by implanting a first conductivity type impurity (N +) into the first conductivity type well 315. In this case, the second conductivity type second well 325 has a higher concentration of impurity implanted than the second conductivity type first well 320.

The device isolation structures 340-2 through 340-6 electrically isolate the emitter region 352, the base region 354, and the collector region 356. For example, the device isolation structures 340-3 and 340-4 may be formed between the emitter region 352 and the base region 354, between the base region 352 and the collector region 356. Can be formed on.

The total emitter current I E is the sum of the first current I nE formed by the electrons of the emitter moving to the base and the second current I pE by holes entering the emitter from the base (I E) = I nE + I pE ).

The ratio between total current and actual useful current is called emitter efficiency (r E ). That is, the emitter efficiency is equal to r E = I nE / I E.

To reduce the efficiency of the emitter, the actual current I nE should be as small as possible and I pE should be as large as possible. Although the first current I nE and the second current I pE are exponentially dependent on the forward bias voltage VBE, the first current I nE and the second current I pE are emitter regions ( It depends on the majority carrier concentration of electrons in 352 and holes in base region 354.

In order to minimize the first current I nE and maximize the second current I pE , the doping concentration of the emitter region 352 should be low and the doping concentration of the base region 354 should be as high as possible.

 The concentration of the second conductivity type second well 325 in which the emitter region 354 is formed is higher than that of the second conductivity type first well 320 so that the first conductivity type impurities may be formed in the second conductivity type agent. The doping concentration of emitter region 352 implanted into two wells 325 is relatively low.

4 is a graph showing current-voltage characteristics of the electrostatic discharge protection device shown in FIG. Here, the current on the y-axis is the collector-emitter current of the bipolar electrostatic discharge protection element, and the voltage on the x-axis represents the voltage of the collector-emitter.

The first graph g1 is a current-voltage characteristic of the general electrostatic discharge protection element, and the second graph g2 is a current-voltage characteristic of the electrostatic discharge protection element shown in FIG. 3.

As shown in FIG. 4, it is understood that the sustain voltage Vh1 of the general electrostatic discharge protection device when the inflow of static electricity is about 23V, and that the sustain voltage Vh2 of the electrostatic discharge protection device according to the embodiment of the present invention is about 26V. Can be. In other words, the holding voltage increases by approximately 3V.

The electrostatic discharge protection device according to the embodiment of the present invention may have a higher concentration than the concentration of the first well in which the base is formed by using a well forming process that is already used in the existing process without adding a new process. By forming two wells and forming an emitter in the second well thus formed, the efficiency of the emitter can be lowered, thereby increasing the sustain voltage.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 shows an equivalent circuit of an electrostatic device using a general bipolar.

2 is a graph showing a design range of a general electrostatic device.

3 is a cross-sectional view showing an electrostatic discharge protection device according to an embodiment of the present invention.

4 is a graph showing current-voltage characteristics of the electrostatic discharge protection device shown in FIG.

Claims (6)

A first conductivity type deep well formed on the substrate in the semiconductor substrate; A first conductivity type well formed in the first conductivity type deep well; A second conductive first well formed in the first conductive deep well spaced apart from the first conductive well; A second conductivity type second well formed in the second conductivity type first well; A first conductivity type emitter region formed in the second conductivity type second well; A second conductivity type base region formed in the second conductivity type first well; And And a first conductivity type collector region formed in said first conductivity type well. The method of claim 1, The impurity concentration of the second conductivity type second well is higher than the impurity concentration of the second conductivity type first well. The method of claim 1, wherein the electrostatic discharge protection element, A first conductivity type buried layer formed in contact with a lower portion of the first conductivity type deep well; And And a first conductivity type vertical doping layer contacting a side surface of the first conductivity type deep well to surround the first conductivity type deep well and vertically formed from a surface of the semiconductor substrate to the first conductivity type buried layer. Electrostatic discharge protection element. The device of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. Selectively implanting first conductivity type impurities into the semiconductor substrate to form a first conductivity type buried layer; Selectively implanting first conductivity type impurities into the semiconductor substrate to form a first conductivity type deep well on the first conductivity type buried layer; Forming a first conductivity type well in the first conductivity type deep well; Forming a second conductivity type first well in the first conductivity type deep well; Forming a second conductivity type second well in the first conductivity type deep well having a higher impurity concentration than the second conductivity type first well; Implanting an impurity of a first conductivity type into the second conductivity type second well to form an emitter region; Implanting a second conductivity type impurity into the second conductivity type first well to form a base region; And And forming a collector region by injecting a first conductivity type impurity into the first conductivity type well. The method of claim 5, wherein the electrostatic discharge protection element forming method is Forming a first conductive buried layer in contact with a lower portion of the first conductive deep well; And And forming a first conductivity type vertical doping layer in contact with a side surface of the first conductivity type deep well so as to surround the first conductivity type deep well and vertically from the surface of the semiconductor substrate to the first conductivity type buried layer. Electrostatic discharge protection element formation method.
KR1020080132820A 2008-12-24 2008-12-24 Apparatus of protecting semiconductor device from the electro static discharge, and method for manufactruing the same KR20100074406A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101304051B1 (en) * 2013-03-05 2013-09-04 단국대학교 산학협력단 Electrostatic discharge protection circuit
KR102444160B1 (en) * 2022-01-27 2022-09-16 큐알티 주식회사 Semiconductor device for electrostatic discharge

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101304051B1 (en) * 2013-03-05 2013-09-04 단국대학교 산학협력단 Electrostatic discharge protection circuit
KR102444160B1 (en) * 2022-01-27 2022-09-16 큐알티 주식회사 Semiconductor device for electrostatic discharge

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