KR102444160B1 - Semiconductor device for electrostatic discharge - Google Patents

Abstract

Provided is a semiconductor device for protecting electrostatic discharge. The semiconductor device for protecting electrostatic discharge can comprise: a substrate; a deep well formed in the substrate; a first base well doped with a dopant of a first conductivity type and a second base well doped with a dopant of a second conductivity type, which are formed in contact with each other in the deep well; a 1-1 diffusion region doped with the dopant of the first conductivity type having a concentration higher than that of the first base well and a 2-3 diffusion region doped with the dopant of the second conductivity type, which are formed in the first base well to be spaced apart from each other; a 2-1 diffusion region with the dopant of the second conductivity type having a concentration higher than that of the second base well and a 1-3 diffusion region doped with the dopant of the first conductivity type, which are formed in the second base well to be spaced apart from each other; and a 1-2 diffusion region formed at a bonding area of the first base well and the second base well and doped with the dopant of the first conductivity type having a concentration higher than that of the first base well; and a transistor using the 1-3 diffusion area as a source and a drain.

Description

Semiconductor device for electrostatic discharge protection

The present application relates to a semiconductor device for electrostatic discharge protection, and more particularly, to a semiconductor device for electrostatic discharge protection having a buried region and a pair of shielding regions.

With the development of semiconductor technology, many electronic products have been miniaturized, and their performance is improving as well as being highly integrated. Therefore, as the degree of integration increases, the area of circuits and devices decreases, the junction depth of semiconductor devices used and the thickness of oxide films such as MOSFETs become thinner. getting serious

In order to prevent such a problem caused by ESD, various technologies have been developed.

For example, in Korean Patent Laid-Open Publication No. 10-2021-0122666, an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node, a first transistor of a first type - the first transistor having a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node, and a first source coupled to the second node, and A clamp circuit is disclosed, comprising a charging circuit coupled between the third node and configured to charge the third node during an ESD event at the second node.

For another example, in Korean Patent No. 10-0698096, a device isolation layer formed in a field region of a first conductivity type semiconductor substrate, and first and second isolation layers formed on the first conductivity type semiconductor substrate isolated by the device isolation layer A high concentration second conductivity type impurity region, a high concentration first conductivity type impurity region formed in the first conductivity type semiconductor substrate on one side of the second high concentration second conductivity type impurity region isolated by the device isolation layer, and the high concentration first conductivity a first conductivity type well formed in the semiconductor substrate under partial regions of the type impurity region, the second high concentration second conductivity type impurity region, and the first high concentration second conductivity type impurity region, one side of the first conductivity type well a second conductivity type well formed in the semiconductor substrate over the remaining partial region of the first high concentration second conductivity type impurity region of , an ESD protection circuit comprising an impurity region of a first conductivity type formed at a boundary portion of a well of a second conductivity type.

One technical problem to be solved by the present application is to provide a semiconductor device for protection against electrostatic discharge with high reliability.

Another technical problem to be solved by the present application is to provide a semiconductor device for electrostatic discharge protection that can effectively protect internal circuits and devices from static electricity in a small area.

Another technical problem to be solved by the present application is to provide a semiconductor device for electrostatic discharge protection having a Silicon Controlled Rectifier (SCR) structure combined with a Bipolar Junction Transistor (BJT) having high tolerance characteristics.

Another technical problem to be solved by the present application is to provide a semiconductor device for electrostatic discharge protection capable of more stably protecting an internal circuit by three-dimensionally and effectively emitting ESD energy.

Another technical problem to be solved by the present application is to provide a semiconductor device for electrostatic discharge protection in which a bipolar transistor having a high holding voltage characteristic is combined.

Another technical problem to be solved by the present application is to provide a semiconductor device for electrostatic discharge protection having a relatively high Second Breakdown Current and a relatively low Second Breakdown Voltage due to a high current driving capability.

The technical problem to be solved by the present application is not limited to the above.

In order to solve the above-described technical problems, the present application provides a semiconductor device for electrostatic discharge protection.

According to an embodiment, the semiconductor device for electrostatic discharge protection includes a substrate, a deep well formed in the substrate, and a first base well formed to be in contact with each other in the deep well and doped with a dopant of a first conductivity type. and a second base well doped with a dopant of a second conductivity type, spaced apart from the first base well and doped with a dopant of the first conductivity type at a higher concentration than the first base well. region and a 2-3rd diffusion region doped with the dopant of the second conductivity type, formed spaced apart from each other in the second base well, and doped with the dopant of the second conductivity type at a higher concentration than the second base well The 2-1 diffusion region, the 1-3 diffusion region doped with the dopant of the first conductivity type, is formed in the junction region of the first base well and the second base well, and has a higher concentration than the first base well and a first-2 diffusion region doped with the dopant of the first conductivity type, and a transistor using the 1-2 diffusion region and the 1-3 diffusion region as sources and drains.

According to an embodiment, the electrostatic discharge protection semiconductor device is formed on a bottom surface of the deep well doped with the dopant of the first conductivity type, and is formed with the dopant of the first conductivity type having a higher concentration than that of the deep well. A doped buried region, a first shielding region formed on one sidewall of the deep well and doped with a dopant of the first conductivity type having a higher concentration than the deep well, and the other sidewall of the deep well, A second shielding region doped with a dopant of the first conductivity type having a higher concentration than that of the deep well may be further included.

According to an embodiment, in the semiconductor device for electrostatic discharge protection, a first to fourth diffusion region formed in the first shielding region and doped with a dopant of the first conductivity type having a higher concentration than that of the first shielding region; A first-fifth diffusion region formed in the second shielding region and doped with a dopant of the first conductivity type having a higher concentration than that of the second shielding region may be further included.

According to an embodiment, the 1-1 diffusion region, the 1-4 diffusion region, the 1-5 diffusion region, and the 2-3 diffusion region are connected to an anode.

According to an embodiment, the 1-3 diffusion region and the 2-1 diffusion region may include being connected to a cathode.

According to an embodiment, a third bipolar transistor including the 1-3 diffusion region, the second base well, the buried region, the first shielding region, and the 1-4 diffusion region is defined, and the and defining a fourth bipolar transistor including a 1-3 diffusion region, the second base well, the second shielding region, and the 1-5 diffusion region.

According to an embodiment, the third bipolar transistor and the fourth bipolar transistor are connected in parallel to increase the holding voltage.

According to an embodiment, a portion of the deep well may be provided between the buried region and the second base well and between the buried region and the first base well.

According to an embodiment, a portion of the deep well may be provided between the first shielding region and the first base well and between the second shielding region and the second base well.

According to an embodiment, the transistor may include a gate insulating layer on the second base well between the 1-2 diffusion region and the 1-3 diffusion region, and a gate electrode on the gate insulating layer.

According to an embodiment of the present application, there is provided a semiconductor device for electrostatic discharge protection having a triple well structure in which a first base well and a second base well are in contact with each other in a deep well formed in a substrate. The electrostatic discharge protection semiconductor device may easily emit ESD energy through a triple well structure.

Specifically, a buried region doped with a dopant of a first conductivity type having a higher concentration than that of the deep well is formed on a bottom surface of the deep well doped with a dopant of a first conductivity type, and on both sidewalls of the deep well The first and second shielding regions doped with the dopant of the first conductivity type having a higher concentration than the deep well may be formed, respectively, so that the PNPN path is diversified and three-dimensionalized to easily release the ESD energy introduced therein. can do. Accordingly, the internal circuit can be more stably protected.

1 is a view for explaining a semiconductor device for electrostatic discharge protection according to a first embodiment of the present application.
2 is a view for explaining a semiconductor device for electrostatic discharge protection according to a second embodiment of the present application.
FIG. 3 is a circuit of the semiconductor device for electrostatic discharge protection shown in FIG. 2 .
4 is a view for explaining a semiconductor device for electrostatic discharge protection according to a modified example of the second embodiment of the present application.
5 is an evaluation of electrical characteristics of a semiconductor device for electrostatic discharge protection according to an embodiment of the present application.
6 is a layout plan view of a semiconductor device for electrostatic discharge protection according to an embodiment of the present application.
7 is a cross-sectional layout view of a semiconductor device for electrostatic discharge protection according to an embodiment of the present application.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical spirit of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

In this specification, when a component is referred to as being on another component, it may be directly formed on the other component or a third component may be interposed therebetween. In addition, in the drawings, the thicknesses of the films and regions are exaggerated for effective description of technical contents.

Also, in various embodiments of the present specification, terms such as first, second, third, etc. are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another. Accordingly, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes a complementary embodiment thereof. In addition, in this specification, 'and/or' is used in the sense of including at least one of the elements listed before and after.

In the specification, the singular expression includes the plural expression unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to designate that a feature, number, step, element, or a combination thereof described in the specification exists, and one or more other features, numbers, steps, or configurations It should not be construed as excluding the possibility of the presence or addition of elements or combinations thereof. In addition, in this specification, "connection" is used in a sense including both indirectly connecting a plurality of components and directly connecting a plurality of components.

In addition, in the following description of the present invention, if it is determined that a detailed description of a related well-known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a view for explaining a semiconductor device for electrostatic discharge protection according to a first embodiment of the present application.

Referring to FIG. 1 , the semiconductor device for electrostatic discharge protection according to the first embodiment of the present application includes a substrate 100 , a first base well 110 formed in the substrate 100 , and a second substrate 100 formed in the substrate 100 . A base well 120 , a 1-1 diffusion region 111 and a 2-3 th diffusion region 123 formed to be spaced apart from each other in the first base well 110 , and spaced apart from each other in the second base well 120 . in the 2-1 th diffusion region 121 , the transistor 122 , and the 1-3 th diffusion region 113 , and in the junction region of the first base well 110 and the second base well 120 . The formed 1-2 diffusion region 112 may be included.

The first base well 110 , the 1-1 diffusion region 111 , the 1-2 diffusion region 112 , and the 1-3 diffusion region 113 are formed with dopants of a first conductivity type. It may be a doped region. In addition, the 1-1 diffusion region 111 , the 1-2 diffusion region 112 , and the 1-3 diffusion region 113 have a higher concentration of the first diffusion region than the first base well 110 . The region may be doped with a dopant of one conductivity type.

The second base well 120 , the 2-1 th diffusion region 121 , and the 2-3 th diffusion region 123 may be regions doped with a dopant of a second conductivity type. In addition, the second-first diffusion region 121 and the second-third diffusion region 123 may be regions doped with a dopant of the second conductivity type having a higher concentration than that of the second base well 120 . have. The substrate 100 may be a semiconductor substrate of the second conductivity type, and the second base well 120 may be a region doped with a dopant of the second conductivity type having a higher concentration than that of the substrate 100 .

According to an embodiment, the dopant of the first conductivity type may be an N-type dopant, and the dopant of the second conductivity type may be a P-type dopant.

Alternatively, according to another embodiment, the dopant of the second conductivity type may be a P-type dopant, and the dopant of the first conductivity type may be an N-type dopant.

When the dopant of the first conductivity type is an N-type dopant and the dopant of the second conductivity type is a P-type dopant, the first-first diffusion region 111 and the second-third diffusion region 123 are an anode. and the 2-1 th diffusion region 121 and the 1-3 th diffusion region 113 may be connected to the cathode.

On the other hand, when the dopant of the first conductivity type is a P-type dopant and the dopant of the second conductivity type is an N-type dopant, the first-first diffusion region 111 and the second-third diffusion region 123 are Silver may be connected to the cathode, and the 2-1 th diffusion region 121 and the 1-3 th diffusion region 113 may be connected to the anode.

The 1-2 diffusion region 112 is formed in a junction region between the first base well 110 and the second base well 120 , and the first base well 110 and the second base well ( 120 ) and may perform a crosslinking function of the first base well 110 and the second base well 120 .

The transistor 122 uses a region of the second base well 120 between the 1-2 diffusion region 112 and the 1-3 diffusion region 113 as an active layer, and the first- The second diffusion region 112 and the 1-3 diffusion region 113 may be used as sources and drains. The transistor 122 may include a gate insulating layer on the second base well 120 between the 1-2 diffusion region 112 and the 1-3 diffusion region 113, and a gate electrode on the gate insulating layer. can

As shown in FIG. 1 , the 2-3 th diffusion region 123 , the first base well 110 , and the second base well 120 may form a first bipolar transistor Q1 . . Also, the 1-2 diffusion region 112 , the second base well 120 , and the 1-3 diffusion region 113 may form a second bipolar transistor Q2 . When the dopant of the first conductivity type is an N-type dopant and the dopant of the second conductivity type is a P-type dopant, the first bipolar transistor Q1 may be a pnp type and the second bipolar transistor Q2 may be an npn type dopant have. On the other hand, when the dopant of the first conductivity type is a P-type dopant and the dopant of the second conductivity type is an N-type dopant, the first bipolar transistor Q1 is an npn type and the second bipolar transistor Q2 is a pnp type. can be

The ESD effect will be described taking the case where the dopant of the first conductivity type is an N-type dopant and the dopant of the second conductivity type is a P-type dopant as an example. As the voltage increases due to excessive ESD energy flowing into the anode terminal, a reverse bias may be applied at the junction of the 1-2 diffusion region 112 serving as a bridge and the second base well 120 . When the reverse bias applied to the 1-2 diffusion region 112 and the second base well 120 rises to the avalanche breakdown voltage, a large number of electron-hole pairs are generated by the avalanche breakdown. It may be formed in the second base well 120 . As such, after a large number of electron-hole pairs are formed, a hole current, which is a majority carrier, may flow from the second base well 120 to the second-first diffusion region 121 .

In this case, a voltage drop may occur due to the second base well resistor 120R in the second base well 120 . The effect of applying a forward bias at the junction of the second base well 120 and the 1-3 diffusion region 113 may occur due to the voltage drop by the second base well resistor 120R, and accordingly , the 1-3 diffusion region 113 and the second base well 120 are turned on to turn on the 1-3 diffusion region 113 , the second base well 120 , and the 1-2 diffusion region The second bipolar transistor Q2 including the region 112 operates. A large number of electron-hole pairs are formed in the region of the first base well 110 by the second bipolar transistor Q2 operating in this way, and in this case, the electron current, which is a majority carrier, is transferred to the first base well 110 . It may flow to the 1-1 diffusion region 111 through the region. In this case, a voltage drop is generated by the first resistor 110R in the first base well 110 , and a forward direction occurs between the junction of the 2-3rd diffusion region 123 and the first base well 110 . A bias may be applied to turn on the 2-3 th diffusion region 123 and the first base well 110 . Accordingly, the first bipolar transistor Q1 including the 2-3rd diffusion region 123 , the first base well 110 , and the second base well 120 operates, and the first bipolar transistor Q1 ) and the second bipolar transistor Q2 form a latch-up path, through which a large amount of ESD current may be discharged.

That is, according to the SCR structure shown in FIG. 1, the ESD current can be discharged through the formation of latch-up paths of the first bipolar transistor Q1 and the second bipolar transistor Q2, which are parasitic PNP and NPN bipolar transistors. can Also, the transistor 122 to which the bias voltage is not applied may have a relatively high holding voltage.

FIG. 2 is a diagram for explaining a semiconductor device for electrostatic discharge protection according to a second embodiment of the present application, and FIG. 3 is a circuit of the semiconductor device for electrostatic discharge protection shown in FIG. 2 .

2 and 3 , the semiconductor device for electrostatic discharge protection according to the second embodiment of the present application includes a substrate 200 , a deep well 240 formed in the substrate 200 , and the deep well ( 240), the first base well 220 and the second base well 230 are formed to be in contact with each other, and the 1-1 diffusion region 221 and the 2-3 diffusion region are spaced apart from each other in the first base well 220. A region 233, a 2-1 diffusion region 231 and a 1-3 diffusion region 223 formed to be spaced apart from each other in the second base well 230, and the first base well 220 and the The 1-2 diffusion region 222 formed in the junction region of the second base well 230, and the 1-2 diffusion region 222 and the 1-3 diffusion region 223 are used as sources and drains. It may include a transistor 232 to

The deep well 240 , the first base well 220 , the 1-1 diffusion region 221 , the 1-2 diffusion region 222 , and the 1-3 diffusion region 223 are The region may be doped with a dopant of the first conductivity type. In addition, the first base well 220 is a region doped with a dopant of the first conductivity type having a higher concentration than that of the deep well 240 , and the 1-1 diffusion region 221 and the 1-2 th diffusion region 221 . The diffusion region 222 and the first to third diffusion regions 223 may be regions doped with a dopant of the first conductivity type having a higher concentration than that of the first base well 220 .

The second base well 230 , the 2-1 th diffusion region 231 , and the 2-3 th diffusion region 233 may be regions doped with a dopant of a second conductivity type. In addition, the second-first diffusion region 231 and the second-third diffusion region 233 may be regions doped with a dopant of the second conductivity type having a higher concentration than that of the second base well 230 . have. The substrate 200 may be a semiconductor substrate of the second conductivity type, and the second base well 230 may be a region doped with a dopant of the second conductivity type having a higher concentration than that of the substrate 200 .

According to an embodiment, the dopant of the first conductivity type may be an N-type dopant, and the dopant of the second conductivity type may be a P-type dopant.

Alternatively, according to another embodiment, the dopant of the second conductivity type may be a P-type dopant, and the dopant of the first conductivity type may be an N-type dopant.

In addition, the semiconductor device for electrostatic discharge protection may further include a buried region 210 , a first shielding region 211 , and a second shielding region 212 .

The buried region 210 is formed on the bottom surface of the deep well 240 , is located in the deep well 240 , and is doped with a dopant of the first conductivity type having a higher concentration than that of the deep well 240 . may be an area. According to an embodiment, as described above, the buried region 210 is provided on the bottom surface of the deep well 240 in the deep well 240 , and the buried region 210 is the first base. It may be spaced apart from the well 220 and the second base well 230 . A portion of the deep well 240 may be provided between the buried region 210 and the first base well 220 and between the buried region 210 and the second base well 230 .

The first shielding region 211 is formed on one sidewall of the deep well 240 adjacent to the first base well 220 , is located in the deep well 240 , and is higher than the deep well 240 . It may be a region doped with a dopant of the first conductivity type in a concentration.

The second shielding region 212 is formed on the other sidewall of the deep well 240 adjacent to the P well 230 , is located in the deep well 240 , and has a higher concentration than that of the deep well 240 . It may be a region doped with the dopant of the first conductivity type.

According to an embodiment, as described above, the first and second shielding regions 211 and 212 are provided on both sidewalls of the deep well 240 in the deep well 240 , The second shielding regions 211 and 212 may be spaced apart from the first base well 220 and the second base well 230 . A portion of the deep well 240 is located between the first and second shielding regions 211 and 212 and the first base well 220 and between the buried region 210 and the second base well 230 . This can be provided.

In addition, the semiconductor device for electrostatic discharge protection includes a first through fourth diffusion region 224 formed in the first shielding region 211 and a first through fifth diffusion region 225 formed in the second shielding region 212 . may further include. The 1-4th diffusion region 224 and the 1-5th diffusion region 225 have a higher concentration of the dopant of the first conductivity type than that of the first shielding region 211 and the second shielding region 212 . It may be a region doped with

When the dopant of the first conductivity type is an N-type dopant and the dopant of the second conductivity type is a P-type dopant, the 1-1 diffusion region 221 , the 1-4 diffusion region 224 , and the The 1-5th diffusion region 225 and the 2-3rd diffusion region 233 may be connected to the anode. In addition, the 1-3 diffusion region 223 and the 2-1 diffusion region 231 may be connected to the cathode.

On the other hand, when the dopant of the first conductivity type is a P-type dopant and the dopant of the second conductivity type is an N-type dopant, the 1-1 diffusion region 221 and the 1-4 diffusion region 224 are , the 1-5th diffusion region 225 , and the 2-3rd diffusion region 233 may be connected to the cathode. Also, the 1-3 diffusion region 223 and the 2-1 diffusion region 231 may be connected to the anode.

The 1-2 diffusion region 222 is provided in the junction region of the first base well 220 and the second base well 230 as described above, and the first base well 220 and the second base well 220 and the second diffusion region 222 are provided. 2 A crosslinking function of the base well 230 may be performed.

The transistor 232 may electrically connect the 1-2 th diffusion region 222 and the 1-3 th diffusion region 223 by a voltage applied to the gate.

The 2-3rd diffusion region 233 , the first base well 220 , and the second base well 230 may form a first bipolar transistor Q1 . In addition, the 1-3 th diffusion region 223 , the second base well 230 , and the 1-2 th diffusion region 222 may form a second bipolar transistor Q2 . The third diffusion region 223, the second base well 230, and the 1-4 diffusion regions 224 may form a third bipolar transistor Q3. In addition, the 1-3 diffusion regions ( 223 ), the second base well 230 , and the 1-5 th diffusion region 225 may form a fourth bipolar transistor Q4 .

When the dopant of the first conductivity type is an N-type dopant and the dopant of the second conductivity type is a P-type dopant, the first bipolar transistor Q1 is a pnp type and the second to fourth bipolar transistors Q2 to Q4 may be an npn type. On the other hand, when the dopant of the first conductivity type is a P-type dopant and the dopant of the second conductivity type is an N-type dopant, the first bipolar transistor Q1 is an npn type and the second to fourth bipolar transistors Q2 to Q2 to Q4) may be a pnp type.

In other words, the 1-1 diffusion region 221 , the 1-4 diffusion region 224 , the 2-3 th diffusion region 223 , and the 1-5 diffusion region 225 are electrically connected to each other. to function as an anode or cathode terminal, and the 1-3 diffusion region 223 and the 2-1 diffusion region 231 are electrically connected to each other to function as a cathode or an anode terminal.

The ESD effect will be described by taking the case in which the dopant of the first conductivity type is an N-type dopant and the dopant of the second conductivity type is a P-type dopant as an example. The first bipolar transistor Q1 as a parasitic PNP bipolar transistor and the second bipolar transistor Q2 as a parasitic NPN bipolar transistor may discharge the ESD current through a positive feedback action.

In this case, the third bipolar transistor including the 1-3 diffusion region 223 , the second base well 230 , the first shielding region 211 , and the 1-4 diffusion region 224 . (Q3) can operate in parallel form. In this case, the ESD current flows through the 1-3 diffusion region 223 , the second base well 230 , the deep well 240 , the buried region 210 , the second shielding region 212 , and the Conducted through the 1-5th diffusion region 225 , the fourth bipolar transistor Q4 may operate in parallel.

Accordingly, the ESD current flows through the 1-1 diffusion region 221 , the P well 230 , the deep well 240 , the buried region 210 , and the first and second shielding regions 211 and 212 . ) is conducted via the 1-4 and 1-5 diffusion regions 224 and 225 within.

That is, compared to the electrostatic discharge protection semiconductor device shown in FIG. 1 , the current driving ability is improved due to the third and fourth bipolar transistors Q3 and Q4 of the NPN type or PNP type connected in parallel, so that the Second Breakdown Current The point can be raised and the Second Breakdown Voltage can be lowered. As such, the holding voltage is maintained high due to the second base well 230 corresponding to the base of the third and fourth bipolar transistors Q3 and Q4 connected in parallel and having a low on-resistance characteristic. can be

In the case of the reverse ESD current, it may be discharged through the parasitic PN diode formed by the second base well 230 , the first base well 220 , and the deep well 240 .

That is, when an ESD current flows into the anode terminal, potentials of the first base well 220 and the deep well 240 may increase. Accordingly, a reverse bias is applied between the 1-2 diffusion region 222 serving as a bridge (crosslinking), the second base well 230 , and the deep well 240 and the second base well 230 . do. When the reverse bias exceeds the threshold voltage, lattice ionization collisions can occur and electron-hole pairs can form.

At this time, the threshold voltage is higher than that between the first base well 220 and the second base well 230 and between the deep well 240 and the second base well 230 , the 1-2 diffusion region ( 222) and the second base well 230 are much lower, and an avalanche breakdown occurs through this region, and at this time, a large amount of electron-holes are generated and holes, which are majority carriers, pass through the second base well 230 . Thus, while moving to the 2-1 th diffusion region 231 , the potential of the second base well 230 is raised by the second resistor 230R to increase the potential of the 1-3 th diffusion region 223 and the second diffusion region 223 . A forward bias is applied to the 2 base well 230 junction to serve as an emitter.

Accordingly, the second bipolar transistor Q2 including the 1-3 diffusion region 223 , the second base well 230 , and the 1-1 diffusion region 221 operates, and the first The third bipolar transistor Q3 and the 1-3 diffusion region 223 including a -3 diffusion region 223, the second base well 230, and the 1-4 diffusion region 224; The fourth bipolar transistor Q4 including the second base well 230 and the 1-5th diffusion region 225 may operate. The second bipolar transistor Q2 discharges the ESD current through a positive feedback operation with the first bipolar transistor Q1, and additionally, in a parallel form through a path composed of the third and fourth bipolar transistors Q3 and Q4. can be discharged. Due to this, the deep well 230 and the third and fourth bipolar transistors Q3 and Q4 in parallel through the buried region 210 have a lower on-resistance characteristic than the SCR shown in FIG. 1, Current driving ability may be excellent.

In addition, in the case of reverse ESD current, in addition to the parasitic PN diode formed by the second base well 230 and the first base well 220 implemented in the SCR structure shown in FIG. 1 , the second base well 230 is additionally , a parasitic PN diode formed of the deep well 240 , the buried region 210 , the first shielding region 211 , and the first to fourth diffusion regions 224 , and the second base well 230 . ), the deep well 240 , the buried region 210 , the second shielding region 212 , and the first-fifth diffusion region 225 may be discharged through the parasitic PN diode.

The semiconductor device for electrostatic discharge protection according to an embodiment of the present application may include a triple well structure of the deep well 240 , the first base well 220 , and the second base well 230 , Due to this, it is possible to have a high holding voltage, low on-resistance, and excellent tolerance characteristics. It is possible to effectively protect an internal circuit by preventing a latch-up phenomenon due to a high holding voltage of the semiconductor device for electrostatic discharge protection in advance. That is, the latch-up state is prevented from being maintained for a long time, so that a large current flows into the internal circuit to prevent damage to the internal circuit, and the on-resistance is lowered through the triple well structure, and the second base well 230 . It may have a high holding voltage characteristic due to a long base corresponding to the depth of .

In addition, due to the low on-resistance of the semiconductor device for electrostatic discharge protection, the second breakdown current is high and the second breakdown voltage is low, so that the ESD tolerance characteristic can be improved, thereby protecting the internal circuit and stably discharging the excessive ESD current .

Therefore, the semiconductor device for electrostatic discharge protection according to an embodiment of the present application can be easily applied to an IC (Integrated Circuit) and VLSI having general I/O (Input/Output).

4 is a view for explaining a semiconductor device for electrostatic discharge protection according to a modified example of the second embodiment of the present application.

Referring to FIG. 4 , in the semiconductor device for electrostatic discharge protection according to a modified example of the second embodiment of the present application described with reference to FIGS. 2 and 3 , the buried region 210 , the first shielding region 211 , and the second shielding region 212 may be omitted.

In this case, the third bipolar transistor Q3 includes the 1-3 diffusion region 223 , the second base well 230 , the deep well 240 , and the 1-4 diffusion region 224 . may include, wherein the fourth bipolar transistor Q4 includes the 1-3 diffusion region 223 , the second base well 230 , the deep well 24 , and the 1-5 diffusion region (225).

4 is an evaluation of electrical characteristics of a semiconductor device for electrostatic discharge protection according to an embodiment of the present application.

Referring to FIG. 5 , the limitation of the ESD protection circuit was quantitatively analyzed while applying a pulse voltage by using a transmission line pulse (TLP) without directly applying the ESD voltage.

In FIG. 5 , a red mark (New Tech) corresponds to the electrostatic discharge protection semiconductor device described with reference to FIG. 2 , and a black mark in FIG. 4 corresponds to the electrostatic discharge protection semiconductor device described with reference to FIG. 1 .

It can be seen that the semiconductor device for electrostatic discharge protection according to the embodiment of the present application described with reference to FIGS. 1 and 2 protects an internal circuit (Internal circuit protection region), and in particular, the static electricity described with reference to FIG. 2 . In the case of a semiconductor device for discharge protection, compared to that described with reference to FIG. 1, the internal circuit is more stably protected, and the holding voltage is higher than the operation voltage region, which stably protects the internal circuit from excessive ESD voltage. know that it can be protected.

6 is a layout plan view of a semiconductor device for electrostatic discharge protection according to an embodiment of the present application, and FIG. 7 is a cross-sectional layout view of a semiconductor device for electrostatic discharge protection according to an embodiment of the present application.

Referring to FIGS. 6 and 7 , it is a plan view and a cross-sectional view of an actual layout of the semiconductor device for electrostatic discharge protection described with reference to FIG. 2 , showing an active layer and an implant layer.

6 and 7, green and light pink indicate regions doped with N and P, yellow indicates gate lines, and dotted lines indicate three types of well implant layers (deep well). (DNWELL), N well (NWELL), P well (PWELL)) are indicated.

The cathodes shaded in the cross-section A-A' in FIG. 7 are not individual, but are electrically connected, as shown two-dimensionally in a plan view. In addition, as described above with reference to FIG. 2 , an excessive ESD current can be easily discharged by a three-dimensionally formed current path by the third bipolar transistor and the fourth bipolar transistor.

In addition, in a plan view, the 1-1 diffusion region, the 1-2 diffusion region, the 1-3 diffusion region, the 2-1 diffusion region, the 2-3 diffusion region, and the first shielding It can be seen that the region and the second shielding region are spaced apart from each other and extend side by side in the first direction, and the width of the first shielding region and the second shielding region in the second direction perpendicular to the first direction may be wider than the widths of the 1-1 diffusion region, the 1-2 diffusion region, the 1-3 diffusion region, the 2-1 diffusion region, and the 2-3 diffusion region. .

As mentioned above, although the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to specific embodiments and should be construed according to the appended claims. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present invention.

100: substrate
110: first base well
120: second base well
111: 1-1 diffusion region
112: 1-2 diffusion region
113: 1-3 diffusion region
121: 2-1 diffusion region
122: transistor
123: 2-3 diffusion region
200: substrate
210: buried area
211: first shielding area
212: second shielding area
220: first base well
221: 1-1 diffusion region
222: 1-2 diffusion region
223: 1-3 diffusion region
230: second base well
231: 2-1 diffusion region
232: transistor
233: 2-3 diffusion region
240: deep well

Claims (13)

Board;
a deep well formed in the substrate;
a first base well doped with a dopant of a first conductivity type and a second base well doped with a dopant of a second conductivity type formed in contact with each other in the deep well;
A first diffusion region formed to be spaced apart in the first base well and doped with a dopant of the first conductivity type having a higher concentration than the first base well, and the second conductivity having a higher concentration than the second base well a second-third diffusion region doped with a type dopant;
a 2-1 diffusion region formed to be spaced apart from each other in the second base well and doped with a dopant of the second conductivity type having a higher concentration than the second base well, and a second diffusion region having a higher concentration than the first base well 1-3 diffusion regions doped with a first conductivity type dopant;
a 1-2 diffusion region formed in a junction region between the first base well and the second base well and doped with a dopant of the first conductivity type having a higher concentration than that of the first base well;
a transistor using the 1-2 diffusion region and the 1-3 diffusion region as sources and drains;
a buried region formed on a bottom surface of the deep well doped with the dopant of the first conductivity type and doped with the dopant of the first conductivity type having a higher concentration than that of the deep well;
a first shielding region formed on one sidewall of the deep well and doped with a dopant of the first conductivity type having a higher concentration than that of the deep well; and
and a second shielding region formed on the other sidewall of the deep well and doped with a dopant of the first conductivity type having a higher concentration than that of the deep well.
delete The method of claim 1,
a first to fourth diffusion region formed in the first shielding region and doped with a dopant of the first conductivity type having a higher concentration than that of the first shielding region; and
and 1-5 diffusion regions formed in the second shielding region and doped with a dopant of the first conductivity type having a higher concentration than that of the second shielding region.
4. The method of claim 3,
and wherein the 1-1 diffusion region, the 1-4 diffusion region, the 1-5 diffusion region, and the 2-3 diffusion region are connected to an anode.
4. The method of claim 3,
and wherein the 1-3 diffusion region and the 2-1 diffusion region are connected to a cathode.
4. The method of claim 3,
a third bipolar transistor including the 1-3 diffusion region, the second base well, the buried region, the first shielding region, and the 1-4 diffusion region is defined;
and defining a fourth bipolar transistor including the 1-3 diffusion region, the second base well, the second shielding region, and the 1-5 diffusion region.
7. The method of claim 6,
and the third bipolar transistor and the fourth bipolar transistor are connected in parallel to increase a holding voltage.
The method of claim 1,
and a portion of the deep well is provided between the buried region and the second base well and between the buried region and the first base well.
The method of claim 1,
and a portion of the deep well is provided between the first shielding region and the first base well and between the second shielding region and the second base well.
The method of claim 1,
The transistor is
a gate insulating layer on the second base well between the 1-2 diffusion region and the 1-3 diffusion region; and
A semiconductor device for electrostatic discharge protection including a gate electrode on the gate insulating layer.
Board;
a deep well formed in the substrate;
a first base well doped with a dopant of a first conductivity type and a second base well doped with a dopant of a second conductivity type formed in contact with each other in the deep well;
A first diffusion region formed to be spaced apart in the first base well and doped with a dopant of the first conductivity type having a higher concentration than the first base well, and the second conductivity having a higher concentration than the second base well a second-third diffusion region doped with a type dopant;
a 2-1 diffusion region formed to be spaced apart from each other in the second base well and doped with a dopant of the second conductivity type having a higher concentration than the second base well, and a second diffusion region having a higher concentration than the first base well 1-3 diffusion regions doped with a first conductivity type dopant;
a 1-2 diffusion region formed in a junction region between the first base well and the second base well and doped with a dopant of the first conductivity type having a higher concentration than that of the first base well;
a transistor using the 1-2 diffusion region and the 1-3 diffusion region as sources and drains; and
and a first shielding region formed on one sidewall of the deep well and doped with a dopant of the first conductivity type having a higher concentration than that of the deep well.
Board;
a deep well formed in the substrate;
a first base well doped with a dopant of a first conductivity type and a second base well doped with a dopant of a second conductivity type formed in contact with each other in the deep well;
A first diffusion region formed to be spaced apart in the first base well and doped with a dopant of the first conductivity type having a higher concentration than the first base well, and the second conductivity having a higher concentration than the second base well a second-third diffusion region doped with a type dopant;
a 2-1 diffusion region formed to be spaced apart from each other in the second base well and doped with a dopant of the second conductivity type having a higher concentration than the second base well, and a second diffusion region having a higher concentration than the first base well 1-3 diffusion regions doped with a first conductivity type dopant;
a 1-2 diffusion region formed in a junction region between the first base well and the second base well and doped with a dopant of the first conductivity type having a higher concentration than that of the first base well;
a transistor using the 1-2 diffusion region and the 1-3 diffusion region as sources and drains; and
and a first shielding region formed on one sidewall of the deep well and doped with a dopant of the first conductivity type having a higher concentration than that of the deep well.
13. The method of claim 12,
and a second shielding region formed on the other sidewall of the deep well and doped with a dopant of the first conductivity type having a higher concentration than that of the deep well.

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