KR20100062597A - A printed circuit board comprising a burried-pattern and a method of manufacturing the same - Google Patents

Abstract

PURPOSE: A printed circuit board and a manufacturing method thereof are provided to remove the fault of a PCB due to plating deviation. CONSTITUTION: A via(310) electrically conducts a circuit pattern(710) formed on an insulator(100) and the up/down surface of the insulator. The via is composed of an electroless plated layer formed in the inner wall of a via hole and an electrolytic plated layer. A plugging ink(500) charges the inside of the via hole.

Description

A printed circuit board having a buried pattern and a manufacturing method thereof {A PRINTED CIRCUIT BOARD COMPRISING A BURRIED-PATTERN AND A METHOD OF MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board having a buried pattern and a method of manufacturing the same, and more particularly, because a via pattern is formed first in a via hole and subsequently a circuit pattern is sequentially formed. The present invention relates to a structure and a manufacturing method of a printed circuit board capable of forming a pattern.

With the development of the electronic industry, the demand for high functionalization and miniaturization of electronic components is increasing rapidly. In order to cope with such a trend, printed circuit boards are also required to have higher density of circuit patterns, and various fine circuit pattern implementation methods have been devised, presented, and applied.

The present invention is to describe a more stable structure and manufacturing method for implementing a high density of the circuit pattern by embedding the circuit pattern in the insulating layer of the fine circuit pattern (implementation method).

1 is a view showing a method for manufacturing a printed circuit board according to the prior art.

First, as shown in FIG. 1A, when a double-sided copper clad laminate in which copper foils 3 are laminated on both sides of the insulating layer 1 is provided, as shown in FIG. 1B, the via hole 5 may be formed using a CNC drill or the like. Processing. Thereafter, as shown in FIG. 1C, the plating layer 7 is formed on the inner wall of the via hole 5, and as shown in FIG. 1D, the plugging ink 9 is filled in the via hole 5, and then, in FIG. 1E. As shown, the protruding plugging ink 9 is removed. Thereafter, an etching resist (not shown) may be laminated and patterned, and then the exposed plating layer 7 and copper foil 3 may be removed to manufacture a double-sided printed circuit board as shown in FIG. 1F.

Thereafter, as illustrated in FIG. 1G, an additional insulating layer 11 is stacked on and under the double-sided printed circuit board to form an additional build-up layer, and as shown in FIG. 1H, exposing the lower circuit layer. The blind via hole 13 is machined. Next, as shown in FIG. 1I, an electroless plating layer 15 is formed on the surface of the additional insulating layer 11 and the inner wall of the blind via hole 13, and as shown in FIG. 1J, the plating resist layer 17 is formed. Are stacked and patterned. Thereafter, as shown in FIG. 1K, the circuit pattern 21 and the vias 19 are formed in the openings formed in the plating resist layer 17 by performing electroplating using the electroless plating layer 15 as a lead wire, and FIG. 1L. As shown in FIG. 1, a four-layer printed circuit board may be manufactured by removing the remaining plating resist layer 17 and removing the electroless plating layer 15 exposed through flash etching, as shown in FIG. 1M. have.

When forming the circuit layer of the initial double-sided printed circuit board in the manufacturing process of the four-layer printed circuit board described above, a process of forming a circuit pattern by a subtractive method has been described, and the additional build-up layer is a conventional SAP (Semi). The process of forming a circuit layer in an additive process has been described.

However, as printed circuit boards such as semiconductor substrates have become fine circuits, it is no longer possible to form fine circuits by the subtractive method. The SAP method developed as a microcircuit forming process is also nearing its limit, and the trench method is emerging as an alternative process for forming a finer circuit.

The present invention has been made to solve the above problems of the prior art, and proposes a method and a structure of a printed circuit board in which a circuit pattern is embedded in an insulating layer to realize a fine circuit.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a printed circuit board having a buried pattern, the method comprising: (A) providing an insulating material, and forming an intaglio pattern for forming a via hole and a circuit pattern in the insulating material; (B) forming a via on the inner wall of the via hole to electrically connect the upper and lower surfaces of the insulating material, and filling plugging ink into the via hole; And (C) filling the intaglio pattern with a conductive metal to form a circuit pattern, wherein the steps are performed sequentially.

As a preferred feature of the invention, the step (A) comprises the steps of: (i) providing an insulating material and forming a via hole penetrating the insulating material; And (ii) forming an intaglio pattern for forming a circuit pattern on an outer layer of the insulating material by using a laser.

In another preferred embodiment of the present invention, the step (B) may include: (i) forming a first metal layer by performing electroless plating and electroplating on the inner wall of the via hole and the outer layer of the insulating material; (Ii) filling a plugging ink into the via hole; And (iii) removing the first metal layer formed on the insulating material so that the outer layer of the insulating material is exposed.

In another preferred embodiment of the present invention, the step (C) may include: (i) forming a second metal layer by performing electroless plating and electrolytic plating on an outer layer of the insulating material including the intaglio pattern; And (ii) removing a portion of the second metal layer in a thickness direction so that an outer layer of the insulating material is exposed.

In another preferred aspect of the present invention, after the step (ii), the method further includes the step of removing the plugging ink protruding out of the insulating material.

As another preferable feature of the present invention, the step (iii) is performed by a physical polishing process, a chemical etching process, or a combination of a physical polishing process and a chemical etching process.

As another preferable feature of the present invention, the step (ii) is performed by a physical polishing process, a chemical etching process, or a combination of a physical polishing process and a chemical etching process.

In a printed circuit board having a buried pattern according to the present invention, a printed circuit board including a circuit pattern formed on an insulating material and vias electrically connecting upper and lower surfaces of the insulating material, wherein the vias are formed on an inner wall of the via hole penetrating the insulating material. It is formed of an electroless plating layer and an electrolytic plating layer, and further comprises a plugging ink filling the inside of the via hole, the height of the exposed surface of the circuit pattern based on the thickness center line of the insulating material is the same as the surface height of the insulating material or Or low.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

Since the printed circuit board having the buried pattern according to the present invention has a form in which the circuit pattern and the via are embedded in the insulating layer, there is no undercut of the circuit pattern and the circuit pattern has a fine pitch.

According to the method of manufacturing a printed circuit board having a buried pattern according to the present invention, a defect is generated in a printed circuit board caused by plating deviation by first forming a via in an insulating material having a via hole and an intaglio pattern, and then sequentially forming a circuit pattern. You can solve the problem.

Hereinafter, a preferred embodiment of a printed circuit board having a buried pattern and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. Throughout the accompanying drawings, the same or corresponding components are referred to by the same reference numerals, and redundant descriptions are omitted. In this specification, terms such as top and bottom are used to distinguish one component from another component, and a component is not limited by the terms.

2 to 11 are diagrams showing a manufacturing method of a printed circuit board having a buried pattern according to a preferred embodiment of the present invention in the order of process.

First, as shown in FIG. 2, an insulating material 100 for manufacturing a printed circuit board is provided. The insulating material 100 is made of an insulating material generally used for manufacturing a printed circuit board, and may be, for example, a prepreg made of an epoxy resin. Alternatively, the insulating material 100 of the present embodiment may be one in which an insulating layer is additionally formed on the core from which the copper foil of the double-sided copper clad laminate is removed.

Next, the via hole 110 and the intaglio pattern 130 for forming a circuit pattern are formed in the insulating material 100.

As shown in FIG. 3, a via hole 110 penetrating the insulating material 100 is formed. As a method of processing the via hole 110 penetrating the insulating material 100, a method using a laser drill such as a YAG laser, a CO2 laser, or a mechanical drill such as a CNC drill may be used. In the present embodiment, a via hole 110 penetrating the insulating material 100 is formed by using a CNC drill.

Subsequently, as shown in FIG. 4, an intaglio pattern 130 for forming a circuit pattern 710 (see FIG. 11) is formed on an outer layer of the insulating material 100. A number of methods for forming the intaglio pattern 130 on which the circuit pattern 710 to be formed later is buried in the insulating material 100 are known, and there are, for example, a method using a laser drill and an imprinting method. In the present exemplary embodiment, the intaglio pattern 130 on which the circuit pattern 710 is to be formed in a later process is formed on the outer layer of the insulating material 100 using a laser drill. At this time, although not essential, it is preferable to form the intaglio pattern 113 in contact with the via hole 110 in order to form a circuit pattern in contact with the via to be formed later.

Next, a via 310 is formed on the inner wall of the via hole 110 to electrically connect the upper and lower surfaces of the insulating material, and the plugging ink 500 is filled in the via hole 110.

As shown in FIG. 5, the first metal layer 300 is formed on the inner wall of the via hole 110 by performing electroless plating and electroplating on the inner wall of the via hole 110 and the outer layer of the insulating material 100. Electroless plating is a pretreatment process for performing electroplating to form an electroless plating layer so that electroplating may be performed on the inner wall of the via hole 110. Thereafter, the first metal layer 300 may be formed on the inner wall of the via hole 110 by electroplating the electroless plating layer with the lead wire.

Thereafter, as shown in FIG. 6, the plugging ink 500 is filled in the via hole 110. Plugging ink 500 (Plugging ink) is generally used to use a plugging ink of insulating ink material, it is also possible to use a conductive paste containing a conductive metal powder.

Thereafter, as shown in FIG. 7, the plugging ink 500 protruding out of the insulating material 100 is removed. This process is an optional process performed only when the plugging ink 500 protrudes out of the insulating material 100, and the plugging ink protruding out of the insulating material 100 by a polishing process using an abrasive brush or a buff ( 500) is removed and planarized.

Thereafter, as shown in FIG. 8, the first metal layer 300 formed on the insulating material 100 is removed to expose the outer layer of the insulating material 100. When the plugging ink 500 protruding by the physical polishing process using the polishing brush or the buff in the above-described process, the plugging ink 500 and the first metal layer 300 may be removed together.

Alternatively, after the physical polishing process of the plugging ink 500, a chemical etching process may be performed to remove the first metal layer 300 formed on the insulating material 100. The physical polishing process may include removing the first metal layer 300. A portion of the thickness may be removed, and the remaining first metal layer 300 may be removed by a chemical etching process. In this case, the first metal layer 300 may remain in the intaglio pattern 130 formed on the insulating material 100, which does not cause any obstacle to the practice of the present invention.

By the above-described process, the via 310 may be formed on the inner wall of the via hole 110 formed in the insulating material 100 to electrically conduct the upper and lower surfaces of the insulating material 100.

Next, the conductive pattern is filled in the intaglio pattern 130 to form the circuit pattern 710.

As shown in FIG. 9, an electroless plating and an electrolytic plating are performed on the outer layer of the insulating material 100 including the intaglio pattern 130 to form a second metal layer 700 made of a conductive metal. In this case, the inside of the intaglio pattern 130 formed on the outer layer of the insulating material 100 is filled with the second metal layer 700, and a second metal layer 700 having a uniform thickness is formed on the insulating material 100.

As such, the reason for forming the second metal layer 700 again after removing the first metal layer 300 is as follows.

The first metal layer 300 is formed by performing an electroless and electroplating process in a state where the via hole 110 and the intaglio pattern 130 are simultaneously present in the insulating material 100, wherein the via hole 110 is the intaglio pattern 130. Since the inner space is larger and deeper than), the first metal layer 300 formed on the first insulating material 100 has a variation in plating thickness. In order to fill the intaglio pattern 130 formed in the insulating material 100 to form a buried pattern, it is essential that the thickness of the metal layer formed on the insulating material 100 be constant, and the first metal layer 300 meets this requirement. Does not meet Therefore, the process of forming the second metal layer 700 having a uniform thickness after removing the first metal layer 300 having the thickness variation is performed again. Since the via hole 110 portion of the insulating material 100 is already filled with the plugging ink 500 in the plating process of forming the second metal layer 700, that is, the outer layer of the insulating material 100 to a desired extent to form the plating layer. Since it is in a planarization state, it is possible to form the second metal layer 700 having a uniform thickness.

Next, a portion of the second electroless plating layer and the second electroless plating layer are removed in a thickness direction so that the outer layer of the insulating material 100 is exposed. Similar to the step of removing the first metal layer 300, the step of removing the second metal layer 700 may also be performed by a physical polishing method, a chemical etching method, or a combination thereof. In this embodiment, a process of removing a part of the second metal layer 700 in the thickness direction by way of a combination of a physical polishing method and a chemical etching method will be described.

First, as shown in FIG. 10, a part of the second metal layer 700 is removed in the thickness direction by a physical polishing process using a polishing brush or a buff.

Thereafter, as illustrated in FIG. 11, a chemical etching process is performed to expose an outer layer of the insulating material 100, and a circuit pattern 710 is insulated from each other on the insulating material 100 by this process.

In this embodiment, for the sake of clarity, the process of forming the circuit pattern 710 on only one surface of the insulating material 100 has been described as an example for convenience. However, according to the process procedure of the present embodiment, the circuit pattern ( It will be appreciated that it is possible to form 710.

According to the method of manufacturing a printed circuit board having a buried pattern as described above, the via 310 is first formed in the insulating material 100 having the via hole 110 and the intaglio pattern 130, and then the circuit pattern 710 is formed. By forming sequentially, the problem of the defect of the printed circuit board caused by the plating deviation can be solved.

Hereinafter, a structure of a printed circuit board having a buried pattern according to a preferred embodiment of the present invention will be described with reference to FIG. 11.

As shown in FIG. 11, the present embodiment relates to a printed circuit board including a circuit pattern 710 formed on the insulating material 100 and a via 310 electrically conducting the upper and lower surfaces of the insulating material 100. The printed circuit board having the buried pattern according to the present exemplary embodiment includes a via 310 formed of an electroless plating layer and an electrolytic plating layer formed on the inner wall of the via hole penetrating the insulating material 100, and a plugging ink 500 filling the via hole. Configuration.

In this case, the height of the exposed surface of the circuit pattern 710 based on the thickness center line of the insulating material 100 is the same as or lower than the surface height of the insulating material 100.

The printed circuit board having the buried pattern according to the present embodiment as described above has a circuit pattern with a fine pitch without occurrence of undercut of the circuit pattern since the circuit pattern and the via are embedded into the insulating layer.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Therefore, such modifications or variations will have to belong to the claims of the present invention.

1 is a view showing a method for manufacturing a printed circuit board according to the prior art.

2 to 11 are diagrams showing a manufacturing method of a printed circuit board having a buried pattern according to a preferred embodiment of the present invention in the order of process.

<Description of Major Symbols in Drawing>

100 Insulation Material 110 Via Hole

130 Engraved Pattern 300 First Metal Layer

500 Plugging Ink 700 Second Metal Layer

710 circuit pattern

Claims (8)

(A) providing an insulating material, and forming an intaglio pattern for forming a via hole and a circuit pattern in the insulating material; (B) forming a via on the inner wall of the via hole to electrically connect the upper and lower surfaces of the insulating material, and filling plugging ink into the via hole; And (C) filling the intaglio pattern with a conductive metal to form a circuit pattern; To include, wherein the step is a method of manufacturing a printed circuit board having a buried pattern, characterized in that proceeding sequentially. The method of claim 1, Step (A) is (Iii) providing an insulating material and forming a via hole through the insulating material; And (Ii) forming an intaglio pattern for forming a circuit pattern on an outer layer of the insulating material by using a laser; Method of manufacturing a printed circuit board having a buried pattern comprising a. The method of claim 1, Step (B) is, (Iv) electroless plating and electroplating the inner wall of the via hole and the outer layer of the insulating material to form a first metal layer; (Ii) filling a plugging ink into the via hole; And (Iii) removing the first metal layer formed on the insulating material so that the outer layer of the insulating material is exposed; Method of manufacturing a printed circuit board having a buried pattern comprising a. The method of claim 1, Step (C) is (Iii) forming a second metal layer by performing electroless plating and electrolytic plating on the outer layer of the insulating material including the intaglio pattern; And (Ii) removing a portion of the second metal layer in a thickness direction so that an outer layer of the insulating material is exposed; Method of manufacturing a printed circuit board having a buried pattern comprising a. The method of claim 3, After step (ii) above, Removing the plugging ink protruding to the outside of the insulating material manufacturing method of a printed circuit board having a buried pattern characterized in that it further comprises. The method of claim 3, The step (iii) is performed by a physical polishing process, a chemical etching process, or a combination of a physical polishing process and a chemical etching process. The method of claim 4, wherein The step (ii) is a manufacturing method of a printed circuit board having a buried pattern, characterized in that performed by a physical polishing process, a chemical etching process, or a combination of a physical polishing process and a chemical etching process. A printed circuit board comprising a circuit pattern formed on an insulating material and vias electrically conducting upper and lower surfaces of the insulating material, The via is formed of an electroless plating layer and an electrolytic plating layer formed on an inner wall of a via hole penetrating the insulating material, and further includes a plugging ink filling the inside of the via hole, and exposing the circuit pattern based on a thickness center line of the insulating material. Printed circuit board having a buried pattern, characterized in that the height of the surface is equal to or lower than the surface height of the insulating material.

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