KR20100057275A - Interconnect structure - Google Patents

Abstract

PURPOSE: The interconnect structure and product offer the electric component including the frame supporting the web and the logic device fixed to the web. CONSTITUTION: The insulation web has the first surface and the second back side. The logic device is fixed to the second back side of the insulation web. The frame assembly supports the insulation web. The frame assembly comprises the frame base(12) and the first conductor layer(18). The logic device comprises the device connector. The frame base is expanded through the first surface, and the second back side and frame base.

Description

Interconnect Structures and Products {INTERCONNECT STRUCTURE}

The present invention includes embodiments of interconnect structures. The interconnect structure may be related to electricity or may be related to light.

In the current embedded chip process, referred to as embedded chip build-up (ECBU) or chips first build-up (CFBU) technology, bare chips do not require solder joints or wirebonds. Packaged in a high density interconnect structure using a perimeter or an array of peripheral I / O pads or I / O pads distributed across the surface. An ECBU or CFBU process can form a chip carrier that interconnects a complex semiconductor chip to a larger contact pad compatible with board level assemblies such as a printed circuit board.

BACKGROUND Semiconductor devices are increasingly manufactured with increasing I / O counts (4000-8000 or more). As CFBU technology is applied to their more complex semiconductor devices, the correspondingly increased routing requirements of the chips allow for the use of additional routing layers and / or thinner conductor lines. Make the distance between the lines narrower. Adding more layers with the same feature size and having more lines routed to smaller features can all increase yield loss. Since CFBU technology does not form interconnect layers or lines, distances and layer-to-layer vias associated with such interconnect layers, the increase in loss rate is at risk of being discarded until after the chip is placed in the carrier. Increase the number of expensive chips. The decoupling capacitor also needs to be adjacent to a moderately effective high speed switching processor. For CFBU carriers with thin profiles, eg, profiles less than 1 millimeter (mm) to industrial surface flip chip build-up carriers with profiles of 2 mm or more, there may be insufficient margin to mount the necessary individual decoupling capacitors in the carrier. . In addition, the pins of the pin grid array have a weaker mechanical strength than the solder balls of the ball grid array.

In one embodiment, the present invention provides an electronic device comprising a frame capable of supporting the web and a logic device secured to the web. The frame supports optical or electronic circuitry, and the supported optical or electronic circuitry is coupled with the logic device.

In one aspect, the electronic circuitry includes passive electronic components such as capacitors, inductors or resistors. In another aspect, the optical circuit includes beam splitters, mirrors, grates, and the like. The frame can be combined with other elements to form an electronic package.

In one embodiment, the present invention provides an insulating web having a first surface and a second surface, a logic device secured to a second surface of the insulating web, a frame base having a first surface and a second surface, the first of the frame base. A first frame insulating layer disposed between the first surface and the second surface of the insulating web, an aperture extending through the frame base and the first frame insulating layer, wherein at least a portion of the logic device is disposed therein, and the frame base A frame panel assembly comprising a first frame connector disposed between a first electrically conductive layer located on a first surface and a second electrically conductive layer located on a surface of the first frame insulating layer, and an I / O on the surface of the logic device; A device connector disposed between the contact and a third electrical conductor located on the surface of the insulating web, a third electrical conductor and a first frame section located on the surface of the insulating web. To provide an interconnect structure including the insulating layer connector which is disposed between the second conductive layer located on the surface of the layer.

In another embodiment, the present invention provides an insulating web having a first surface and a second surface, a logic device secured to a second surface of the insulating web, a frame base having a first surface and a second surface, the first of the frame base. A first frame insulating layer disposed between the first surface and the second surface of the insulating web, an aperture extending through the frame base and the first frame insulating layer, at least a portion of the logic device disposed therein, and the frame base and the first A frame panel assembly comprising a first frame connector disposed between the one frame insulating layer, a device connector disposed between the logic device and the insulating web, and an insulating layer connector disposed between the insulating web and the first frame insulating layer Providing a product.

The present invention includes embodiments of interconnect structures. The interconnect structure may have an integrated frame assembly. The interconnect structure may be related to electricity or may be related to light.

As used herein, a passive element or passive element is an element that consumes (but does not produce) electrical energy or an element that does not obtain power gain. Non-passive devices are called active devices. Circuits consisting entirely of passive elements are also considered passive (also having the same characteristics as passive elements). Under this definition, passive elements include capacitors, inductors, resistors, transformers, voltage sources, and current sources. Active devices may include devices with one or more transistors, relays, glow tubes, voltage regulator tubes, tunnel diodes, and similar devices. The term "insulative" refers to being electrically insulating, and the term "conductive" refers to being electrically conductive unless the context or language indicates otherwise. An "interconnection layer" is an insulating layer having at least one via and at least one circuit or connector thereon.

1 and 2, an interconnection intermediate structure 2 is shown. The intermediate structure 2 (FIG. 1) is modified to produce a frame 10 (FIG. 2) according to an embodiment of the present invention. The frame includes a frame base 12 having a first surface 14 and a second surface 16. The first conductive layer 18 is fixed to the first surface of the frame base. The frame adhesive layer 20 secures the first frame insulation layer 22 to the frame base and overlays at least a portion of the first conductive layer. The frame adhesive layer is not shown in some figures for clarity. The first frame insulating layer has a first outward-facing surface 24 and a second inward-facing surface 26. The second electrically conductive layer 28 is located on the first surface of the first frame insulating layer.

Referring to FIG. 2, the via 30 is formed to extend through the frame adhesive layer and the first frame insulating layer. Vias are filled with an electrically conductive material to form first frame connector 32. The first frame connector allows connection to a first conductive layer located on the first surface of the frame base through the frame adhesive layer and the first frame insulating layer. Conductive traces or contacts 34 are formed on the outward surface of the first frame insulating layer. The frame base has an interior surface 35 that defines a frame feature 36, which extends to penetrate the frame base.

FIG. 3 is a perspective cross-sectional view of the frame assembly 37 including the frame (not actual scale) of FIG. 1 and the insulating web 38 secured to the frame by the insulating adhesive layer 39. The insulating web extends through one open end of the frame aperture and closes the end, thereby forming a nest or recess. Logic device 40 is shown mounted on an insulating web in a frame aperture spaced from an inward surface of the frame base. The logic device has a first surface 42 and a second surface 44. The first surface of the logic device includes I / O contacts 46. The I / O contacts of the logic device may be corresponding bond pads (not shown) on the inward surface of the insulating web, or the like, or if they extend above the inward surface of the insulating web, the corresponding bond pads on the inward surface of the insulating web adhesive layer. (Not shown). The trench or gap 48 is defined by the surface of the logic device and the inward surface of the frame base. Reference numeral 49 denotes the outward surface of the insulating web.

Other frames may be monolithic, but the illustrated frames include a frame base, a frame insulation layer, and a frame adhesive layer that bonds them together. Metallization layers, circuits and passives may be included and / or embedded in any of the foregoing, depending on the embodiment.

The frame base may be formed of a material selected from metal, ceramic or polymer materials. Suitable polymeric materials may include polyimides, ROMP-capable monomers or epoxies. The polymeric material may include a reinforcing filler. Such fillers may include fibers or small inorganic particles. Suitable fibers may be glass fibers or carbon fibers. Suitable particulates can include silica, silicon carbide, boron nitride, aluminum oxide, or aluminum nitride. When formed of a polymeric material, the frame base may be a molded or cast structure. Suitable molding techniques may include resin injection molding, bulk molding, and the like.

The frame base comprises a material selected for a particular design based on the desired coefficient of thermal expansion, stiffness or other desired mechanical, electrical and thermal properties. If the frame base is electrically conductive, a dielectric or electrically insulating overcoating may be applied to the surface of the frame base. Suitable electrically conductive frame materials may be metal. Suitable metals for use as the frame base can be selected from aluminum, nickel, titanium, iron or tin. Alternatively, the metal may be an alloy or a metal compound. Suitable alloys and compounds may include, for example, stainless steel or Cu: Invar: Cu. Suitable electrically insulating overcoating materials may be ceramic materials, polymeric materials or enamels. The overcoating material may be selected according to the coefficient of thermal expansion matching, the dielectric properties of the overcoating, the stickiness and other properties of the materials used in relation to each other. The electrically insulating overcoating material may insulate the conductive trace and the electronic device supported on the frame base.

The frame base material and the insulating layer material should be chosen so as not to bend the frame base during use. The frame base material should be chosen such that the coefficient of thermal expansion (CTE) closely matches the CTE of one or more devices that will assemble the structure. The semiconductor carrier may be fixed to the organic printed circuit board. Such printed circuit boards may have a CTE in the range of about 15 ppm / ° C. to about 20 ppm / ° C. If the insulating layer has a higher CTE than the printed circuit board CTD, the frame base may bend and concave. If the CTE of the insulating layer is lower, the frame base can be bent and convex. Selecting a frame base with a relatively increased Young's Modulus can reduce the chance of bending, even if the stress and strain on the frame base is relatively high. In addition, selecting the insulating layer to lower the shrinkage of the insulating layer during modulus and / or curing of the Young's modulus can reduce the chance of warpage and the stress or strain on the frame base.

The frame base has an inward surface that defines an opening or an aperture, so that the frame also has such an inward surface. Milling, mechanical stamping, laser cutting, water jetting, wet etching, laser ablation, die punching or dry etching ( dry etching) may form an aperture in the frame base. The logic device may be supported on an insulating web in the aperture (more details are provided later). The apertures may be formed before or after the addition of the frame insulation layer, the frame adhesion layer, the first conductive layer and other elements.

The first electrically conductive layer may be a metallization surface disposed over at least a portion of the first surface of the frame base and optionally on at least a selected portion of the second surface of the frame base. The first electrically conductive layer is a continuous metal plane that can function as a reference plane. The reference plane may be a ground plane or a power supply plane. Alternatively, the first electrically conductive layer can be a partial metal face. Metallization on the first surface of the frame insulation layer may be used as the signal routing layer, and metallization on the first surface of the frame base may be used as the ground reference plane. Metallization on the first surface of the insulating web may be used as the first signal plane or second signal routing layer as used for the voltage plane. Both sides of the ground reference plane on the frame insulation layer and the reference voltage plane on the insulating web can be used as one solid voltage plane that may be required in a high performance logic device or as a plane having multiple insulation reference planes. The configuration of many other signal layers, voltage reference layers and layers including both signal routing and reference planes can be configured as required by specific circuit requirements.

Suitable materials used to form the conductive layer may include one or more of Al, Ag, Au, Cu, Ni, Pb, Sn and Ti. The conductive layer may be applied to the surface of the frame base, the frame insulation layer, and / or the insulating web by electroplating, sputtering or electroless plating. In one embodiment, the conductive layer may be an elemental metal formed by the decomposition of organic metal precursors. The frame base may have a tie layer to improve adhesion with the conductive layer. Suitable materials for use as the tie layer may include polyimide, epoxy and silicone.

The frame adhesive layer may be applied to the second surface of the first frame insulating layer or the surface of the frame base, or may be applied as a sandwich laminate. Application methods may include spin coating, spray coating, roller coating, meniscus coating, pattern print deposition, jetting, or by other dosing methods. The frame insulating layer is disposed on and in contact with the first surface of the frame base after the frame adhesive layer is applied to the first frame insulating layer. The frame adhesive layer may be fully cured to bond the first frame insulation layer to the first surface of the frame base. Suitable materials for use in the adhesive layer may include a thermoset adhesive or radiation cured adhesive. Other suitable tackifiers may include thermosetting plastic tackifiers, water cure adhesives, air cure adhesives. The adhesive layer may be thermally cured or may be cured by a combination of heat and radiation. If thermally curable, a suitable curing temperature may range from approximately 100 degrees Celsius to approximately 200 degrees Celsius. If curable with radiation, suitable radiation may include ultraviolet (UV) light, electron beams, and / or microwave radiation.

Partial vacuum, if any, can be used to remove volatiles from the adhesive during curing. Examples of suitable tackifiers may be thermoset polymers and radiation curable polymers, each of which may be combined with suitable curler hardeners, additives and the like. Suitable thermosetting polymers may include epoxy, silicone, acrylate, urethane, polyetherimide, or polyimide, or mixtures of two or more thereof. Commercially available suitable polyimides include CIBA GEICY 412 (manufactured by Ciba Geigy), AMOCO AI-10 (manufactured by Amoco Chemicals Corporation) and PYRE-MI (manufactured by EI du Pont de Nemours & Co.) Can be. CIBA GEIGY 412 has a T _g of approximately 360 degrees Celsius.

Suitable methods of applying an adhesive layer to an insulating layer (or web) are spray coating, spin coating, roll coating, meniscus coating, dip coating, transfer coating, spraying, drop administration dispensing, pattern print deposition, stenciling, and dry film laminating. The adhesive layer may have a thickness greater than approximately 5 micrometers. In one embodiment, the adhesive layer ranges from approximately 5 micrometers to approximately 10 micrometers, approximately 10 micrometers to approximately 20 micrometers, approximately 20 micrometers to approximately 30 micrometers, approximately 30 micrometers approximately approximately It may have a thickness in the range of 40 micrometers, in the range of approximately 40 micrometers to in the range of approximately 50 micrometers, or in a range greater than approximately 50 micrometers. In another embodiment, the adhesive layer may be a prefabricated self-adhesive film that may be applied to the surface of the additional insulating layer. In yet another embodiment, a mixed adhesive material is used, such as a pressure sensitive adhesive in several fixed points that places the layer in a suitable position while the thermosetting adhesive is cured to b-stage.

The frame insulation layer can be an organic dielectric film or a support web. As used herein, the film or web is a flexible sheet that is not self-supporting. The film has a thickness of less than 0.2 millimeters. The film may be continuous in some embodiments and discontinuous in other embodiments. The film may for example be reinforced with a fibrous material. In addition, the film may comprise a plurality of sub-layers, and the sub-layers may have different compositions and properties from one another. For example, one sub-layer can provide dimensional stability and the other sub-layer can provide electrostatic discharge, thermal conduction, or high dielectric properties. Suitable materials for use as the frame insulation layer may include one or more of polyimide, polyetherimide, benzocyclobutene (BCB), liquid crystal polymer, bismaleimide-triazine resin (BT resin), epoxy or silicone. . Commercially available materials suitable for use in the frame insulation layer are KAPTON H polyimide or KAPTON E polyimide (manufactured by EIdu Pont de Nemours & Co.) APICAL AV polyimide (manufactured by Kanegafugi Chemical Industry Company), UPILEX polyimide Mead (manufactured by UBE industries, Ltd.) and ULTEM polyetherimide (manufactured by General Electric Company). In the illustrated embodiment, the frame insulation layer is fully cured as KAPTON H polyimide.

In another embodiment, the aforementioned laminated frame insulating structure comprising a frame insulating layer and a frame adhesive may be replaced with a single dielectric deposit, such as a thermoset or thermoplastic polymer coating. Thermoplastic polymers are polyetherimides such as ULTEM 1000 or ULTEM 6000 available from GE Plastics, polyether ether ketones such as PEEK available from Victrex, polyether sulfides such as VITREX available from ICI Americas, from Ciba Giegy Polyether sulfides such as XU 218 available, or UDEL 1700 polysulfides available from Union Carbide. Thermosetting or thermoplastic polymers may be applied by spray coating, spin coating, roll coating or dry film laminating.

Suitable conductors include optical and electrical conductors and may be located on the frame insulation layer. Suitable electrical conductors may include pads, pins, bumps, and solder balls. The connector between the frame base and the first frame insulation layer may be a structure selected based on the application specific parameters. For example, the apertures, holes or vias may extend from the first surface of the first frame insulating layer to the first electrically conductive layer disposed on the first surface of the frame base through the frame adhesive layer. The via exposes the metal region on the first surface of the frame base. In one embodiment, vias may be sized such that they are micro-vias. Laser cutting, wet chemical etching, plasma etching, reactive ion etching, or photolithography may form vias. Other suitable via formation could be accomplished, either entirely or partially, using mechanical drilling or perforation.

The electrically conductive material filled in the vias may be a metal, an inherently electrically conductive polymer, a polymer or ceramic filled with an electrically conductive filler, or a metal. When the electrically conductive material is a, suitable metals may include one or more of Ag, Au, Al, Cu, Ni, Sn and Ti. If the electrically conductive material is an inherently electrically conductive polymer, it may be used in an unfilled state, for example to achieve a determined viscosity and / or have a determined wet or degassing capacity. Inherently electrically conductive polymers may be deposited by spraying or screening.

Suitable electrically conductive filler materials may include epoxy, polysulfides, or polyurethanes filled with conductive metal particles, for example. Such metal particles may comprise silver and gold. Other suitable metal particles may include one or more of Al, Cu, Ni, Sn and Ti. Instead of a filled polymeric material, native conductive polymers may be used. Suitable conducting polymers include polyacetylene, polypyrrole, polythiophene, polyaniline, polyfluorene, poly 3-hexylthiophene, polynaphthalene, poly p-phenylene sulfide, and poly para-phenylene vinylene. Of course, the inherently conductive polymer can be filled with an electrically conductive filler to further increase the electrical conductivity.

If the conductive material is a metal, the conductive material may be deposited by a method comprising one or more of sputtering, evaporation, electroplating, or non-electrode plating. Suitable materials may include one or more of Al, Ag, Au, Cu, Ni, Pb, Sn and Ti. In one embodiment, both the first surface of the first frame insulating layer and the exposed surface of the vias extending to the electrical conductor on the frame base are metallized. Metallization may utilize a combination of sputter plating and electroplating sequences. The frame insulation layer may be disposed within the vacuum sputter system with vias exposed to the sputter system and the first surface of the frame insulation layer. A backsputter step sputter-etches the exposed electrical conductors on the frame base to remove residual tack material and natural metal oxides. In addition, the back sputtering step etches into the frame insulating layer surface. The sputter etch of the metal electrical conductor located on the first surface of the frame base reduces the contact resistance of the subsequent metallization step, and etching of the frame insulation layer can increase the metal adhesion to the first surface of the frame insulation layer.

The metal deposited on the first surface of the frame insulation layer can be patterned using subtractive or semi-additive techniques to form metalized vias, pads and signal routing traces. In one semi-additive patterning process, a seed layer having a thickness of approximately 0.1 micrometers to approximately 2.0 micrometers may be applied to the entire frame insulating first surface using a metallization process as described above. The area on the first surface of the frame insulation layer desired to retain metals, such as interconnect traces, I / O contacts, and vias, remains uncovered with a photoresist (not shown) and the metal is desired to be removed. The area of the surface of the frame insulation layer is left covered. The exposed metallization region of the first surface of the frame insulation layer including via sidewalls is electroplated to a thickness in the range of approximately 1 micrometer to approximately 20 micrometers. Following the plating process step, the remaining photoresist material may be removed. The removal exposes the metallization region on the first surface of the frame insulation layer, on which the seed metal was not plated. Many standard wet metal etch electrolyzers can remove exposed seed metal to leave the desired metallization pattern.

In a subtractive metal patterning process, the metallized surface of the frame insulation layer, including via sidewalls, is electroplated with metal to form a layer having a thickness in the range of approximately 2 micrometers to approximately 20 micrometers. do. A photo mask material (not shown) may be disposed in front of the first surface of the frame insulating layer and may be photo-patterned to expose selected areas of the surface. The area on the first surface of the frame insulation layer, which is desired to keep metal such as interconnect traces, I / O contacts, and vias, remains covered with photoresist and the area of the frame insulation surface that caused the metal to be removed Exposed and not covered. Many wet metal etch electrolyzers remove the plated and sputtered metal from the exposed frame insulation layer surface area and the remaining area is protected from the wet etchant by the masking material. After completion of the etching step, the remaining photoresist material may be removed. Removal of the photoresist material results in the desired metallization pattern.

The insulating web is fixed to the frame insulating layer by an insulating web adhesive layer. The insulating web adhesive layer can have a thickness greater than approximately 5 micrometers. In one embodiment, the adhesive layer ranges from approximately 5 micrometers to approximately 10 micrometers, approximately 10 micrometers to approximately 20 micrometers, approximately 20 micrometers to approximately 30 micrometers, approximately 30 micrometers to approximately It may have a thickness in the range of 40 micrometers, approximately greater than 50 micrometers.

The insulating web adhesive layer may be applied to the second surface of the insulating web by spin coating, spray coating, roller coating, meniscus coating, pattern print deposition, or spraying. In one embodiment, the tackifier may be applied by dry film lamination. Suitable tackifiers include those described above.

IO contacts on the logic device are connected with corresponding contacts on the insulating web (see FIG. 4). One example of an I / O contact that can be located on a logic device includes pads, pins, solder bumps, and solder balls. In the illustrated embodiment, the I / O contact is an I / O pad. Other suitable logic devices may be packaged or unpackaged semiconductor chips such as microprocessors, microcontrollers, video processors or application specific integrated circuits (ASICs), a discrete passive, or BGA carriers. In one embodiment, the electronic device may be a semiconductor silicon chip having an array of I / O contact pads disposed on its first surface.

The frame panel assembly may be provided with a number of apertures. If the features are formed in the frame base prior to application of the frame insulation layer, the area of the frame insulation layer overlaying the features in the frame base may be removed. Removal may be by laser ablation, water jets, or by mechanical means.

Referring to FIG. 4, an insulating web (also an insulating web adhesive layer, if necessary) is treated to provide an aperture or via therethrough. Vias are formed in the apertures to provide circuitry and electrical contact. In particular, one contact 50 is toe-in with the first frame conductive layer through the frame insulation layer, the other contact 51 is connected with a metal or a circuit on the frame first insulation layer, and the other contact 52 is It is connected to both the one frame conductive layer and the other contacts 53 which are connected to the I / O contacts on the logic device. Another contact 54 is directly connected with the I / O contact on the circuit device, but not with the first frame insulation layer. In addition, one via 55 extends through both the insulating web and the first frame insulating layer (also a corresponding adhesive layer), and the contact 56 is directly connected with the first frame conductive layer. Other variations, circuits, and structures are envisioned and possible, but not shown. The outward surface 57 of the insulating web has contacts and circuits exposed thereon.

The first surface of the logic device is in contact with the adhesive coated second surface of the insulating web. Alternatively, the insulating web is in direct contact if no tackifier is present. At least a portion of the logic device may be disposed within a frame feature in the frame panel assembly. The adhesive bonds the insulating web to the frame and bonds the logic device to the insulating web.

Some contacts are disposed on the first surface of the logic device and may be referred to as device connectors. The device connector may be connected through conductive material in one or more vias, each extending from the first surface of the insulating web to an I / O contact disposed on the first surface of the logic device. Likewise, the frame insulation layer connector can be secured to the frame insulation layer, the frame base connector can be secured to the frame base, and the insulated web connector can be secured to the insulated web. The conductive material may be disposed in the via, bridged or routed through the support layer as needed.

Other connectors in the interconnect structure and assembly may be formed in a manner similar to the process of forming the first frame connector and the insulation layer connector. In one embodiment, the first surface of the insulating web can be metallized using the metallization and patterning steps described above for the frame insulating layer.

The preceding process step completes the first interconnect layer and its connection to the I / O contacts and conductive layers of the logic device as needed. Although only one logic device with only two I / O contacts is shown for clarity, more complex logic device interconnects are included. Logic devices may include microprocessors, video processors, and ASICs. Some logic devices require an additional interconnect layer to fully route all required chip I / O contacts. For these electronic devices, one or more additional interconnect layers may be formed on the front of the frame and / or insulating web. For simpler logic devices with less complex routing, only one interconnect layer may be required.

Referring to FIG. 5, the inner surface of the frame feature and the outer edge of the logic device disposed within the frame feature define a gap or moat. This gap may be left unfilled or filled with a sealing material. Sealing material 60 surrounds the logic device in the gap. The gap between the inner edge of the frame panel aperture and the outer edge of the logic device may be filled with a sealing material. In other embodiments, the game may be partially filled. The fill height may be in the range of about 1 percent to about 50 percent, in the range of about 50 percent to about 100 percent, or over the logic device, depending on the height of the logic device relative to the insulating web surface. According to another measure, the volume of the gap is approximately 10 percent to approximately 30 percent of the total, approximately 30 percent to approximately 50 percent of the total, approximately 50 percent to approximately 80 percent of the total, or approximately 80 percent of the total And may range from percent to approximately 95 percent of the total.

Suitable sealing materials may include thermoplastic and / or thermoset polymers. Suitable aliphatic and aromatic polymers include polyamides, polyacrylates, polyurethanes, polypropylenes, polysulfides, polytetrafluoroethylenes, epoxies, benzocyclobutenes (BCBs), polyimides, polyetherimides, polycarbonates, silicones, or Two or more of these compounds. Other suitable sealing materials may include room temperature vulcanizing materials. In one embodiment, the sealing material may be a thermoset polymer due to the relatively low cure temperature available. The sealing material may comprise a filler material. The type, size and amount of filler material can be tailored to various molding material properties such as heat conduction, coefficient of thermal expansion, viscosity, swim resistance, shrinkage, out gassing and moisture uptake. Can be used. For example, these materials may include particles, fibers, screens, mats or plates of inorganic particles.

Suitable filler materials may be formed of glass, ceramics, or metals. Some examples of filler materials include silica, SiC, Al ₂ O ₃ , Bn and AlN. Other suitable fillers may include the form of carbon. In one embodiment, the filler material is thermally conductive and electrically insulating. Additives may be added to affect the sealing properties. Some additives can increase glass transition temperature, flexibility, tensile strength, flowability, or oxide resistance. Other affected properties may include heat conduction, coefficient of thermal expansion, viscosity, propagation resistance, shrinkage, and moisture absorption. The sealing material can be cured.

In certain embodiments, it may be advantageous to simultaneously cure the sealing material and the insulating web adhesive layer. The adhesive layer can be radiation cured. Suitable radiation can include IR (heat), UV light, e-beams, and / or microwaves.

5, an additional interconnect layer is formed by fixing the second insulating web 62 to the outward surface of the first interconnect layer 57 using the second insulating web adhesive layer 63. The outward surface 64 of the second insulating web supports, for example, contacts that are connected with the first conductive layer, the second conductive layer, logic device I / O contacts, and other circuitry (not shown). The connection may be made directly using vias extending through the appropriate conductive layer, or indirectly using a connector to connect with the appropriate conductive layer. The interconnect structure 66 may be provided with a sealing layer, additional interconnect layers, pins, solder balls, and the like.

The second surface of the second insulating web may be positioned to contact the outward surface (non-device side) of the first insulating web. The adhesive layer may be cured to bond the second insulating web to the first insulating web. In one embodiment, the second insulating layer may be laminated over the first surface of the insulating web using a heated vacuum lamination system.

The device connector may be connected with an I / O contact disposed on the outward surface of the second insulating web through the second insulating layer. The outward surface of the second insulating web can be metalized to form the corresponding conductive layer. Metallized regions can be used as I / O pads and / or reference planes and / or additional signal routing traces. The process can be additive or subtractive. The additional connector may be formed on at least one electrical conductor on the first surface of the second insulating layer and on a conductive layer or circuit on the frame base or frame insulating layer. The multilayer deep via may be formed to extend from the first surface of the second insulating web to the first surface of the frame insulating layer.

Multiple additional interconnect layers can be formed in a similar manner. Processes of insulating layer coating, via formation, metallization, and light patterning may repeatedly add additional reference planes or interconnect layers.

With respect to the final outward interconnect layer, a dielectric or solder masking material can be used to passivate the metal traces and define the contact pads used for assembly or package I / O contacts. Package I / O contacts allow additional metal deposition to be applied to the exposed contact pads to provide more robust I / O contacts. Suitable additional metal depositions may include alloys such as Ti: Ni: Au. Additional metal deposition can be applied by non-electrode plating. I / O contact pads may have pins, solder spheres, or leads attached thereto, or I / O contact pads may create a pad array.

Referring to FIG. 6, the interconnect structure 67 is similar to the interconnect structure shown in FIG. 5, but with a second frame aperture defined by the fin array 68, the passivation layer 69, and the sidewalls 59. It further includes a passive element 70 located within. The second feature may open through the frame base when the feature 36 is open. One or more passive connectors 72 connect the circuit or first conductive layer to the passive element via via 73.

One of the pins of the illustrated array is connected with one of the logic device I / O contacts, and the other illustrated pins of the array are connected with the other logic device I / O contacts. In alternative embodiments (not shown), solder ball arrays, solder bumps, electrically conductive polymer bumps, contact pads, leads or optical I / O connections are used in place of the pins.

Passive connectors allow connection from I / O contacts on passive elements to conductors located on insulating webs. The passive connector may include one or more vias each extending from an first surface of the insulating web to an I / O contact located on the surface of the passive element. The electrically conductive material may be disposed within at least a portion of the via, which extends through the via to an I / O contact located on the passive element.

FIG. 7 is a schematic diagram illustrating a structure 100 in which a thin frame insulating layer 110 and an electrically conductive layer 112 are deposited on a first conductive layer 18 located on a frame base surface. Portions of the conductive and frame insulating layers are removed to form a distributed passive element. One example of a distributed passive element is a decoupling capacitor.

The thin frame insulating layer may be formed of an organic dielectric material. Suitable organic dielectric materials may include polyimide or diamondoid carbon. The layer may be deposited by spin coating (polyimide) or may be deposited by evaporation (DLC). In an alternative embodiment, the thin frame insulating layer may be formed of an inorganic dielectric material. Suitable inorganic dielectric materials may include SrTiO ₃ , PZT, BST, TaO ₂ or BaTiO ₃ . The layer may be formed by chemical dissolution deposition, metal oxide deposition, or hydrothermal synthesis.

The conductive layer can be patterned to expose selected areas of the thin electrically resistive dielectric layer on the frame insulating layer. Alternatively, the electrically conductive layer, thin resistive dielectric layer and thin frame insulating layer can be separately patterned to expose selected areas of the first frame electrical conductor that produce the thin resistive dielectric layer, thin frame insulating layer and the patterned passive element. . Examples of patterned passive elements can include resistors, capacitors, inductors, and conductor elements.

8-9, frame panel assembly 120 includes a plurality of interconnect structures 66, each structure having a plurality of through-holes that are sized and shaped to receive array pins during manufacture. Has (122). The frame surface may be patterned to form an area free of conductive material through which through-holes may be formed (FIG. 9). Suitable through-hole forming processes may include mechanical drilling, drilling, laser ablation, or water jets.

After the through-hole is formed in the frame base (in the non-patterned area), the through-hole can be metal plated 126 to better receive the array fins. The pins can be mechanically and electrically connected to the patterned metal on the insulating layer (s) using solder or an electrically conductive adhesive.

In alternative embodiments, the logic device may be an optical device. In such cases, some or all of the connectors and conductors described herein may be optically transmissive rather than electrically transmissive. Suitable optical connectors and / or conductors may include optical fibers and / or waveguides.

The embodiments described herein are examples of configurations, structures, systems and methods having elements corresponding to the elements of the invention recited in the claims. This description may enable those skilled in the art to make and use embodiments having alternative elements that likewise correspond to the elements of the invention recited in the claims. Accordingly, the scope of the present invention includes structures, structures, systems and methods that do not differ from the literal language of the claims, and other structures, systems and methods that differ little from the literal language of the claims. It includes more. Although only certain features and embodiments are illustrated and described herein, numerous modifications and changes may occur to those skilled in the art. The appended claims cover all such modifications and changes.

1 is a schematic side view of an intermediate product;

2 is a schematic side view of a frame assembly according to an embodiment of the present invention formed from the intermediate product of FIG. 1;

3 is a cross-sectional perspective side view of the frame assembly of FIG. 2 and a logic device bonded thereto in accordance with an embodiment of the present invention;

4 is a schematic side view of an interconnect structure according to an embodiment of the present invention;

5 is a schematic side view of an interconnect structure provided from the interconnect structure of FIG. 4 in accordance with an embodiment of the present invention;

6 is a schematic side view of an interconnect structure according to an embodiment of the present invention;

7 is a schematic side view of a frame assembly having a metal layer and an insulating layer in accordance with an embodiment of the present invention;

8 is a schematic top view of a plurality of frame assemblies according to an embodiment of the invention;

9 is a schematic side view of an interconnect structure according to an embodiment of the present invention.

Claims (10)

An insulative web having a first surface and a second surface, A logic device secured to the second surface of the insulating web, A frame assembly supporting the insulating web, the frame assembly comprising a frame base and a first conductive layer; A device connector operable to connect said logic device with said first conductive layer, The frame base has a first surface, a second surface, and an inward facing surface that extends through the frame base and defines frame features in which at least a portion of the logic device is disposed; The first conductive layer is located on the first surface of the frame base Interconnect structure. The method of claim 1, The insulating web is a polymer film Interconnect structure. The method of claim 1, The frame assembly further includes a first frame insulating layer disposed between the first surface of the frame base and the insulating web. Interconnect structure. The method of claim 3, wherein The first frame insulating layer comprises a first surface and a second surface, The frame assembly, A second frame insulating layer having a first surface and a second surface, the first surface of the first frame insulating layer being fixed to the second surface of the second frame insulating layer; Further comprising a second frame connector between a second electrically conductive layer located on said first frame insulating layer and a fourth electrical conductor located on said second frame insulating layer. Interconnect structure. A frame base having a first surface and a second surface and conductive, a first frame insulating layer disposed on the first surface of the frame base, a frame aperture extending through the frame base, on the first frame insulating layer A frame assembly comprising a frame conductive layer disposed thereon and a frame connector supported by the frame base and connected to at least a portion of the frame conductive layer; An insulating web having a first surface and a second surface, An insulating web conductor layer supported by the insulating web, A logic device supported by the insulating web and disposed within the frame aperture; A device connector connected with the insulating web conductive layer; A frame connector coupled with the frame conductive layer and the insulating web conductive layer; product. The method of claim 5, The logic device is an optical device, The frame connector and the device connector are optically transmissive, The frame conductive layer and the insulating web conductive layer include a waveguide product. A frame for supporting a web and a logic device secured to the web; An optical or electronic circuit supported by the frame and coupled with the logic device; Electronic devices. The method of claim 7, wherein Further comprising an electronic device connector for connecting the logic device to the electronic circuitry; Electronic devices. The method of claim 7, wherein Further comprising an optical device connector to connect the logic device with the optical circuitry Electronic devices. The method of claim 7, wherein The frame is electrically conductive and further comprises a dielectric layer disposed adjacent the electronic device on the surface of the frame. Electronic devices.

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