JP5586841B2 - Interconnect structure - Google Patents

Description

  The invention includes embodiments that relate to an interconnect structure. The interconnect structure may be electrical or optical.

  In the current embedded chip process called ECBU (Embedded Chip Build-Up) technology or CFBU (Chips First Build-Up) technology, bare chips are either I / O distributed with peripheral or peripheral I / O pads or on the top surface. Along with the arrangement of pads, it is packaged in a high density interconnect structure without the need for either solder bonding or wire bonding. The ECBU or CFBU process forms a chip carrier that interconnects complex semiconductor chips and large conductor pads that fit a wide range of assemblies such as printed circuit boards.

Semiconductor devices continue to be manufactured with increasing I / O numbers (4000 to 8000 or more). Since CFBU technology is applied to these increasingly complex semiconductor devices, the corresponding increasing routing requirements of the chip can utilize additional routing layers and / or thinner conductor lines, and You are forced to use the space between the lines. Adding additional routing layers with the same feature dimensions, coupled with routing more lines with smaller features, can increase yield loss. In CFBU technology, the interconnect layer and the lines, spaces, and interlayer vias corresponding to this interconnect layer are not formed until the chip is received in the carrier, so increasing yield loss results in the disposal of many expensive chips. Increase the risk of Also, the decoupling capacitor must be close to a fast switching processor in order to be effective. For example, a CFBU carrier with a thin profile of less than 1 mm may not have enough space to mount the necessary discrete decoupling capacitors in the carrier compared to an industry standard flip chip stacked carrier with a profile of 2 mm or more. There is. Also, the mechanical strength of the pins of the pin grid array is lower than the solder balls of the ball grid array.
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  In one embodiment, the present invention provides an electronic component that includes a frame that can support a web and logic elements secured to the web. The frame supports an optical circuit or an electronic circuit, and the supported optical circuit or electronic circuit communicates with the logic element.

  In one aspect, the electronic circuit includes passive electronic components such as capacitors, inductors, and resistors. In another aspect, the optical circuit includes a beam splitter, a mirror, a grating, and the like. The frame can be combined with other elements to form an electronic package.

  In one embodiment, the present invention provides an interconnect structure, the interconnect structure having an insulating web having a first surface and a second surface, and a logic secured to the second surface of the insulating web. An element and a frame panel assembly, wherein the frame panel assembly is between a frame base having a first surface and a second surface, and between the first surface of the frame base and the second surface of the insulating web. A first frame insulating layer disposed on the frame base, and an opening extending through the frame base and the first frame insulating layer, in which at least a part of the logic element is disposed; A first frame connector disposed between a first conductive layer disposed on a first surface of the frame base and a second conductive layer disposed on a surface of the first frame insulating layer; Said interconnection The structure is further disposed on the surface of the insulating web, with an element connector disposed between an I / O contact on the surface of the logic element and a third conductor disposed on the surface of the insulating web. An insulating layer connector disposed between the third conductor and the second conductive layer disposed on the surface of the first frame insulating layer.

  In another embodiment, the present invention provides an insulating web having a first surface and a second surface, a logic element secured to the second surface of the insulating web, a frame panel assembly, A frame base having a first surface and a second surface; a first frame insulating layer disposed between the first surface of the frame base and a second surface of the insulating web; the frame base and the second surface; A first insulating layer extending between the frame base and the first frame insulating layer; and an opening in which at least a portion of the logic element is disposed; A frame panel assembly including a frame connector, an element connector disposed between the logic element and the insulating web, and an insulating layer disposed between the insulating web and the first frame insulating layer. To provide a product that includes a connector.

  The present invention includes embodiments relating to interconnect structures. The interconnect structure can comprise an integrated frame assembly. The interconnect structure may be optical or electrical.

  A passive component or element as used herein is a component that consumes (but does not generate) electrical energy or that cannot perform power acquisition. Non-passive components are called active components. A circuit consisting entirely of passive components is also considered passive (and has the same characteristics as passive components). In this definition, passive components include capacitors, inductors, resistors, transformers, voltage sources and current sources. Active components include components having one or more transistors, repeaters, glow discharge tubes, constant voltage discharge tubes, tunnel diodes and similar elements. Unless the context or term indicates otherwise, the term “insulating” means electrically insulating and the term “conductive” means conducting layer. An “interconnect layer” is an insulating layer having at least one via and at least one circuit or connector on a circuit.

  Referring to FIGS. 1 and 2, an interconnect intermediate structure 2 is shown. The intermediate structure 2 (FIG. 1) is changed to produce a frame 10 (FIG. 2) according to an embodiment of the present invention. The frame includes a frame base 12 having a first surface 14 and a second surface 16. The first conductive layer 18 is fixed to the first surface of the frame base. The frame adhesive layer 20 fixes the first frame insulating layer 22 to the frame base and overlaps at least a part of the first conductive layer. The frame adhesive layer is not shown in some of the drawings for clarity. The first frame insulating layer comprises a first surface 24 facing outward and a second surface 26 facing inward. The second conductive layer 28 is disposed on the first surface of the first frame insulating layer.

  Referring to FIG. 2, vias 30 are formed and extend through the frame adhesive layer and the first frame insulating layer. The via is filled with a conductive layer material to form the first frame connector 32. The first frame connector enables communication with a first conductive layer provided on the first surface of the frame base via the frame adhesive layer and the first frame insulating layer. The conductive wiring or contact 34 is formed on the surface facing the outside of the first frame insulating layer. The frame base has an internal surface 35 that defines a frame opening 36 extending through the frame base.

  FIG. 3 is a cross-sectional perspective view of a frame assembly 37 that includes the frame of FIG. 2 (not to scale) and an insulating web 38 that is secured to the frame by an insulating adhesive layer 39. The insulating web extends beyond the open end of the frame opening, otherwise the open end that remains open closes to form a nest or depression. The logic element 40 is shown attached to the insulating web within the frame opening and spaced from the inwardly facing surface of the frame base. The logic element has a first surface 42 and a second surface 44. The first surface of the logic element includes I / O contacts 46. The I / O contacts of the logic element face the inside of the insulating web adhesive layer if it extends on the surface facing the inside of the insulating web or if the insulating web adhesive layer extends on the surface facing the inside of the insulating web On the surface, it is electrically coupled with a corresponding adhesive pad (not shown) or the like. A trench groove or gap 48 is defined by the surface of the logic element and the inwardly facing surface of the frame base. Reference numeral 49 represents the surface facing the outside of the insulating web.

  Although the alternative frame may be a single body, the illustrated frame includes a frame base, a frame insulating layer, and a frame adhesive layer that bonds them together. In some embodiments, the metallization layer, the circuit, and the passive portion may be incorporated in or embedded in any of the previously described members.

  The frame base can be formed of a material selected from metal, ceramic or polymeric materials. Suitable polymeric materials include polyimide, ROMP capable monomers, epoxy resins, and the like. The polymeric material may include a reinforcing filler. Such fillers can include fibers or small inorganic particles. Suitable fibers may be glass fibers or carbon fibers. Suitable particles include silica, silicon carbide, boron nitride, aluminum oxide, aluminum nitride, and the like. When formed from a polymeric material, the frame base may be a molded structure or a cast structure. Suitable molding techniques include resin injection molding and bulk molding.

  The frame base includes a material selected for a specific design based on the desired coefficient of thermal expansion, stiffness, or other desired mechanical, electrical, and thermal properties. When the frame base is conductive, a dielectric or electrically insulating protective film can be applied to the surface of the frame base. A suitable conductive layer frame material may be a metal. Suitable metals for use as the frame base may be selected from aluminum, nickel, titanium, iron, copper or tin. As an alternative configuration, the metal may be an alloy or a metal composite. Suitable alloys and composite materials include, for example, stainless steel or Cu: Invar: Cu. A suitable electrically insulating protective film material may be a ceramic material, a polymeric material or an enamel. The protective film material may be selected based on thermal expansion coefficient matching, protective film dielectric properties, adhesives and other properties of the materials utilized in conjunction with each other. The electrically insulating protective film material can insulate the conductive wiring from the electronic device supported on the frame base.

  The material of the frame base and insulating layer must be selected so as to prevent distortion of the frame base during use. The frame base material must be selected such that the coefficient of thermal expansion (CTE) is approximately consistent with the CTE of one or more components used to assemble the structure. The semiconductor carrier can also be fixed to an organic printed circuit board. Such a printed circuit board may have a CTE in the range of about 15 ppm / ° C. to about 20 ppm / ° C. If the CTE of the insulating layer is higher than the CTD of the circuit board, the frame base may be distorted and concave. If the CTE of the insulating layer is lower, the frame base may be distorted and convex. By selecting the frame base to have a relatively increased Young's modulus, the risk of distortion can be reduced, but the stress and strain on the frame base can be relatively high. In addition, by selecting the insulating layer so that at least one of the Young's modulus of the insulating layer and the shrinkage rate of the insulating layer being cured is low, the risk of distortion and stress and strain are suppressed. Can do.

  The frame base and thus the frame has an inwardly facing surface that defines an opening or opening. The opening can be formed in the frame base by milling, mechanical stamping, laser cutting, water jet, wet etching, laser ablation, punching or dry etching. The logic element can be supported on the insulating web within the opening (more details are described below). The opening may be formed before or after the addition of the frame insulating layer, the frame adhesive layer, the first conductive layer, and other components.

  The first conductive layer may be a metallization plane formed on at least a portion of the frame base first surface, and the metallization plane is, optionally, of the frame base second surface. It may also be formed at least on selected parts. The first conductive layer is a continuous metal surface that can function as a reference surface. This reference plane may be a ground plane or a power plane. As an alternative configuration, the first conductive layer may be a segmented metal surface. While the metallization on the first surface of the frame insulation layer can be used as a signal routing layer, the metallization on the first surface of the frame base may be utilized as a ground reference plane. The metallization on the first surface of the insulating web can be utilized as either the second signal routing layer or the second reference plane as utilized for the voltage plane. Both the ground reference on the frame insulation layer and the reference voltage plane on the insulation web are utilized as a single solid voltage plane or a plane with multiple independent reference planes that may be required for high performance logic elements. be able to. Many other configurations for the signal layer, voltage reference layer, and layers that include both the signal routing plane and the reference plane can be configured depending on the needs dictated by specific circuit requirements.

  Suitable materials for use in forming the conductive layer can include one or more of Al, Ag, Au, Cu, Ni, Pb, Sn, and Ti. The conductive layer may be applied to the surface of at least one of the frame base, the frame insulating layer, and the insulating web by electroplating, sputtering, or electroless plating. In one embodiment, the conductive layer may be an elemental metal formed by decomposition of an organometallic precursor. The frame base may have a tie layer that improves adhesion with the conductive layer. Examples of materials suitable for use as the tie layer include polyimide, epoxy resin, and silicone.

  The frame adhesive layer can be applied to the second surface of the first frame insulating layer, to the surface of the frame base, or as a sandwich structure. Application methods include spin coating, spray coating, roller coating, meniscus coating, pattern printing deposition, spraying or other dispensing methods. The frame insulating layer is disposed on the first surface of the frame base in contact with the first surface after the frame adhesive is applied to the first frame insulating layer. The frame adhesive layer may be fully cured to bond the first frame insulating layer and the first surface of the frame base. Suitable materials for use in the adhesive layer can include thermosetting adhesives or radiation curable adhesives. Other suitable adhesives include thermoplastic resin adhesives, water curable adhesives, and air curable adhesives. The adhesive layer may be cured by heat or by a combination of heat and radiation. If it is thermosetting, a suitable curing temperature is in the range of about 100 ° C to about 200 ° C. When radiation curable, suitable radiation can include ultraviolet (UV) light, electron beam, and / or microwave radiation.

If volatiles are present, partial vacuum can be utilized to remove volatiles from the adhesive during curing. Examples of suitable adhesives include those in which a thermosetting polymer and a radiation curable polymer are combined with appropriate curing agents, hardeners, additives and the like, respectively. Suitable thermosetting polymers include epoxy resins, silicones, acrylates, urethanes, polyetherimides, polyimides, or mixtures of two or more thereof. Suitable polyimides that are commercially available include CIBA GEIGY 412 (Ciba Gaigy), AMOCO AI-10 (Amoco Chemicals) and PYRE-MI (EI du Pont de Nemours). CIBA GEIGY 412 has a T _{g of} about 360 ° C.

  Suitable methods for applying the adhesive layer to the insulating layer (or web) are spray coating, spin coating, roll coating, meniscus coating, dip coating, transfer coating, jetting, droplet dispensing, pattern printing deposition, screen printing. And dry film lamination. The adhesive layer can have a thickness greater than about 5 μm. In one embodiment, the adhesive layer has a thickness in the range of about 5 μm to about 10 μm, about 10 μm to about 20 μm, about 20 μm to about 30 μm, about 30 μm to about 40 μm, about 40 μm to about 50 μm, or greater than about 50 μm. Can do. In an alternative embodiment, the adhesive layer may be a ready-made adhesive film that can be applied to the surface of the additional insulating layer. In another alternative embodiment, a mixed adhesive material such as a pressure sensitive adhesive is utilized at some tack points to hold the layer in place while the thermoset adhesive is cured to the B stage. The

  The frame insulating layer may be an organic dielectric film or a support web. As used herein, a film or web is a flexible sheet that is not free-standing. The membrane has a thickness of less than 0.2 mm. The membrane may be continuous in some embodiments or discontinuous in other embodiments. This membrane can be reinforced using, for example, a fiber material. The film can also include a plurality of sublayers, which can have different compositions and properties. For example, one sublayer can provide dimensional stability and the other can provide electrostatic discharge, heat conduction, or high dielectric properties. Materials suitable for use as the frame insulating layer include at least one of polyimide, polyetherimide, benzocyclobutene (BCB), liquid crystal polymer, bismaleimide / triazine resin (BT resin), epoxy resin or silicone. Can be included. Commercially available materials suitable for use in the frame insulating layer include KAPTON H polyimide or KAPTON E polyimide (manufactured by EI du Pont de Nemours), APICAL AV polyimide (Kanebuchi Chemical Industry Co., Ltd.) ), UPILEX polyimide (manufactured by Ube Industries), and ULTEM polyetherimide (manufactured by General Electric). In the illustrated embodiment, the frame insulation layer is fully cured as KAPTON H polyimide.

  In other embodiments, the aforementioned laminated frame insulation structure comprising a frame insulation layer and a frame adhesive is applied to a single dielectric deposit such as a thermosetting or thermoplastic polymer coating or an adhesive frame insulation layer. Can be replaced. The thermoplastic polymer is a polyetherimide resin such as ULTEM1000 or ULTEM6000 commercially available from GE Plastics, a polyetheretherketone such as PEEK commercially available from Victrex, a polyethersulfone resin such as VITREX commercially available from ICI Americas, Ciba It may be a polyethersulfone resin such as XU218 commercially available from Gaigy or UDEL 1700 polysulfone commercially available from Union Carbide. Thermoplastic or thermosetting polymers can be applied by spray coating, spin coating, roll coating or dry film lamination.

  Suitable conductors include light guides and conductors and can be disposed on the frame insulation layer. Suitable conductors include pads, pins, bumps and solder balls. The connector between the frame base and the first frame insulation layer may be a structure that is selected based on the application specific parameters. For example, the opening, hole, or via extends from the first surface of the first frame insulating layer through the frame adhesive layer to the first conductive layer disposed on the first surface of the frame base. The via exposes a metal area on the first surface of the frame base. In one embodiment, the via may be sized to be a micro via. Vias can be formed by laser ablation, wet etching, plasma etching, reactive ion etching or photolithography. Other suitable via formation may be performed in whole or in part using mechanical drilling or stamping.

  The electrically conductive material filled in the via may be a metal, an intrinsically conductive polymer, a conductive layer filler, or a polymer or ceramic to which a metal is added. When the conductive layer material is a, suitable metals can include one or more of Ag, Au, Al, Cu, Ni, Sn, and Ti. When the electrically conductive material is an intrinsically conductive polymer, it is used in an unfilled state, for example, at least one of achieving a predetermined viscosity and having a predetermined wetting performance or degassing performance. Can be realized. The intrinsically conductive polymer can be deposited by spraying or screening.

  Suitable conductive layer filling materials include, for example, epoxy resins to which conductive metal particles are added, polysulfone or polyurethane. Such metal particles include silver or gold. Other suitable metal particles can include one or more of Al, Cu, Ni, Sn, and Ti. Instead of the filled polymer material, an intrinsically conductive polymer may be used. Suitable conductive polymers include polyacetylene, polypyrrole, polythiophene, polyaniline, polyfluorene, poly-3-hexylthiophene, polynaphthalene, poly p-phenylene sulfide and polyparaphenylene vinylene. Of course, a conductive layer filler may be added to the intrinsically conductive polymer to further improve the electrical conductivity.

  When the conductive material is a metal, the conductive material may be deposited by a method that includes one or more of sputtering, vapor deposition, electroplating or electroless plating. Suitable metals may include one or more of Al, Ag, Au, Cu, Ni, Pb, Sn and Ti. In one embodiment, the first surface of the first frame insulating layer and the exposed surface of the via extending to the conductor on the frame base are both metallized. For this metallization, a combination of sputter plating and electroplating can be used. The frame insulating layer may be disposed in a vacuum sputtering system, and the first surface of the frame insulating layer and the via may be exposed by the sputtering system. In the back sputtering process, the exposed conductor can be sputter etched into the frame base to remove residual adhesive material and intrinsic metal oxide. Further, in the back sputtering process, etching into the surface of the frame insulating layer is performed. Sputter etching of the metal conductor disposed on the first surface of the frame base suppresses the contact resistance of the subsequent metallization step, while etching of the frame insulating layer is metal adhesion to the first surface of the frame insulating layer. Can be improved.

  The metal deposited on the first surface of the frame insulating layer can be patterned to form metallized vias, pads and signal routing wiring using subtractive or semi-additive techniques. In the semi-additive patterning process, a seed layer having a thickness of about 0.1 μm to about 2.0 μm can be applied to the entire first surface of the frame insulation using a metallization process as described above. Of the area on the first surface of the frame insulation layer, areas that are required to hold metal, such as interconnect wiring, I / O contacts, and vias, remain uncovered with photoresist (not shown). Of the region on the surface of the frame insulating layer, the region where the metal is required to be removed remains in the coated state. The exposed metallized area of the first surface of the frame insulating layer, including the via sidewalls, is then formed by electroplating to a thickness in the range of about 1 μm to about 20 μm. After the plating process is complete, the remaining photoresist material may be removed. This removal exposes the metallized areas on the first surface of the frame insulating layer that were not plated with the seed metal. In several standard wet metal etch baths, the exposed seed metal can be removed to leave the desired metallization pattern.

  In the subtractive metal patterning process, the metallized surface of the frame insulating layer including the via sidewalls is electroplated with metal to form a layer having a thickness in the range of about 2 μm to about 20 μm. A photomask material (not shown) may be deposited on the first surface of the frame insulating layer, and photopatterning may be performed to expose specified areas of the surface. Of the region of the first surface of the frame insulating layer, the region required to hold the metal, such as interconnect wiring, I / O contacts, and vias, is coated with a photoresist, and of the region of the frame insulating surface, The area where the metal is to be removed is exposed without being coated. A plurality of wet metal etch baths remove the plated and sputtered metal in the surface area of the exposed frame insulation layer, while the remaining areas are protected from the wet etchant by the masking material. . After completion of the etching process, the remaining photoresist material may be removed. By removing the photoresist material, the desired metallization pattern is exposed.

  The insulating web is secured to the frame insulating layer by an insulating web adhesive layer. The insulating web adhesive layer can have a thickness greater than about 5 μm. In one embodiment, the adhesive layer has a thickness in the range of about 5 μm to about 10 μm, about 10 μm to about 20 μm, about 20 μm to about 30 μm, about 30 μm to about 40 μm, about 40 μm to about 50 μm, or greater than about 50 μm. obtain.

  The insulating web adhesive layer can be applied to the second surface of the insulating web by spin coating, spray coating, roller coating, meniscus coating, pattern printing deposition or spraying. In one embodiment, the adhesive may be applied by dry film lamination. Suitable adhesives include those described above in this specification.

  IO contacts on the logic element communicate with corresponding contacts on the insulating web (see FIG. 4). Examples of I / O contacts that can be placed on a logic element include pads, pins, solder bumps, and solder balls. In the illustrated embodiment, the I / O contact is an I / O pad. Other suitable logic elements are packaged or unpackaged semiconductor chips such as microprocessors, microcontrollers, video processors, ASICs (application specific integrated circuits), discrete passive components, or BGAs It may be a career. In one embodiment, the electronic device may be a semiconductor silicon chip having an array of I / O contact pads provided on the first surface.

  The frame panel assembly can be made with a plurality of openings. In the case where the opening is formed in the frame base before application of the frame insulating layer, the region of the frame insulating layer overlapping the opening of the frame base may be removed. This removal can be done by laser ablation, water jet method or mechanical means.

  Referring to FIG. 4, the insulating web (and the insulating web adhesive layer, if necessary) has been processed to provide openings or vias through the layer. Vias are formed in the openings to provide circuitry and electrical contacts. In particular, one contact 50 communicates with a contact that passes through the frame insulation layer to the first frame conductive layer, and another contact 51 communicates with a metal coating or circuit on the frame first insulation layer. The contact 52 communicates with both the first frame conductive layer and the other contact 53 that communicates with the I / O contact of the logic element. Yet another contact 54 communicates directly with the I / O contact on the circuit element, but does not communicate with the first frame conductive layer. Also, one via 55 extends through both the insulating web and the first frame insulating layer (and corresponding adhesive layer), and the contact 56 communicates directly with the first frame conductive layer. Other sequences, circuits and structures can be devised and used, but are not specifically shown here. The outwardly facing surface 57 of the insulating web has exposed contacts and circuitry on the surface.

  The first surface of the logic element is in contact with the second surface of the insulating web coated with adhesive. An alternative arrangement is to contact the insulating web directly if no adhesive is present. At least a portion of the logic element can be disposed within the frame opening of the frame panel assembly. The adhesive bonds the insulating web to the frame and bonds the logic elements to the insulating web.

  Some contacts are disposed on the first surface of the logic element and can be considered as an element connector. The device connector can conduct through conductive material in one or more vias, each of the one or more vias being disposed from the first surface of the insulating web onto the first surface of the logic device. It extends to the installed I / O contact. Similarly, the frame insulation layer connector can be secured to the frame insulation layer, the frame base connector can be secured to the frame base, and the insulation web connector can be secured to the insulation web. Conductive material may be placed in the vias as needed to form a bridge or path through the support layer.

  The interconnect structure and other connectors in the assembly may be formed in a manner similar to the process of forming the first frame connector and the insulating layer connector. In one embodiment, the first surface of the insulating web may be metallized using the metallization and patterning steps described above for the frame insulating layer.

  In the preceding processing steps, the first interconnect layer and the connections to the I / O contacts and conductive layers of the logic elements of the first interconnect layer are completed as needed. For clarity, only a single logic element having only two I / O contacts is shown, but more complex logic element interconnections are incorporated. Examples of the logic element include a microprocessor, a video processor, and an ASIC (application specific integrated circuit). Some logic elements require an additional interconnect layer to construct a complete path for all the necessary chip I / O contacts. For these electronic devices, one or more additional interconnect layers can be formed on at least one of the frame and the insulating web. For simple logic elements with less complex routing, only one interconnect layer may be required.

  Referring to FIG. 5, a gap or moat is defined by the inner surface of the frame opening and the outer edge of the logic element disposed in the frame opening. This gap may be left unfilled or filled with a sealing material. The sealing material 60 surrounds the logic elements in the gap. The gap between the inner edge of the frame panel opening and the outer edge of the logic element can be filled with a sealing material. In other embodiments, the game may be partially filled. The fill height may range from about 1% to about 50%, from about 50% to about 100%, or may overflow from the top of the logic element, based on the height of the logic element relative to the insulating web surface. . According to other measures, the gap volume may satisfy about 10% to about 30%, about 30% to about 50%, about 50% to 80%, or about 80% to about 95%. It may be a range.

  Suitable sealing materials can include at least one of a thermoplastic polymer and a thermosetting polymer. Suitable aliphatic and aromatic polymers include polyamide, polyacrylate, polyurethane, polypropylene, polysulfone, polytetrafluoroethylene, epoxy resin, benzocyclobutene (BCB), polyimide, polyetherimide, polycarbonate, silicone or A mixture of two or more of these may be mentioned. Other suitable sealing materials include room temperature vulcanizable materials. In one embodiment, the encapsulant may be a thermosetting polymer because a relatively low curing temperature can be utilized. The sealing material can include a filler material. Various types of molding material properties such as thermal conductivity, thermal expansion coefficient, viscosity, floating resistance, shrinkage, degassing and hygroscopicity can be adjusted using the type, size and amount of filler material. For example, these materials can include particles, fibers, screens, mats, and plates of inorganic particles.

Suitable filler materials can be formed from glass, ceramic or metal. Some examples of filler materials include silica, SiC, Al ₂ O ₃ , BN, AlN, and the like. Other suitable fillers include the form of carbon. In one embodiment, the filler material is thermally conductive and electrically insulating. Additives may be added to affect the properties of the sealant. Some additives can increase glass transition temperature, flexibility, tensile strength, flowability or oxidation resistance. Other properties that are affected include thermal conductivity, thermal expansion coefficient, viscosity, floating resistance, shrinkage rate, hygroscopicity, and the like. The sealing material may be cured.

  In certain embodiments, it is advantageous to cure the encapsulant and the insulating web adhesive layer simultaneously. The adhesive layer can be radiation cured. Suitable radiation may include at least one of IR (heat), ultraviolet light, e-beam, and microwave.

  With further reference to FIG. 5, an additional interconnect layer is formed, which interconnect layer is formed on the outwardly facing surface of the first interconnect layer 57 using a second insulating web adhesive layer 63. It is formed by fixing the insulating web 62. The outer surface 64 of the second insulating web supports contacts in communication with, for example, the first conductive layer, the second conductive layer, the logic element I / O contacts, and other circuits (not shown). The communication may be directed directly to the conductive layer using vias that extend through the appropriate conductive layer or indirectly using a connector in communication with the appropriate conductive layer. The interconnect structure 66 can be made with a sealing layer, additional interconnect layers, pins, solder balls, and the like.

  The second surface of the second insulating web can be arranged in contact with the surface facing the outside of the first insulating web (non-component side). The adhesive layer can be cured to bond the second insulating web to the first insulating web. In one embodiment, the second insulating layer may be laminated onto the first surface of the insulating web using a heated vacuum lamination system.

  The element connector can communicate with an I / O contact disposed on a surface facing the outside of the second insulating web through the second insulating layer. The outwardly facing surface of the second insulating web can be metallized to form a corresponding conductive layer. The metallized area can be utilized for at least one of I / O pads, reference planes, and additional signal routing wiring. This process may be additive or subtractive. The additional connector can be formed between at least one conductor on the first surface of the second insulating layer and a conductive layer or circuit on the frame base or frame insulating layer. A deep via that extends from the first surface of the second insulating web to the first surface of the frame insulating layer may be formed.

  Multiple additional interconnect layers can be formed in a similar manner. Insulating layer application, via formation, metallization and photo patterning processes can be repeated to add additional reference planes or interconnect layers.

  For the last outward facing surface interconnect layer, a dielectric or solder resist material is used to passivate the metal wiring and define the conductor pads used for the I / O contacts of the assembly or package. May be. In order to provide a more robust I / O contact, the I / O contact of the package can be provided with additional metal deposits applied to exposed conductor pads. Suitable additional metal deposits can include alloys such as Ti: Ni: Au. Additional metal deposits may be applied by electroless plating methods. Although the I / O conductor pads can comprise pins, solder balls, or conductors attached thereto, the I / O conductor pads may form a pad array.

  Referring to FIG. 6, interconnect structure 67 is similar to the interconnect structure shown in FIG. 5, but within a second frame opening defined by an array of pins 68, a protective layer 69, and an inner wall 59. And a passive element 70 disposed on the substrate. The second opening can be opened from the frame base when the opening 36 is opened. One or more passive connectors 72 are in contact with passive elements via vias 73, circuits, or first conductive layers.

  One pin of the illustrated array communicates with one of the logic element I / O contacts, and the other illustrated pin of the array communicates with the other logic element I / O contact. In an alternative embodiment (not shown), an array of solder balls, solder bumps, conductive layered polymer bumps, conductor pads, conductors or optical I / O connections is utilized instead of pins.

  The passive connector allows a conductor disposed on the insulating web to communicate from the I / O contact of the passive element. The passive connector can include one or more vias that extend from the first surface of the insulating web to an I / O contact disposed on the surface of the passive element. Conductive layered material can be provided in at least a portion of the via, and the conductive layered material extends from the via to an I / O contact disposed on the passive device.

  FIG. 7 is a schematic diagram illustrating a structure 100 in which a thin frame insulating layer 110 and a conductive layer 112 are disposed on a first conductive layer 18 disposed on a frame base surface. By removing a part of the frame insulating layer and the conductive layer, a distributed passive element is formed. An example of a distributed passive element is a decoupling capacitor.

The thin frame insulating layer can be formed from an organic dielectric material. Suitable organic dielectric materials include polyimide or diamond like carbon (DLC). The layer can be applied by spin coating (polyimide) or by vapor deposition (DLC). In an alternative embodiment, the thin frame insulating layer can be formed from an inorganic dielectric material. Suitable inorganic dielectric materials include SrTiO ₃ , PZT, BST, TaO ₂ or BaTiO ₃ . The layer can be formed by chemical solution deposition, metal oxide deposition or hydrothermal synthesis.

  The conductive layer may be patterned to expose selected regions of the thin electrically resistive dielectric layer on the frame insulating layer. As an alternative configuration, the conductive layer, the thin resistive dielectric layer, and the thin frame insulating layer are individually patterned to select the thin resistive dielectric layer, the thin frame insulating layer, and the first frame conductor. Patterned passive elements may be fabricated with exposed regions. Examples of patterned passive elements include resistors, capacitors, inductors, and conductor elements.

  Referring to FIGS. 8-9, the frame panel assembly 120 can include a plurality of interconnect structures 66, each interconnect structure having a plurality of penetrations sized and shaped to receive an array of pins when processed. It has a hole 122. The frame surface can be patterned to form a region that does not include a conductive material, and a through hole can be formed in a region that does not include the conductive material (FIG. 9). Suitable through-hole forming processes include mechanical drilling, punching, laser ablation, water jet method, and the like.

  After the through holes are formed in the frame base (non-patterned region), the through holes can be provided with metal plating 126 to facilitate receiving the alignment pins. These pins can be mechanically and electrically connected to the patterned metal on the insulating layer using solder or conductive layer adhesive.

  In an alternative embodiment, the logic element may be an optical element. In such cases, some or all of the connectors and conductors described herein may be optically transmissive rather than electrically transmissive. Suitable optical connectors and / or light guides can include optical fibers and / or waveguides.

  The embodiments described herein are illustrative of compositions, structures, systems and methods having elements corresponding to those of the claimed invention. The description provided herein enables one skilled in the art to make and use embodiments having alternative elements that likewise correspond to the elements of the invention recited in the claims. Accordingly, the scope of the present invention includes compositions, structures, systems, and methods that do not depart from the literal meaning of the claims and other structures and systems that do not substantially differ from the literal meaning of the claims. And a method. Although only specific features and embodiments have been illustrated and described herein, many variations and modifications can be made by those skilled in the art. The appended claims encompass all such variations and modifications.

It is a side view which shows an intermediate product typically. FIG. 2 is a side view schematically showing a frame assembly according to an embodiment of the present invention formed from the intermediate product of FIG. 1. FIG. 3 is a cross-sectional perspective side view showing the frame assembly of FIG. 2 and logic elements joined to the frame assembly according to one embodiment of the present invention. It is a side view showing typically the interconnection structure concerning one embodiment of the present invention. FIG. 5 is a side view schematically illustrating an interconnect structure made from the interconnect structure of FIG. 4 according to one embodiment of the present invention. It is a side view showing typically the interconnection structure concerning one embodiment of the present invention. 1 is a side view schematically showing a frame assembly having a metallized layer and an insulating layer according to an embodiment of the present invention. It is a top view which shows typically the some flame | frame assembly which concerns on one Embodiment of this invention. It is a side view showing typically the interconnection structure concerning one embodiment of the present invention.

Claims (6)

An interconnect structure (2), wherein the interconnect structure (2)
(A) a first insulating web (38) having a first surface and a second surface;
(B) a logic element (40) secured to a second surface of the first insulating web (38) ;
(C) a frame assembly (37) for supporting said first insulating web (38) by a first insulating adhesive layer (39) ,
(C1) a frame base (12) having an inwardly facing surface defining a first surface (14) , a second surface (16) and a frame opening (36) , wherein said frame opening ( 36) have extending beauty through the frame base (12), a frame base (12) of said at least part of the logic element (40) is disposed in the opening,
(C2) the frame base (12) a first surface (14) a first conductive layer disposed on a (18) and Nde containing the logic element (40) is a first insulating adhesive layer ( 39) a frame assembly (37) secured to the second surface of the first insulating web (38) via
(D) a first connector (53) operable to allow the logic element (40) to communicate with the first conductive layer (18) through the interior thereof;
And
The frame assembly (37) includes a first frame insulating layer (22) disposed between the first surface (14) of the frame base (12) and the first insulating web (38). In addition, the first frame insulating layer (22) includes a first surface (24) and a second surface (26);
Said frame assembly (37),
A second frame insulating web (62) having a first surface and a second surface, wherein the first insulating web (38) has a second insulating adhesion to the second frame insulating web (62). A second frame insulating web (62) secured by a layer (63);
A second frame connector between a second conductive layer disposed on the first insulating web (38) and a conductor disposed on the second frame insulating web (62);
Further including an interconnect structure. The frame assembly (37) further comprises a contact (56) between a second conductive layer disposed on the first insulating web (38) and the first conductive layer (18). Interconnect structure. The interconnect structure of claim 1 or claim 2, wherein the first insulating web (38) is a polymer membrane. The interconnect structure according to any one of claims 1 to 3, wherein the frame base (12) is formed of a material selected from a metal, a ceramic or a polymeric material. The first insulation web (38) is supported via first insulating adhesive layer (39) and the frame opening of the interconnect structure of any one of claims 1 to claim 4 (36) A product comprising a logic element (40) disposed therein. The product of claim 5, wherein the logic element (40) is an optical element, the frame connector and the element connector are optically transmissive, and the frame conductive layer and the insulating web conductive layer include a waveguide.

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