KR20090105860A - Method of making demountable interconnect structure - Google Patents

Abstract

PURPOSE: A method of making a demountable interconnect structure is provided to remove inferior electronic device from interconnection structure or arbitrary inferiority remaining part. CONSTITUTION: A method of making a demountable interconnect structure is comprised of the steps: coating a first metal layer(24) on an electronic device including more than one I/O contact unit(18); locating the first metal layer on the surface t of I/O contact unit; coating a disposable layer(26) on the electronic device so that it is adjacent to the first metal layer; coating a bonding layer(16) on the electronic device or a base insulation layer(10); and fixing the contact layer on the base insulation layer by using the bonding layer.

Description

METHOD OF MAKING DEMOUNTABLE INTERCONNECT STRUCTURE}

This application is a partial continuing application of pending US patent application Ser. No. 11 / 766,356, filed June 21, 2007.

The present invention includes embodiments relating to the assembly of interconnect structures. Embodiments of the present invention relate to a method of recovering chips or other electrical components from an interconnect structure.

Bonding electronic devices, such as semiconductor chips, discrete passives, BGA carriers, or other electrical devices, onto a printed circuit board, substrate, interconnect structure, or flex circuit is generally accomplished by soldering or adhesives. Is done. In an area array attach assembly, electrical connections are made by raising the temperature to reflow the solder that solidifies upon cooling. In applications where the coefficient of thermal expansion (CTE) of the electronic device is hardly matched to the CTE of the substrate to which the electronic device is attached, thermal cycling stresses the solder joint and destroys solder fatigue. may cause fatigue failure. One way to overcome this problem is to reduce the stress on the solder joint by wrapping the solder joint with a polymer resin underfill, such as a filling epoxy. These underfills can be applied by dispensing the liquid resin onto one or more sides of the part so that the resin flows down the part by osmotic action.

High temperature sensitive electronic devices such as 200 ° C. should not use high temperature thermoplastic bonding materials. In addition, low temperature thermoplastics may not be exposed to later processing steps, such as curing, or to certain assembly steps above the melting or softening temperature. Thus, thermosetting adhesives are used in the treatment of such electronic devices, since the thermosetting adhesives can be cured at relatively low temperatures (<200 ° C.) and are also stable at higher temperatures during subsequent processing steps or in the use environment. to be. In addition, lower temperatures of adhesion and bonding are desirable because zero stress points are established at the bonding temperature, and lower bonding temperatures lower the stress of the interconnect assembly at normal operating temperatures.

If a large number of electronic devices are attached to a common substrate and one of these devices is found to be bad after soldering and underfill hardening, then generally the bad device is removed and replaced with a new portion, thereby replacing the substrate and other electrons located on the substrate. It is preferable to use a device. A problem associated with the use of thermoset underfill resins is that the thermoset resin cannot be remelted at normal processing temperatures, so that a defective electronic device cannot be replaced and the entire circuit must be discarded. Thus, the use of low stress thermoset adhesives at low processing temperatures results in an irreparable treatment step. In addition, reworkable thermoplastics that can be remelted require high temperature treatment, resulting in high stress structures that are incompatible with some uses.

Similar problems also arise in embedded chip applications where the interconnect structure is directly attached to the surface of the electronic component. In these applications, the use of thermoplastic adhesives to bond electronic components to interconnect structures results in excessive component stress and / or assembly temperature due to excessive thermoplastic melt temperatures or low thermoplastic melt temperatures. Restrict. In addition, the thermoplastic adhesive may become liquid during bonding of the chip to the film, causing the chip to move during processing. The use of thermoset adhesives for these applications can reduce stress and increase the operating and assembly temperature ranges, but recovery of electronic components is extremely difficult, if not impossible.

In the current embedded chip process, called Embedded Chip Build-Up (ECBU) or Chips First Build-Up (CFBU) technology, bare chips do not require solder bonding or wirebonding and do not require peripheral or peripheral I / O pads. Or packaged into a high density interconnect structure by an array of I / O pads distributed over the top surface. The ECBU or CFBU process can be used to form chip carriers that interconnect complex semiconductor chips to larger contact pads that are compatible with board level assemblies, such as printed circuit boards. These high-end chips cost hundreds of dollars. Since all complex interconnect structures have processing drawbacks such as electrical short and / or open, they also have inherent yield losses. In conventional flip chip or wire bonded chip carrier assemblies, the interconnect structures are fully fabricated and electrically tested before assembling expensive chips. Thus, poor interconnect structures do not cause expensive chip losses. In the ECBU process, chips are bonded to the interconnect structure prior to fabrication of the interconnect structure, so that potentially good chips can be broken by a bad package.

In one embodiment, the present invention provides a method of manufacturing an interconnect structure. The first metal layer is applied to the electronic device. The electronic device includes at least one I / O contact and the first metal layer is located on the surface of the I / O contact. A removable layer is applied to the electronic device. The removable layer is adjacent to the first metal layer. An adhesive layer is applied to the electronic device or base insulating layer. The adhesive layer fixes the electronic device to the base insulating layer. The first metal layer and the removable layer are located between the electronic device and the base insulating layer.

In one embodiment, a method of manufacturing an interconnect structure includes applying a first metal layer to a base substrate. The base substrate includes at least one contact pad, and the first metal layer is disposed on the surface of the contact pad. The removable layer is disposed on the base substrate. The removable layer is adjacent to the first metal layer. The conductive element electrically connects I / O contacts located on the electronic device to the contact pad vias. The conductive element is secured to the first metal layer. The underfill layer is disposed between the electronic device and the base substrate.

The present invention includes embodiments relating to the manufacture of electrical components or interconnect structures. The invention also includes embodiments of a method of recovering a chip or other electrical device from the component. A method is provided for recovering an undamaged electronic device such as a chip from a defective interconnect structure or package. These methods may be useful in processes associated with resin underfill and other embedded chip technologies. And, these methods may be used for applications that want to withdraw electronic devices from interconnect structures or packages.

The electronic component can include a base insulating layer having a first surface and a second surface, and an electronic device having a first surface and a second surface. The electronic device is fixed to the base insulating layer. The volume is defined by the first surface of the electronic device and the second surface of the base insulating layer. Within this volume there may be an adhesive layer, a first metal layer, a removable layer. Other layers and materials may optionally be disposed in this volume, for example a second metal layer may be disposed in this volume.

With regard to the base insulating layer, suitable materials for use may include one or more of polyimide, polyetherimide, benzocyclobutene (BCB), liquid crystal polymer, bismaleimide-triazine resin, epoxy or silicone. have. Commercial materials suitable for use as the base insulating layer include KAPTON H polyimide or KAPTON E polyimide (produced by EI du Pont de Nemours & Co.), APICAL AV polyimide (produced by Kanegafugi Chemical Industry Company), UPILEX polyimide (UBE Industries, Ltd.) and ULTEM polyetherimide (manufactured by General Electric Company). In the illustrated embodiment, the base insulating layer is fully cured as KAPTON H polyimide.

The base insulating layer can form an interconnect structure, a flex circuit, a circuit board or other structure. The interconnect structure carries one or more electronic devices and is interconnected with these devices. In one embodiment, the optional properties for the base insulating layer include elastic modulus and thermal and humidity expansion coefficients that provide a minimum change in size during processing. In order to maintain flexibility, the thickness of the base insulating layer can be minimized. The base insulating layer must have sufficient rigidity (due to thickness, support structure or material properties) to selectively support the metallization layer on the first and second surfaces and to maintain dimensional stability through subsequent processing steps. .

For the thickness of the base insulating layer, an appropriate thickness may be selected by referring to the end user application, the number and type of electronic devices, and the like. This thickness may be greater than about 10 μm. This thickness may be less than about 50 μm. In one embodiment, the base insulating layer ranges from about 10 μm to about 20 μm, from about 20 μm to about 30 μm, from about 30 μm to about 40 μm, from about 40 μm to about 50 μm or at a thickness greater than 50 μm. Has In one embodiment where the base insulating layer is a circuit board, the appropriate thickness may be based on the number of layers in the circuit board. The number of circuit board layers is generally about 2 to about 50, and the thickness of each layer is about 100 mu m.

The adhesive layer is a thermosetting adhesive. Examples of suitable adhesives are thermoset polymers. Suitable thermosetting polymers may include epoxies, silicones, acrylates, urethanes, polyetherimides or polyimides. Suitable commercial adhesives include polyimides such as CIBA GEIGY 412 (manufactured by Ciba Geigy), AMOCO AI-10 (manufactured by Amoco Chemicals Corporation) and PYRE-MI (manufactured by E.I. du Pont de Nemours & Co.). CIBA GEIGY 412 has a glass transition temperature of about 360 ° C. Other suitable adhesives may include thermoplastic adhesives, water cure adhesives, air cure adhesives and radiation cure adhesives.

The adhesive layer may be applied to form a layer having a thickness greater than about 5 μm on the surface of the base insulating layer. In one embodiment, the adhesive layer ranges from about 5 μm to about 10 μm, from about 10 μm to about 20 μm, from about 20 μm to about 30 μm, from about 30 μm to about 40 μm, from about 40 μm to about 50 μm Range or thickness greater than 50 μm.

The adhesive layer may be applied to the base insulating layer by spin coating, spray coating, roller coating, meniscus coating, screen printing, stenciling, pattern printing deposition, jetting or other dispensing methods. have. In one embodiment, the adhesive is applied by dry film lamination. The adhesive layer may be applied to partially or completely cover the second surface of the base insulating layer. For example, the adhesive layer may be applied to an optional area on the base insulating surface, such as an electronic device mounting location, leaving other areas on the base insulating layer surface such as electrical contact pads or electrical test pads uncoated. This can be done by direct dispensing systems such as spraying or by screen printing standard assembly processing steps used to selectively apply stencil or solder mask resin onto a board, substrate or parts. The direct dispense process may deposit a layer having a thickness of less than about 50 μm, and the screen printing technique may form a deposited layer having a thickness greater than about 50 μm.

The adhesive layer may be applied to the electronic device after applying the removable layer and the first and second metal layers to the electronic device. Thus, the adhesive layer may be applied to the surface of the removable layer and to the surface of the first metal layer or the second metal layer. In one embodiment, the adhesive layer may be applied and dried on the electronic device in liquid form. The adhesive layer may be applied alone in liquid form or may be deposited, for example, as part of a solution mixed with a solvent. In one embodiment, a suitable liquid thermoset polymer is 0.59% by weight of a 0.1% solution of CIBA GEIGY 412, FC 430® (surfactant from 3M Corporation), which is 24.8% by weight in a liquid solution containing 66.4% by weight N-mp. And 8.3% weight DMAC. The droplet of this material may be dispensed into the electronic device in an amount sufficient to produce a coating of about 200 μm to about 1000 μm. After the adhesive layer solution has been deposited, the material may be dried in a series of thermal steps such as 10 minutes to 20 minutes at about 150 ° C., 10 to 20 minutes at about 220 ° C., and 10 to 20 minutes at about 300 ° C. Can be. The number and duration of thermal steps and the temperature used will depend on the particular thermosetting polymer or other material used. This drying sequence removes the solvent from the thermosetting adhesive solution and leaves a completely dried layer of adhesive layer on the electronic device. Thermoset polymers are fully cross-linked, no longer soluble in solvent solutions and will not soften until exposed to extremely high temperatures.

In order to bond or secure the electronic device to the base insulating layer, the adhesive layer may be fully cured if necessary. A curing temperature below the melting temperature of the removable layer and the first and second metal layers should be used.

In one embodiment, the removable layer comprises a thermoplastic polymer. Suitable thermoplastic polymers for use in forming the removable layer include, but are not limited to, polyolefins, polyimides, polyetherimides, polyether ketones, polyether sulfones, silicones, siloxanes, or epoxies. Examples of suitable thermoplastic polymers include XU 412 (available from Ciba Geigy), ULTEM 1000 and ULTEM 6000, polyetherimide resins from GE Plastics, VITREX, polyether ether ketone from Victrex, XU 218, polyether sulfone from Ciba Geigy, Union Carbide UDEL 1700, a polyether sulfone.

Suitable methods of applying the removable layer to electronic devices include spray coating, spin coating, roll coating, meniscus coating, dip coating, transfer coating, jetting, drop dispensing, patterns Print deposition or dry film laminating. The removable layer may have a thickness greater than about 5 μm. In one embodiment, the removable layer ranges from about 5 μm to about 10 μm, from about 10 μm to about 20 μm, from about 20 μm to about 30 μm, from about 30 μm to about 40 μm, from about 40 μm to about 50 μm. Thickness or a thickness in the range exceeding about 50 μm. In other embodiments, the removable layer has a thickness of less than about 100 μm.

The removable layer can be applied to the electronic device while the electronic device is in the form of a single part or when the electronic device is in panel or wafer format. For example, if the electronic device is a semiconductor chip, the removable layer may be applied after wafer level or wafer processing is complete and after wafer sawing. The wafer may be sawed into two or more individual chips using semiconductor wafer dicing equipment. These chips can be rinsed to eliminate sawing debris. Alternatively, the removable layer can be applied directly onto the singulated chip after wafer sawing. Once the removable layer is applied at the wafer level, it can be deposited onto one wafer by spin coating or spray coating. Once the removable layer is applied to the unitary chip, spray coating or drop dispensing can apply the removable layer. In small packaged electronic devices, such as area array chip scale components, in which the electronic device can be fabricated in a panel having a plurality of devices processed together, the removable layer is roll coated, meniscus. It can still be applied to the device in the panel via a coating or other batch application method.

The removable layer is applied to partially cover the first surface of the electronic device so that the I / O contacts are not coated. If desired, additional regions on the electronic device may be left uncoated. This may be accomplished by stencil or screen printing standard assembly processing steps used to selectively apply solder mask resin onto a direct dispense system or board, substrate, or components, such as spraying. The removable layer can be applied to the electronic device before or after applying the first and second metal layers to the electronic device.

If regions on the electronic device other than the I / O contacts remain uncoated by the removable layer, the corresponding additional regions on the second surface of the base insulating layer are left uncoated by the adhesive layer. Specifically, the adhesion layer should be applied to an optional area of the electronic device mounting location on the base insulating layer, so that the area on the first surface of the electronic device that is not coated with the removable layer or the first metal layer is such that the electronic device is insulated from the base. It is placed in contact with the layer and is not in contact with the adhesive when bonded to the base insulating layer.

In one embodiment of forming the removable layer, the thermoplastic polymer is dried after being deposited on the electronic device in liquid form. The thermoplastic polymer may be applied in liquid form or may be deposited, for example, as part of a liquid solution mixed with a solvent. In one embodiment, a suitable solution is 4.1%, 27.3% anisole and 66.1% γ-butyorolactone (GBL) of 2.5% by weight of a solution of dimethyl acetamide (DMAC). It is formed by adding the CIBY GEIGY XU 412 together. The volume of this material can be dispensed onto the electronic device in a sufficient amount to produce a coating having a thickness in the range of about 100 μm to about 1000 μm. After the liquid thermoplastic polymer is deposited, the material can be dried in sequential thermal steps. Examples of suitable thermal steps may be 10-20 minutes at about 150 ° C, 10-20 minutes at about 220 ° C and 10-20 minutes at about 300 ° C. The number and duration of thermal steps and the temperature used will depend on the particular thermoplastic polymer employed. This drying sequence removes the solvent from the thermoplastic polymer solution and leaves a completely dried layer of thermoplastic polymer on the electronic device, forming a removable layer.

Another factor to consider is the pressure exerted on the parts during curing. Of course, higher pressures will create thinner bondlines. If more pressure is required than a sufficiently thick bondline requires, spacer material can be added to the adhesive to control the bondline thickness. The spacer material may be more functionally selected as long as it can have desirable thermal conductivity and electrical resistivity as intrinsic properties.

If the removable layer is a curable material, the removable layer may be cured after it is formed. The removable layer can be thermally cured by radiation or a combination of heat and radiation. Suitable radiation can include ultraviolet (UV) light, electron beams and / or microwaves. The cured removable layer is sufficiently transparent at visible wavelengths so that automated vision systems at wafer sawing and chip pick and place can distinguish wafer saw lanes. This transparency enables alignment of chips or other electronic devices during alignment and placement during wafer sawing. In addition, the cured removable layer should allow laser drilling at the wavelength used to remove the vias through the base insulating layer. For example, the cured removable layer may preferably be laser drilled.

After application of the adhesive layer, the adhesive layer can be cured. The adhesive layer is partially cured until the adhesive is at the B state point, where the adhesive layer is not fully cured but is sufficiently stable for further processing. The adhesive layer can be cured thermally or by a combination of heat or radiation. Suitable radiation may include UV light and / or microwaves. If volatiles are present from the adhesive during curing, a partial vacuum may be used to remove these materials.

One or more first metal layers are applied to the first surface of the electronic device. Specifically, each first metal layer is applied to the surface of the I / O contact located on the electronic device. Each first metal layer has a first surface and a second surface, the first surface of the first metal layer being located directly on the I / O contact. The perimeter of each first metal layer substantially corresponds to the perimeter of the I / O contact where the first metal layer is deposited. In the finished interconnect structure, each first metal layer is located adjacent to the removable layer and has a thickness substantially equal to the thickness of the removable layer. The first metal layer is lead, silver, tin, platinum, copper, lanthanum; And / or arsenic, phosphorus or sodium; Or a combination of two or more thereof. In a preferred embodiment, the first metal layer comprises lead.

One or more second metal layers may also be applied to the first surface of the electronic device. Each second metal layer is applied to a second surface of the first metal layer. The perimeter of each second metal layer substantially corresponds to the perimeter of the first metal layer and the I / O contact on which the second metal layer is deposited. In the finished interconnect structure, each second metal layer is located adjacent to the removable layer, and the combined thickness of the first and second metal layers is substantially the same as the thickness of the removable layer. The second metal layer may be made of lead, copper, silver, cadmium, tin, thallium, zinc or a combination of two or more thereof. In addition, the first and / or second metal layers may be silver-lead, tin-copper, tin-silver, lead-silver, arsenic-cadmium, lead-cadmium, platinum-cadmium, copper-lead, lanthanum-tin, phosphorus-thallium And binary systems such as platinum-lead, lead-zinc and platinum-thallium.

Suitable methods of applying the first and second metal layers to the electronic device include plating, evaporation and sputtering. The first and second metal layers may be applied to the electronic device either before or after applying the removable layer to the electronic device, respectively.

Referring to FIG. 1A, in one embodiment of the present invention, the base insulating layer 10 has a first surface 12 and a second surface 14. The base insulating layer is secured to the frame structure (not shown) to provide dimensional stability to the insulating layer during processing. The base insulating layer is formed of an electrically insulating material. In addition, the base insulating layer may be a polymer film to which the electrically insulating material can be fixed.

As shown in FIG. 1B, the adhesive layer 16 may be applied to the second surface of the base insulating layer. The adhesive layer may be bonded to the electronic device 18 (see FIG. 1 (c)). Thus, the adhesive layer can fix or bond the electronic device to the base insulating layer.

As shown in FIG. 1C, the electronic device has a first surface 20 and a second surface 22. The first surface of the electronic device may be the active surface of the device where one or more I / O contacts 23 are located. Examples of I / O contacts that may be located on an electronic device include pads as shown in the illustrated embodiment. Passivation layer 21 may be deposited on at least a portion of the first surface of the electronic device. The passivation layer protects the active area of the electronic device and exposes the I / O contacts. The passivation layer may be made of benzocyclobutene (BCB), silicon oxide, silicon nitride or polyimide.

Suitable electronic devices may be packaged or unpackaged semiconductor chips, discrete passive or ball grid array carriers such as microprocessors, microcontrollers, video processors or application specific integrated circuits (ASICs). . In one embodiment, the electronic device is a semiconductor silicon chip with an array of I / O contact pads disposed on its first surface.

Referring to FIG. 1C, a plurality of first metal layers 24, a plurality of second metal layers 25, and a removable layer 26 are applied to the first surface of the electronic device. In one embodiment shown in FIG. 1C, the removable layer is applied to the first surface of the electronic device in an area not covered by the first metal layer or the second metal layer. In another embodiment, shown in FIG. 2A, a removable layer is applied over the entire first surface of the electronic device, thus covering the first and second metal layers. Alternatively, only the removable layer and the plurality of first metal layers can be applied to the electronic device shown in FIG. 2 (b). The electronic device assembly can then be assembled onto the base insulating layer.

In one embodiment, the active surface or first surface of the electronic device is arranged to be in contact with the second surface of the base insulating layer, such that the active surface of the electronic device having the removable layer and the first and second metal layers is in contact with the adhesive layer. (See Fig. 1 (d)). For example, the base insulating layer is a heating stage of an automated pick and place system that picks each electronic device (in this case a chip) from a tray of unified chips, such as a diced wafer or a waffle pack. may be located in the heated stage. The partially cured adhesive layer is heated so that the adhesive softens and is tacky but not cured. These chips are then arranged with the first surface facing down, so that the active surface of the chip is positioned opposite the second surface of the base insulating layer, whereby the I / O contacts of each chip are preferably Aligned with the starting point on the base insulating layer (see Fig. 1 (d)). These origins can be ink, patterned metal, through holes, or other features formed on the first or second surface of the base insulating layer.

In one embodiment shown in FIG. 3A, the removable layer and the plurality of first and second metal layers are applied to the first surface of the electronic device. The removable layer can be applied to the electronic device and cured as described in the first embodiment. An adhesive layer may be applied to the removable surface and the first surface of the electronic device on top of the first and second metal layers and used to bond the electronic device to the base insulating layer as shown in FIG. 3 (a). Suitable application methods are the same as described above.

Referring to FIG. 3B, the active or first surface of the electronic device having the removable layer, the first and second metal layers, and the adhesive layer can be positioned to contact the second surface of the base insulating layer. The base insulating layer was fixed to the frame structure (not shown) to provide dimensional stability to the insulating layer during processing. In an automated system, the base insulation layer is heated in an automated pick and place system that picks each electronic device (in this case a chip) from a tray of unified chips, such as a diced wafer or waffle pack. It may be located on a heated stage. The chips are heated so that the partially cured adhesive layer softens and is tacky, but not cured. These chips are then positioned such that the first surface of the electronic device is in contact with the second surface of the base insulating layer so that the I / O contacts of each chip are preferably aligned at the origin on the base insulating layer as described above. The adhesive layer can be fully cured as described above.

In order to recover the electronic device from the interconnect structure and the base insulating layer, the encapsulation step may be delayed until the final processing step. However, if the electronic device is left unencapsulated on the base insulating layer during processing, the base insulating layer may have a patterning problem due to the non-flatness of the unencapsulated surface.

The base insulating layer is fixed to the frame to provide dimensional stability to the base insulating layer during processing. Referring to FIG. 4, in one embodiment, the frame panel 30 has a first surface and a second surface 34. The frame panel has a surface that defines the aperture or opening 38 at each electronic device location on the base insulating layer (see FIGS. 4A and 4B).

The base insulating layer may be fixed to the frame panel shown in FIG. 5. The frame panel stabilizes the base insulating layer instead of or in addition to the frame structure described above during fabrication of the interconnect structure. In addition, the frame panel can increase the planarity of the unencapsulated surface of the base insulating layer during processing. The frame panel may be a relatively permanent part of the interconnect structure. As shown in FIG. 5 (a), the frame panel can be large enough to include a plurality of openings 38, where each opening is for a different electronic device location on the base insulating layer, and thus the frame panel. Provides stability and increased planarity to a plurality of electronic device locations. Alternatively, the frame panel may include a single opening and is sized to provide stability and increased planarity to one electronic device location on the base insulating layer.

Suitable frame panels may be formed of metal, ceramic or polymeric materials. Suitable polymeric materials may include polyimide or epoxy or epoxy mixtures. The polymeric material may include one or more reinforcing fillers. Such fillers may include fibers or small inorganic particles. Suitable fibers may be glass fibers or carbon fibers. Suitable particles may include silicon carbide, boron nitride or aluminum nitride. The frame panel may be a molten polymer structure. In one embodiment, the frame panel is a metal selected from titanium, iron, copper or tin. Alternatively, the metal may be stainless steel or an alloy or metal mixture such as Cu: Invar: Cu. The particular material from which the frame panel is formed may be selected for a particular design based on the desired coefficient of thermal expansion, rigidity or other desired mechanical properties. The frame panel may have a metal coating. Suitable coating metals may include nickel. The frame panel may have polymer corning. Suitable polymer coating materials may include polyimide, which may improve tack.

The frame structure and / or frame panel may stabilize the base insulating layer during processing. However, the use of frame structures or frame panels may not be required. For example, roll-to-roll processing may not require the use of frame structures or frame panels.

The frame panel may have a coefficient of thermal expansion (CTE) greater than about 10 ppm / ° C. The frame panel may have a coefficient of thermal expansion (CTE) of less than about 20 ppm / ° C. In one embodiment, the frame panel may have a thickness that is equal to or close to the thickness of the electronic device. In another embodiment, the frame panel may have a thickness much thicker than the thickness of the electronic device. In embodiments where a plurality of electronic devices having variable thicknesses are located at the electronic device site, the frame panel may have a thickness that is equal to or close to the thickness of the thickest electronic device or much thicker than the thickness of the thickest electronic device.

In one embodiment, the first surface of the frame panel is secured to the second surface of the base insulating layer (see FIGS. 5A and 5B). The base insulating layer may be bonded to the frame panel using the adhesive layer 40. Suitable adhesives for bonding the frame panel to the base insulating layer include the materials listed above as at least suitable adhesive materials. Suitable application methods include those listed below.

In one embodiment, the frame panel is secured to the base insulating layer before the electronic device is secured to the base insulating layer, as shown in FIG. 5 (c).

Also, if the adhesive layer used to bond the frame panel to the base insulating layer is the same as the adhesive layer used to bond the electronic device to the base insulating layer, the electronic device and the frame panel may be simultaneously placed on the base insulating layer and cured. This can simplify or reduce the number of processing steps. For example, as shown in FIG. 6, the second surface of the base insulating layer 14 is coated with a thermosetting adhesive layer 16, and the adhesive material is cured into a B-stage. The second surface of the base insulating layer is laminated to the first surface of the frame panel 30 as shown in FIG. 6 (b). An electronic device 18 having a removable layer and first and second metal layers is located on the second surface of the base insulating layer in the opening in the frame panel 30 (see FIGS. 6 (c) and 6 (d)). . The adhesive layer is fully cured to bond the frame panel and the electronic device to the base insulating layer.

Once the adhesive layer is applied to the first surface of the electronic device shown in FIGS. 3 (a) and 3 (b), the frame panel adhesive can be used to secure the first surface of the frame panel to the second surface of the base insulating layer. The frame panel adhesive layer 40 may be selectively applied to the area of the second surface of the base insulating layer in contact with the frame panel, or the frame panel adhesive may be applied to the first surface of the frame panel. Suitable adhesives for bonding the frame panel to the base insulating layer include at least the materials listed above as suitable adhesive materials. Suitable application methods include those listed above.

Each opening in the frame panel may be in a range from about 0.2 mm to about 5 mm larger in x and y dimensions than the electronic device. Multiples of this size may facilitate subsequent placement of the electronic device on the base insulating layer. Alternatively, the frame panel may be disposed on the base insulating layer after the electronic device is disposed on and / or bonded to the base insulating layer.

Referring to FIG. 7A, for example, the second surface of the base insulating layer is coated with an adhesive layer, and the adhesive is cured with a B-stage. An electronic device having a removable layer, a first metal layer and a second metal layer is located on the second surface of the base insulating layer shown in FIG. 7 (b). The second surface of the base insulating layer is laminated to the first surface of the frame panel as shown in Figs. 7 (c) and 7 (d). The electronic device is disposed in the opening in the frame panel. Finally, the adhesive layer is fully cured to bond the frame panel and the electronic device to the base insulating layer.

In one embodiment, the subassembly comprises a barrier coating disposed between the adhesive layer and the removable layer and between the adhesive layer and the first and second metal layers. The barrier coating may block the migration of reactive species from the adhesive layer to the removable layer, the first metal layer and the second metal layer, such that the adhesive layer does not react with the removable layer, the first metal layer and the second metal layer during processing. It can also be prevented. This reaction, if it occurs, may create a weak interface or defect between the adhesive layer and the removable layer or between the adhesive layer and the first or second metal layer. For example, the thermosetting adhesive layer may react with the thermoplastic material of the removable layer during high temperature treatments such as curing.

The barrier coating may be applied to the outer surface (top surface) of the removable layer and the first and second metal layers after the removable layer and the first and second metal layers have been applied to the electronic device. The barrier coating can be an organic or inorganic layer. In embodiments where an organic barrier coating is used, the barrier coating is applied to the base insulating layer or the electronic device by the method described above as being suitable for the application of an adhesive layer or a removable layer, including chemical vapor deposition, plasma deposition or reactive sputtering. Can be. In embodiments using an inorganic barrier coating, the barrier coating may be deposited by CVD, evaporation or sputtering, for example. The barrier coating may be deposited at the wafer level after wafer processing is completed and prior to wafer sawing. Alternatively, the barrier coating may be applied on the singulated chips after wafer sawing.

The barrier coating may comprise one or more organic materials selected from polyolefins, polyesters, or amorphous hydrogenated carbon. Other suitable barrier coatings may be formed of inorganic materials such as Ta ₂ O ₅ , Al ₂ O ₃ , Sb ₂ O ₃ , Bi ₂ O ₃ , WO ₃ or ZrO ₂ .

In one embodiment, an electrical connection between the electronic device and the base insulating layer is formed after the electronic device is bonded to the base insulating layer. Specifically, an electrical connection is made between an I / O contact located on the electronic device and an electrical conductor located on the base insulating layer.

Referring to FIG. 8, a suitable electrical conductor 41 that can be placed on the base insulating layer includes pads, pins, bumps, and solder balls. The electrical connection between the base insulating layer and the electronic device can be a structure selected based on the application specific parameters. For example, openings, holes, or vias 42 may be created in one or more first or second metal layers on the electronic device through the base insulating layer and the adhesive layer (see FIG. 8 (a)). Alternatively, if a removable layer is applied over the first metal layer and the second metal layer shown in FIG. 2A, the base insulating layer, the adhesive layer, and the removable layer may be applied to one or more first metal layers or second metal layers on the electronic device. Openings, holes, or vias 42 may be created. Vias may be formed using laser ablation, wet chemical etching, plasma etching or reactive ion etching. In one embodiment, the vias may be micro vias.

The diameter of the vias may be less than about 10 μm. In one embodiment, the diameter of the via exceeds about 10 μm to about 20 μm, about 20 μm to about 30 μm, about 30 μm to about 40 μm, about 40 μm to about 50 μm, or greater than about 50 μm. May have a range.

By forming vias using laser ablation techniques, the base insulating layer can be supported by the frame structure, which can be flipped over and placed in an automated laser system. The laser system may be programmed to laser remove the base insulating layer in the selected location. This process forms at least one blind via through the base insulating layer and the adhesive layer to the second metal layer deposited on the I / O contacts on the electronic device 18. If a second metal layer is not deposited on the I / O contacts, the vias will extend to the first metal layer. If desired, a de-smear or de-scum process may be performed that removes the remaining debris and residual adhesive layer in the vias after laser removal to expose the first or second metal layer on the electronic device. This step can be performed by reactive ion etching (RIE), plasma cleaning or wet chemical etching. If desired, a trace, a power plane, or a ground plane may be formed on the first surface of the base insulating layer.

Referring to FIG. 8 (b), reference numeral 44 is provided on the first surface of the base insulating layer 10 and inside the via extending to one or more first or second metal layers deposited on the I / O contacts on the electronic device. An electrically conductive material denoted as may be deposited. The electrically conductive material can be an electrically conductive polymer and can be deposited by spraying or screening. Examples of suitable electrically conductive materials are polyurethanes, epoxies, or polysulfones comprising metal particle fillers. Suitable metal particles include silver and gold. Other suitable metals are Al, Cu, Ni, Sn and Ti. Rather than a filled polymer material, inherently conductive polymers can be used. Suitable conductive polymers include polyacetylene, polypyrrole, polyaniline, polyfluorene, polynaphthalene, poly-p-phenylene vinylene. When the viscosity and stability problems are solved, the inherent conductive polymer may be filled with an electrically conductive filler to further improve the electrical conductivity.

If the conductive material is a metal, the conductive material may be deposited by a method comprising one or more of sputtering, distillation, electroplating, or electroless plating. In one embodiment, the exposed surface of the via extending to the first surface and the second metal layer of the base insulating layer may be metallized using a combined sputter plate and electroplating sequence. The base insulating layer is located within the vacuum sputter system, and the first surface and vias of the base insulating layer are exposed to the sputter system. The back sputtering step sputter etches the exposed second metal layer to remove residual adhesive material and native metal oxide. Also, the back sputtering step etches into the surface of the base insulating layer. Although etching of the base insulating layer increases metal adhesion to the first surface of the base insulating layer, sputter etching of the first metal layer or the second metal layer reduces the contact resistance of the subsequent metallization step.

As shown in FIG. 8 (b), a seed metal layer 44 is sputter deposited on the first surface of the base insulating layer, sidewalls defining the vias, and the exposed first or second metal layer. It is also possible to use double metal systems comprising barrier metals such as Ti or Cr and non-barrier metals such as Cu or Au. The barrier metal may be plated to a thickness in the range of about 1000 microns to about 3000 microns and the non-barrier metal may be plated to a thickness in the range of about 0.2 microns to about 2.0 microns. The metal deposition step may form a metal interconnect on the first surface or non-component side of the base insulating layer.

After the sputtering step, as shown in Fig. 8C, a relatively thick non-barrier seed metal layer is electroplated on the first surface of the base insulating layer. Suitable metallization patterning processes may include semi-additive or pattern plate-up processes as shown in FIG. 8. The seed metal layer on the surface of the base insulating layer including the via sidewalls is electroplated with metal to form a plating layer having a thickness in the range of about 0.5 μm to about 2 μm. A photomask material is deposited over the plating layer on the first surface of the base insulating layer and photopatterned to expose selected areas of the surface. The photomask material is removed from the area on the first surface of the base insulating layer that metals such as interconnect traces and vias are intended to retain. The area of the base insulating surface on which the metal is to be removed is left covered with photomask material. Referring to FIG. 8C, after the photomask material is patterned, a thick metal is plated to a thickness ranging from about 2 μm to about 20 μm on the exposed areas of the first surface of the insulating layer. Since the plated-up metal has sidewalls along the straight sidewalls of the patterned photoresist, the photoresist thickness should be thicker than the thickness of the plated metal. After thicker metal plating, residual photomask material is removed, and the exposed areas of the resulting thin seed metal are removed by a plurality of wet metal etch baths that remove the plated and sputtered metals, as shown in FIG. The desired metallization pattern remains as shown in d).

In one sequence, a subtractive metal patterning process is used. In this method, the plating layer is plated on a thick layer having a thickness based on the circuit requirements of the electronic component in the range of about 2 μm to about 20 μm. A photomask material is deposited over the first surface of the base insulating layer and then photopatterned to expose selected areas of the surface. The area on the first surface of the base insulating layer intended to retain metal, such as interconnect traces, second metal layer and vias, is covered with photoresist, and not the area of the surface of the base insulating layer intended to remove metal. A plurality of standard wet metal etch baths remove the plated and sputtered metal on the exposed base insulating layer surface regions, while the remaining regions are protected from the wet etchant by the masking material. After the end of the etching step, the remaining photoresist material is removed. When the photoresist material is removed, the desired metallization pattern appears as shown in Figure 8 (d). Electrical connections between the base insulating layer and the electronic device can also be formed using a solder process.

Previous process steps complete electrical connection with the first interconnect layer 48 and the I / O contacts of the electronic device. Interconnection with one or more complex electronic devices, including semiconductor chips such as microprocessors, video processors and Application Specific Integrated Circuits (ASICs) may require additional interconnect layers to fully route all of the required chip I / O contacts. It may be. In these electronic devices, one or more additional interconnect layers may be formed over the first surface of the base insulating layer. In simpler electronic devices with less routing complexity, only one interconnect layer may be required.

In one embodiment, an additional interconnect layer is formed by bonding an additional insulating layer 50 to the first interconnect layer. In one embodiment shown in FIG. 9A, the additional insulating layer has a first surface 52 and a second surface 54 and is coated with an additional adhesive layer 56. Adhesives suitable for use in the present invention include materials listed above as suitable adhesive materials. If the additional adhesive layer comprises a thermosetting material, after applying the additional adhesive layer to the additional insulating layer, the adhesive is cured to the B stage. In another embodiment, an additional adhesive layer may be applied to the first surface of the first interconnect layer. In another embodiment, the additional insulating layer may be applied in liquid form and cured in place on the first surface of the first interconnect layer.

Suitable methods for applying an additional adhesive layer to the first surface of the additional interconnect layer or the previous interconnect layer include spray coating, spin coating, roll coating, meniscus coating, dip coating, transition coating, spraying, and drop dispensing. Pattern printing deposition or dry film laminating. As shown in FIG. 9A, the additional adhesive layer 56 may have a thickness greater than about 5 μm. In one embodiment, the additional adhesive layer ranges from about 5 μm to about 10 μm, from about 10 μm to about 20 μm, from about 20 μm to about 30 μm, from about 30 μm to about 40 μm, from about 40 μm to about Have a thickness in the range of 50 μm or greater than 50 μm. In another embodiment, the adhesive layer may be a prefabricated self adhesive film applied to the surface of the additional insulating layer.

Referring to Figure 9 (b), the second surface of the additional insulating layer is positioned in contact with the first surface (the part free surface) of the base insulating layer. The adhesive layer 56 is fully cured to bond an additional insulating layer to the base insulating layer and the interconnect layer 48. In one embodiment, an additional insulating layer is laminated over the first surface of the base insulating layer using a heated vacuum lamination system.

The electrical conductor 41 on the additional insulating layer is electrically connected to the electrical conductor 41 on the base insulating layer. For example, vias can be formed through additional insulating and adhesive layers to selected electrical conductors on the base insulating layer, as shown in FIG. 9 (c). As described above, the same process steps used to form the vias in the first interconnect layer and deposit the electrically conductive material may be used to form the electrically conductive vias in the additional insulating and adhesive layers (FIG. 9 (d)). Reference).

In one embodiment, the first surface of the additional insulating layer is metallized using the metallization and patterning steps described above for the first interconnect layer to complete the second interconnect layer. The plurality of additional interconnect layers can be formed in a similar manner.

The plurality of interconnect layers help to define the interconnect assembly 60 as shown in FIGS. 9D and 10. The interconnect assembly has a first surface 62 and a second surface 64. The interconnect assembly may be completed by passivating any metal traces and coating the first surface of the assembly with dielectric or solder masking material 68 to define the contact pads used for assembly or package I / O contact. The package I / O contacts may have additional metal deposits such as Ti: Ni: Au applied to the exposed contact pads to provide more robust I / O contacts. Additional metal scavengers may be applied by electroless plating. I / O contact pads may have pins, solder spheres, or lead left on these pads or left when creating a pad array. 10 illustrates an interconnect assembly 60 having an array of solder spheres 69, such as a ball grid array. Other interconnect structures may be used. For example, the interconnect assembly may have an array of pins, such as for a pin grid array.

Upon completion of the interconnect structure, which may be an interconnect assembly or interconnect layer comprising a plurality of interconnect layers, a standard electrical test station determines whether all interconnections are correct. Correct means that the circuit is not open or shorted. If the test results indicate that the interconnect structure is bad or other components on the interconnect structure are bad, good electronic devices can be recovered from the bad package. Alternatively, if the electronic device is found to be bad, the bad device can be removed from the interconnect structure and replaced with a new one.

In one embodiment, the removable layer, the first metal layer and the second metal layer may each have a softening temperature or melting point. Each of the removable layer, the first metal layer and the second metal layer has a softening temperature or melting point between about 250 ° C and about 350 ° C. The electronic device may be recovered from the interconnect structure by heating the removable layer, the first metal layer and the second metal layer to a softening temperature or melting point. At this temperature, the electronic device released or removed from the base insulating layer and the interconnect structure can be recovered. The removable layer, the first metal layer and the second metal layer are exposed to a heat source for softening or melting the removable layer and the first and second metal layers. Using this technique, the interconnect structure can be stripped from the electronic device when the interconnect structure is securely held by the holding device. Suitable holding devices may use vacuum or mechanical clamps. The clamp may grip the edge of the interconnect structure and may remove or strip the interconnect structure from the electronic device.

The removable layer, the first metal layer and the second metal layer allow the electronic device to be recovered without damaging the electronic device or elements on its active surface. This is particularly relevant with recent semiconductor devices that use low K (dielectric) interlayer dielectrics because they have low mechanical strength and are damaged.

In another recovery method, the interconnect structure may be mounted on a heating stage where the secondary heat source locally heats the electronic device and the area surrounding the device. The removable layer, the first metal layer and the second metal layer are heated to the softening temperature or to the melting point. If the removable layer comprises a thermoplastic or thermoset polymer, the removable layer is softened by exposing the removable layer to this temperature, as long as the temperature determined by the material properties of the polymer is above the softening temperature or melting point of the first and second metal layers. Or melted.

In order for a functional and intact electronic device to be separated from the defective base insulating layer, the softening point or melting point temperature of the removable layer, the first metal layer and the second metal layer must be lower than the maximum damage threshold temperature of the electronic device. The maximum damage threshold temperature of an electronic device is the maximum temperature at which the electronic device (including any circuitry thereon) can be exposed without damaging the electronic device. Alternatively, if it is desired to remove a defective electronic device from a functional and intact base insulating layer, the softening point or melting point of the removable layer, the first metal layer and the second metal layer should be lower than the maximum damage threshold temperature of the base insulating layer. The maximum damage threshold temperature of the base insulating layer (including any circuit thereon) is the maximum temperature at which the base insulating layer can be exposed without damaging the components. Thus, from the interconnect structure, the bad electronic device or any bad residual parts can be removed.

In one embodiment, the interconnect structure is a flip chip or chip scale that utilizes a relatively fine pitch (about 50 μm to about 1000 μm) array of solder spheres to electrically connect the electronic device to the base substrate to define and form the interconnect structure. An electronic device. Referring to FIG. 11A, a circuit board or flexible interconnect structure including one or more interconnect layers has a first surface 81 and a second surface 82. A plurality of contact pads 83 may be deposited on the second surface of the base substrate, and passivation layer 84 may be deposited on at least a portion of the second surface of the Jay substrate. The passivation layer protects the electrical properties of the base substrate and exposes the contact pads. The passivation layer may be made of a solder mask material such as epoxy. A plurality of first metal layers 86, a plurality of second metal layers 87 and a removable layer 88 are applied to the second surface of the base substrate.

Referring to FIG. 11B, an electronic device in the state of flip chip or chip scale components 90, 90 ′ has a first surface 92 and a second surface 93. I / O contact pads 94 are located on the first surface of the flip chip or chip scale component. Conductive element 96 is disposed on the I / O contacts that electrically connect the I / O contacts to respective contact pads on the base substrate. The conductive element may consist of a metal, a conductive polymer or a polymer filled with conductive particles.

Referring to FIG. 11C, the electronic device is disposed on the base substrate, and the conductive element forms a mechanical attachment and electrical connection between the I / O contact on the electronic device and the corresponding contact pad located on the base substrate. If the conductive element consists of a polymer, adhesion is achieved by heating the polymer above the polymer curing temperature. Alternatively, if the conductive element is a metal, adhesion is achieved by heating the metal above its melting point. The underfill layer 98 may be disposed between the first surface of the electronic device and the second surface of the base substrate. The underfill layer encapsulates the conductive element after bonding to the substrate contact pad. Thus, the underfill is bonded to the removable layer and the first or second metal layer rather than the substrate. Applying the removable layer and the first and second metal layers below the electronic device mounting position allows the electronic device to be recovered after underfill curing has occurred. In one embodiment, the interconnect structure may be mounted on a heated stage. The secondary heat source locally heats the electronic device and the area surrounding the device. Removable layer connections, first and second metal layer connections, and solder connections, all of which attach the electronic device to the interconnect structure, are heated to their softening or melting point. This releases the removable layer, the first metal layer, the second metal layer and the electronic device, and allows the electronic device to be recovered from the mounting position without damaging the thermosetting underfill. The previous mounting position can be modified to remove residue or debris. Finally, new electronic devices with conductive elements can be mounted on the substrate, bonded to the substrate and underfilled to complete the replacement of the defective part.

Once the electronic device is removed from the interconnect structure, residual adhesive layers and electrically conductive material located within the vias may remain on the electronic device. The excess residual adhesive layer on the remaining electrically conductive material or electronic device surface may be removed by wet etching, plasma etching, chemical etching or reactive ion etching, and the remaining adhesive material may be removed by plasma etching, chemical etching or reactive ion etching. Can be. In addition, if the electrically conductive material is formed of a metal, the portion of the conductive material remaining on the electronic device may be removed by metal etching. If the electrically conductive material comprises a Cu or Ti: Cu bimetal structure, Cu can be etched by nitric acid leaving the thin Ti metallized in place. In addition, any portion of the first metal layer or the second metal layer remaining on the electronic device may be removed by metal etching.

After removing any residual adhesive layer, electrically conductive material, first metal layer and second metal layer from the electronic device, the device is in its original state and can be assembled to other interconnect structures.

Using the embodiments disclosed herein, a benefit may be gained in chip-on-flex, plastic high density interconnect (HDI), and high I / O count processor chips. In a chip-on-flex process, complex interconnect structures need to be fabricated after the electronic device is bonded to the base insulating layer. This is problematic in terms of the number of layers needed to route multiple chip I / O pads and the complexity of each interconnect layer needed. It has a failure rate per interconnect structure, such as about 2% to about 10%. The loss of yield of complex interconnect structures carries the risk of discarding expensive processor chips unless rework processes are performed. Recovery by one or more of the aforementioned methods is stable above normal operating temperatures that can withstand high solder reflow temperatures but provides a relatively low stress recovery process for recoverable bonds if the electronic component needs to be recovered from the interconnect structure. .

In one embodiment, encapsulation may be delayed until the final step to enable the recovery of the electronic device from the interconnect structure. After the interconnect layer is completed, a test of the interconnect structure is performed. If the interconnect structure and the electronic device are found to be free of defects, the area surrounding the electronic device may be encapsulated to protect the electronic device and the interconnect structure from moisture and thermo-mechanical stress. The base insulating layer and the exposed electronic device may be encapsulated with encapsulating material 70 to completely embed the base insulating layer and the electronic device (see FIG. 10). In another embodiment, the base insulating layer and the exposed electronic device may be partially encapsulated to embed the base insulating layer and the electronic device (see FIG. 10). In one embodiment, a potting or molding process is used for encapsulation. Suitable molding processes may include pour molding, transfer molding or compression molding. Preferably, a dam and fill encapsulation method is used.

Encapsulation materials that can be used include thermoplastic and thermoset polymers. Suitable aliphatic and aromatic polymers include polyetherimide, acrylate, polyurethane, polypropylene, polysulfone, polytetrafluoroethylene, epoxy, benzocyclobutene (BCB), room temperature vulcanizable (RVT) silicone and urethane, polyimide, poly Carbonate, silicone, and the like. In one embodiment, the encapsulating material is a thermoset polymer due to the relatively low curing temperatures available. The encapsulation material may comprise a filling material. The type, size and amount of filling material can be used to suit a variety of molding material properties such as thermal conductivity, coefficient of thermal expansion, viscosity and moisture absorption. For example, these materials may include particles, fibers, screens, mats or plates of inorganic particles. Suitable fill materials may include glass, silica, ceramics, silicon carbide, alumina, aluminum nitride, boron nitride, gallium, or other metals, metal oxides, metal carbides, metal nitrides, or metal silicides. Other suitable fill materials may include carbon based materials.

If a frame panel is used, the frame panel may be applied before attachment of the electronic device (see FIG. 6) and after attachment of the electronic device (see FIG. 7) or after completion of the interconnect assembly. In the latter method, the adhesive is applied to the major surface of the frame panel and bonded to the second surface of the interconnect assembly. In all these frame panel attachment methods, there may be a gap or moat area between the inner edges of the frame spanner opening and the outer edge of the electronic device disposed within the opening. This gap may be left unfilled or completely or partially filled with encapsulation material. The gap between the inner edges of the frame panel opening and the outer edge of the electronic device may be partially filled by about 10% to about 90%. The encapsulation material may be cured. In some embodiments, it may be desirable to cure the encapsulation material and the adhesive layer simultaneously.

After the base insulating layer and the exposed electronic device are encapsulated, the lead / heat release plate 72 may be bonded to the second surface of the electronic device for thermal protection to the electronic device. A lead / thermal spreader is bonded with a thermal interface material (TIM) 74. The lead / heat dissipation plate may also be bonded to the second surface of the frame panel using adhesive 76. Alternatively, the backside of the electronic device may be exposed to facilitate thermal movement during device operation in high power consumption devices having power consumption from about 5 Watts to about 100 Watts or higher.

Embodiments disclosed herein are embodiments of a configuration, structure, system, and method corresponding to the elements of the invention disclosed in the claims. The disclosure disclosed herein enables those skilled in the art to make and use embodiments having other elements that correspond to the elements of the invention disclosed in the claims. Accordingly, the scope of the present invention includes other configurations, systems, and methods that do not differ from the literal language of the claims, and that other configurations, systems, and methods have substantive differences from the literal languages of the claims. Include. Although only certain features and embodiments are shown and described herein, many modifications and variations can be made by those skilled in the art. The appended claims cover all such modifications and variations.

1A-1D are schematic side views of an electronic device bonded to a base insulating layer, in accordance with one embodiment of the present invention.

2 (a) is a schematic side view of an electronic device according to another embodiment of the present invention.

2B is a schematic side view of an electronic device according to another embodiment of the present invention.

3 (a) and 3 (b) are schematic side views of an electronic device bonded to a base insulating layer, in accordance with another embodiment of the present invention.

4A is a plan view of the frame panel.

4B is a schematic side view of the frame panel.

5 (a) and 5 (b) are schematic side views of a frame panel bonded to a base insulating layer, in accordance with another embodiment of the present invention.

5C is a schematic side view of an electronic device disposed in a frame panel on a base insulating layer, in accordance with another embodiment of the present invention.

6 (a) to 6 (d) are schematic side views of an electronic device bonded to a base insulating layer in a frame panel according to another embodiment of the present invention.

7A-7D are schematic side views of a frame panel and an electronic device bonded to a base insulating layer, in accordance with another embodiment of the present invention.

8A-8D are schematic side views of via formation and metallization of a base insulating layer, in accordance with one embodiment of the present invention.

9 (a) and 9 (b) are schematic side views of an additional base insulating layer bonded to an interconnect layer in accordance with another embodiment of the present invention.

9 (c) and 9 (d) are schematic side views of via formation and additional base insulators, in accordance with another embodiment of the present invention.

10 is a schematic side view of an interconnect assembly made in accordance with another embodiment of the present invention.

Figure 11 (a) is a schematic side view of an interconnect substrate according to another embodiment of the present invention.

Figure 11 (b) is a schematic side view of a two chip scale electronic device prior to placing on an interconnect substrate, in accordance with another embodiment of the present invention.

11C is a schematic diagram of a two chip scale electronic device mounted on an interconnect substrate, in accordance with another embodiment of the present invention.

Explanation of symbols for main parts of the drawings

10: base insulation layer

12: first surface of the base insulating layer

14: second surface of the base insulating layer

16: adhesive layer

18: electronic device

20: first surface of an electronic device

21: passivation layer

22: second surface of the electronic device

23: I / O contact

24: first metal layer

25: second metal layer

26: removable layer

30: frame panel

32: first surface of the frame panel

34: second surface of the frame panel

38: opening

40: adhesive layer

42: Via

44: electrically conductive material

48: first interconnect layer

50: additional insulation layer

52: first surface of the additional insulating layer

54: second surface of additional insulating layer

56: additional adhesive layer

60: interconnect assembly

62: first surface of an interconnect assembly

64: second surface of the interconnect assembly

69: solder sphere

70: encapsulation material

72: lead / heat dissipation plate

74: thermal interface material (TIM)

76: adhesive

80: base substrate

81: first surface of the base substrate

82: second surface of the base substrate

83: Contact Pad

84: passivation layer

86: first metal layer

87: second metal layer

88: removable layer

90, 90 ': electronic device

92: first surface of the electronic device

93: second surface of the electronic device

94: I / O Contact Pad

96: conductive element

98: underfill layer

Claims (10)

In the method of manufacturing the interconnect structure, Applying a first metal layer 24 to the electronic device 18, the electronic device 18 comprising at least one I / O contact 23, the first metal layer 24 being the I / O. Located on the surface of the contact 23- Applying a removable layer 26 to the electronic device 18, wherein the removable layer 26 is located adjacent to the first metal layer; Applying an adhesive layer 16 to the electronic device 18 or the base insulating layer 10, Fixing the electronic device 18 to the base insulating layer 10 using the adhesive layer 16, The first metal layer 24 and the removable layer 26 are located between the electronic device 18 and the base insulating layer 10. Method of manufacturing interconnect structures. The method of claim 1, The removable layer 26 and the first metal layer 24 do not damage the electronic device 18, do not damage the base insulating layer 10, or the electronic device 18 and the base insulating layer. (10) allows the electronic device 18 to be recovered from the base insulating layer 10 without damaging all of them. Method of manufacturing interconnect structures. The method of claim 1, Each of the removable layer 26 and the first metal layer 24 has a softening point or melting point temperature lower than the maximum damage threshold temperature of the electronic device 18, The method is Exposing the removable layer 26 and the first metal layer 24 to a temperature above their softening or melting point but below the maximum damage threshold temperature of the electronic device 18; Further comprising removing the electronic device 18 from the base insulating layer 10. Method of manufacturing interconnect structures. The method of claim 1, Each of the removable layer 26 and the first metal layer 24 has a melting point or softening point temperature lower than the maximum damage threshold temperature of the base insulating layer 10, The method is Exposing the removable layer 26 and the first metal layer 24 to a temperature above their melting point or softening point but below the maximum damage threshold temperature of the base insulating layer 10; Further comprising removing the electronic device 18 from the base insulating layer 10. Method of manufacturing interconnect structures. The method of claim 1, Further comprising applying a second metal layer 25 to the surface of the first metal layer 24, The second metal layer 25 is located adjacent to the removable layer 26. Method of manufacturing interconnect structures. The method of claim 5, wherein The removable layer 6, the first metal layer 24 and the second metal layer 25 do not damage the electronic device 18, do not damage the base insulating layer 10 or the electronic device ( 18 and allow the electronic device 18 to be recovered from the base insulating layer 10 without damaging both the base insulating layer 10 and the base insulating layer 10. Method of manufacturing interconnect structures. The method of claim 5, wherein The removable layer 26, the first metal layer 24 and / or the second metal layer 25 each have a softening point or melting point lower than the maximum damage threshold temperature of the electronic device 18, The method is Exposing the removable layer 26, the first metal layer 24 and / or the second metal layer 25 to a temperature higher than their softening or melting point but below the maximum damage threshold temperature of the electronic device 18; , Further comprising removing the electronic device 18 from the base insulating layer 10. Method of manufacturing interconnect structures. The method of claim 5, wherein The removable layer 26, the first metal layer 24 and / or the second metal layer 25 each have a softening point or melting point temperature lower than the maximum damage threshold temperature of the base insulating layer 10, The method is Exposing the removable layer 26, the first metal layer 24 and / or the second metal layer 25 to a temperature higher than their softening or melting point but below the maximum damage critical temperature of the base insulating layer 10. Wow, Further comprising removing the electronic device 18 from the base insulating layer 10. Method of manufacturing interconnect structures. In the method of manufacturing the interconnect structure, Applying the first metal layer 86 to the base substrate 80-the base substrate 80 includes at least one contact pad 83, and the first metal layer 86 is the contact pad 83. Located on the surface of-with, Applying a removable layer 88 to the base substrate 80, wherein the removable layer 88 is located adjacent to the first metal layer 86; Electrically connecting an I / O contact pad 94 located on an electronic device 90 to the at least one contact pad 83 via a conductive element 96, wherein the conductive element 96 is configured to be the first member. Fixed to the metal layer 86-and, Applying an underfill layer 98 between the electronic device 90 and the base substrate 80. Method of manufacturing interconnect structures. The method of claim 9, Each of the removable layer 88 and the first metal layer 86 has a melting point or softening point temperature lower than the maximum damage threshold temperature of the base substrate 80, The method is Exposing the removable layer 88 and the first metal layer 86 to a temperature above their softening or melting point but below the maximum damage threshold temperature of the base substrate 80; Removing the electronic device 90 from the base substrate 80 Method of manufacturing interconnect structures.

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